1 //===-- AMDGPUInstrInfo.cpp - Base class for AMD GPU InstrInfo ------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Implementation of the TargetInstrInfo class that is common to all
12 /// AMD GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUInstrInfo.h"
17 #include "AMDGPURegisterInfo.h"
18 #include "AMDGPUTargetMachine.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 
23 using namespace llvm;
24 
25 #define GET_INSTRINFO_CTOR_DTOR
26 #define GET_INSTRINFO_NAMED_OPS
27 #define GET_INSTRMAP_INFO
28 #include "AMDGPUGenInstrInfo.inc"
29 
30 // Pin the vtable to this file.
31 void AMDGPUInstrInfo::anchor() {}
32 
33 AMDGPUInstrInfo::AMDGPUInstrInfo(const AMDGPUSubtarget &st)
34     : AMDGPUGenInstrInfo(-1, -1), ST(st) {}
35 
36 const AMDGPURegisterInfo &AMDGPUInstrInfo::getRegisterInfo() const {
37   return RI;
38 }
39 
40 bool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
41                                            unsigned &SrcReg, unsigned &DstReg,
42                                            unsigned &SubIdx) const {
43 // TODO: Implement this function
44   return false;
45 }
46 
47 unsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
48                                              int &FrameIndex) const {
49 // TODO: Implement this function
50   return 0;
51 }
52 
53 unsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
54                                                    int &FrameIndex) const {
55 // TODO: Implement this function
56   return 0;
57 }
58 
59 bool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
60                                           const MachineMemOperand *&MMO,
61                                           int &FrameIndex) const {
62 // TODO: Implement this function
63   return false;
64 }
65 unsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI,
66                                               int &FrameIndex) const {
67 // TODO: Implement this function
68   return 0;
69 }
70 unsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI,
71                                                     int &FrameIndex) const {
72 // TODO: Implement this function
73   return 0;
74 }
75 bool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI,
76                                            const MachineMemOperand *&MMO,
77                                            int &FrameIndex) const {
78 // TODO: Implement this function
79   return false;
80 }
81 
82 MachineInstr *
83 AMDGPUInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
84                                       MachineBasicBlock::iterator &MBBI,
85                                       LiveVariables *LV) const {
86 // TODO: Implement this function
87   return nullptr;
88 }
89 
90 void
91 AMDGPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
92                                     MachineBasicBlock::iterator MI,
93                                     unsigned SrcReg, bool isKill,
94                                     int FrameIndex,
95                                     const TargetRegisterClass *RC,
96                                     const TargetRegisterInfo *TRI) const {
97   llvm_unreachable("Not Implemented");
98 }
99 
100 void
101 AMDGPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
102                                      MachineBasicBlock::iterator MI,
103                                      unsigned DestReg, int FrameIndex,
104                                      const TargetRegisterClass *RC,
105                                      const TargetRegisterInfo *TRI) const {
106   llvm_unreachable("Not Implemented");
107 }
108 
109 bool AMDGPUInstrInfo::expandPostRAPseudo (MachineBasicBlock::iterator MI) const {
110   MachineBasicBlock *MBB = MI->getParent();
111   int OffsetOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
112                                                AMDGPU::OpName::addr);
113    // addr is a custom operand with multiple MI operands, and only the
114    // first MI operand is given a name.
115   int RegOpIdx = OffsetOpIdx + 1;
116   int ChanOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
117                                              AMDGPU::OpName::chan);
118   if (isRegisterLoad(*MI)) {
119     int DstOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
120                                               AMDGPU::OpName::dst);
121     unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
122     unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
123     unsigned Address = calculateIndirectAddress(RegIndex, Channel);
124     unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
125     if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
126       buildMovInstr(MBB, MI, MI->getOperand(DstOpIdx).getReg(),
127                     getIndirectAddrRegClass()->getRegister(Address));
128     } else {
129       buildIndirectRead(MBB, MI, MI->getOperand(DstOpIdx).getReg(),
130                         Address, OffsetReg);
131     }
132   } else if (isRegisterStore(*MI)) {
133     int ValOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
134                                               AMDGPU::OpName::val);
135     unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
136     unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
137     unsigned Address = calculateIndirectAddress(RegIndex, Channel);
138     unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
139     if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
140       buildMovInstr(MBB, MI, getIndirectAddrRegClass()->getRegister(Address),
141                     MI->getOperand(ValOpIdx).getReg());
142     } else {
143       buildIndirectWrite(MBB, MI, MI->getOperand(ValOpIdx).getReg(),
144                          calculateIndirectAddress(RegIndex, Channel),
145                          OffsetReg);
146     }
147   } else {
148     return false;
149   }
150 
151   MBB->erase(MI);
152   return true;
153 }
154 
155 MachineInstr *AMDGPUInstrInfo::foldMemoryOperandImpl(
156     MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
157     MachineBasicBlock::iterator InsertPt, int FrameIndex) const {
158 // TODO: Implement this function
159   return nullptr;
160 }
161 MachineInstr *AMDGPUInstrInfo::foldMemoryOperandImpl(
162     MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
163     MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const {
164   // TODO: Implement this function
165   return nullptr;
166 }
167 bool AMDGPUInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
168                                            ArrayRef<unsigned> Ops) const {
169   // TODO: Implement this function
170   return false;
171 }
172 bool
173 AMDGPUInstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
174                                  unsigned Reg, bool UnfoldLoad,
175                                  bool UnfoldStore,
176                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
177   // TODO: Implement this function
178   return false;
179 }
180 
181 bool
182 AMDGPUInstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
183                                     SmallVectorImpl<SDNode*> &NewNodes) const {
184   // TODO: Implement this function
185   return false;
186 }
187 
188 unsigned
189 AMDGPUInstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
190                                            bool UnfoldLoad, bool UnfoldStore,
191                                            unsigned *LoadRegIndex) const {
192   // TODO: Implement this function
193   return 0;
194 }
195 
196 bool AMDGPUInstrInfo::enableClusterLoads() const {
197   return true;
198 }
199 
200 // FIXME: This behaves strangely. If, for example, you have 32 load + stores,
201 // the first 16 loads will be interleaved with the stores, and the next 16 will
202 // be clustered as expected. It should really split into 2 16 store batches.
203 //
204 // Loads are clustered until this returns false, rather than trying to schedule
205 // groups of stores. This also means we have to deal with saying different
206 // address space loads should be clustered, and ones which might cause bank
207 // conflicts.
208 //
209 // This might be deprecated so it might not be worth that much effort to fix.
210 bool AMDGPUInstrInfo::shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1,
211                                               int64_t Offset0, int64_t Offset1,
212                                               unsigned NumLoads) const {
213   assert(Offset1 > Offset0 &&
214          "Second offset should be larger than first offset!");
215   // If we have less than 16 loads in a row, and the offsets are within 64
216   // bytes, then schedule together.
217 
218   // A cacheline is 64 bytes (for global memory).
219   return (NumLoads <= 16 && (Offset1 - Offset0) < 64);
220 }
221 
222 bool
223 AMDGPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
224   const {
225   // TODO: Implement this function
226   return true;
227 }
228 void AMDGPUInstrInfo::insertNoop(MachineBasicBlock &MBB,
229                                 MachineBasicBlock::iterator MI) const {
230   // TODO: Implement this function
231 }
232 
233 bool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const {
234   // TODO: Implement this function
235   return false;
236 }
237 
238 bool AMDGPUInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
239                                         ArrayRef<MachineOperand> Pred2) const {
240   // TODO: Implement this function
241   return false;
242 }
243 
244 bool AMDGPUInstrInfo::DefinesPredicate(MachineInstr *MI,
245                                       std::vector<MachineOperand> &Pred) const {
246   // TODO: Implement this function
247   return false;
248 }
249 
250 bool AMDGPUInstrInfo::isPredicable(MachineInstr *MI) const {
251   // TODO: Implement this function
252   return MI->getDesc().isPredicable();
253 }
254 
255 bool
256 AMDGPUInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
257   // TODO: Implement this function
258   return true;
259 }
260 
261 bool AMDGPUInstrInfo::isRegisterStore(const MachineInstr &MI) const {
262   return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_STORE;
263 }
264 
265 bool AMDGPUInstrInfo::isRegisterLoad(const MachineInstr &MI) const {
266   return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_LOAD;
267 }
268 
269 int AMDGPUInstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const {
270   const MachineRegisterInfo &MRI = MF.getRegInfo();
271   const MachineFrameInfo *MFI = MF.getFrameInfo();
272   int Offset = -1;
273 
274   if (MFI->getNumObjects() == 0) {
275     return -1;
276   }
277 
278   if (MRI.livein_empty()) {
279     return 0;
280   }
281 
282   const TargetRegisterClass *IndirectRC = getIndirectAddrRegClass();
283   for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
284                                             LE = MRI.livein_end();
285                                             LI != LE; ++LI) {
286     unsigned Reg = LI->first;
287     if (TargetRegisterInfo::isVirtualRegister(Reg) ||
288         !IndirectRC->contains(Reg))
289       continue;
290 
291     unsigned RegIndex;
292     unsigned RegEnd;
293     for (RegIndex = 0, RegEnd = IndirectRC->getNumRegs(); RegIndex != RegEnd;
294                                                           ++RegIndex) {
295       if (IndirectRC->getRegister(RegIndex) == Reg)
296         break;
297     }
298     Offset = std::max(Offset, (int)RegIndex);
299   }
300 
301   return Offset + 1;
302 }
303 
304 int AMDGPUInstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const {
305   int Offset = 0;
306   const MachineFrameInfo *MFI = MF.getFrameInfo();
307 
308   // Variable sized objects are not supported
309   assert(!MFI->hasVarSizedObjects());
310 
311   if (MFI->getNumObjects() == 0) {
312     return -1;
313   }
314 
315   Offset = MF.getSubtarget().getFrameLowering()->getFrameIndexOffset(MF, -1);
316 
317   return getIndirectIndexBegin(MF) + Offset;
318 }
319 
320 int AMDGPUInstrInfo::getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const {
321   switch (Channels) {
322   default: return Opcode;
323   case 1: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_1);
324   case 2: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_2);
325   case 3: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_3);
326   }
327 }
328 
329 // Wrapper for Tablegen'd function.  enum Subtarget is not defined in any
330 // header files, so we need to wrap it in a function that takes unsigned
331 // instead.
332 namespace llvm {
333 namespace AMDGPU {
334 static int getMCOpcode(uint16_t Opcode, unsigned Gen) {
335   return getMCOpcodeGen(Opcode, (enum Subtarget)Gen);
336 }
337 }
338 }
339 
340 // This must be kept in sync with the SISubtarget class in SIInstrInfo.td
341 enum SISubtarget {
342   SI = 0,
343   VI = 1
344 };
345 
346 static enum SISubtarget AMDGPUSubtargetToSISubtarget(unsigned Gen) {
347   switch (Gen) {
348   default:
349     return SI;
350   case AMDGPUSubtarget::VOLCANIC_ISLANDS:
351     return VI;
352   }
353 }
354 
355 int AMDGPUInstrInfo::pseudoToMCOpcode(int Opcode) const {
356   int MCOp = AMDGPU::getMCOpcode(
357       Opcode, AMDGPUSubtargetToSISubtarget(ST.getGeneration()));
358 
359   // -1 means that Opcode is already a native instruction.
360   if (MCOp == -1)
361     return Opcode;
362 
363   // (uint16_t)-1 means that Opcode is a pseudo instruction that has
364   // no encoding in the given subtarget generation.
365   if (MCOp == (uint16_t)-1)
366     return -1;
367 
368   return MCOp;
369 }
370