1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Interface definition of the TargetLowering class that is common
12 /// to all AMD GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
17 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
18 
19 #include "llvm/Target/TargetLowering.h"
20 
21 namespace llvm {
22 
23 class AMDGPUMachineFunction;
24 class AMDGPUSubtarget;
25 class MachineRegisterInfo;
26 
27 class AMDGPUTargetLowering : public TargetLowering {
28 protected:
29   const AMDGPUSubtarget *Subtarget;
30 
31   SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV,
32                                    const SDValue &InitPtr,
33                                    SDValue Chain,
34                                    SelectionDAG &DAG) const;
35   SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
36   SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
37   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
38   /// \brief Lower vector stores by merging the vector elements into an integer
39   /// of the same bitwidth.
40   SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
41   /// \brief Split a vector store into multiple scalar stores.
42   /// \returns The resulting chain.
43 
44   SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
45   SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
46   SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
47   SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
48   SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
49 
50   SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const;
51   SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
52   SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
53   SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
54 
55   SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
56 
57   SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
58   SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
59   SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
60   SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
61 
62   SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
63   SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
64   SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
65 
66   SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
67 
68 protected:
69   SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
70   SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
71   SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
72   SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
73   SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
74   SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
75   SDValue performCtlzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
76                              SDValue RHS, DAGCombinerInfo &DCI) const;
77   SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
78 
79   static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
80   static EVT getEquivalentLoadRegType(LLVMContext &Context, EVT VT);
81 
82   virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
83                                      SelectionDAG &DAG) const;
84 
85   /// Return 64-bit value Op as two 32-bit integers.
86   std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
87                                               SelectionDAG &DAG) const;
88   SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
89   SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
90 
91   /// \brief Split a vector load into 2 loads of half the vector.
92   SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
93 
94   /// \brief Split a vector store into 2 stores of half the vector.
95   SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
96 
97   SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
98   SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
99   SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
100   SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
101   void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
102                                     SmallVectorImpl<SDValue> &Results) const;
103   /// The SelectionDAGBuilder will automatically promote function arguments
104   /// with illegal types.  However, this does not work for the AMDGPU targets
105   /// since the function arguments are stored in memory as these illegal types.
106   /// In order to handle this properly we need to get the origianl types sizes
107   /// from the LLVM IR Function and fixup the ISD:InputArg values before
108   /// passing them to AnalyzeFormalArguments()
109   void getOriginalFunctionArgs(SelectionDAG &DAG,
110                                const Function *F,
111                                const SmallVectorImpl<ISD::InputArg> &Ins,
112                                SmallVectorImpl<ISD::InputArg> &OrigIns) const;
113   void AnalyzeFormalArguments(CCState &State,
114                               const SmallVectorImpl<ISD::InputArg> &Ins) const;
115   void AnalyzeReturn(CCState &State,
116                      const SmallVectorImpl<ISD::OutputArg> &Outs) const;
117 
118 public:
119   AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
120 
121   bool isFAbsFree(EVT VT) const override;
122   bool isFNegFree(EVT VT) const override;
123   bool isTruncateFree(EVT Src, EVT Dest) const override;
124   bool isTruncateFree(Type *Src, Type *Dest) const override;
125 
126   bool isZExtFree(Type *Src, Type *Dest) const override;
127   bool isZExtFree(EVT Src, EVT Dest) const override;
128   bool isZExtFree(SDValue Val, EVT VT2) const override;
129 
130   bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
131 
132   MVT getVectorIdxTy(const DataLayout &) const override;
133   bool isSelectSupported(SelectSupportKind) const override;
134 
135   bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
136   bool ShouldShrinkFPConstant(EVT VT) const override;
137   bool shouldReduceLoadWidth(SDNode *Load,
138                              ISD::LoadExtType ExtType,
139                              EVT ExtVT) const override;
140 
141   bool isLoadBitCastBeneficial(EVT, EVT) const override;
142 
143   bool storeOfVectorConstantIsCheap(EVT MemVT,
144                                     unsigned NumElem,
145                                     unsigned AS) const override;
146   bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
147   bool isCheapToSpeculateCttz() const override;
148   bool isCheapToSpeculateCtlz() const override;
149 
150   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
151                       const SmallVectorImpl<ISD::OutputArg> &Outs,
152                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
153                       SelectionDAG &DAG) const override;
154   SDValue LowerCall(CallLoweringInfo &CLI,
155                     SmallVectorImpl<SDValue> &InVals) const override;
156 
157   SDValue LowerDYNAMIC_STACKALLOC(SDValue Op,
158                                   SelectionDAG &DAG) const;
159 
160   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
161   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
162   void ReplaceNodeResults(SDNode * N,
163                           SmallVectorImpl<SDValue> &Results,
164                           SelectionDAG &DAG) const override;
165 
166   SDValue CombineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
167                                SDValue RHS, SDValue True, SDValue False,
168                                SDValue CC, DAGCombinerInfo &DCI) const;
169 
170   const char* getTargetNodeName(unsigned Opcode) const override;
171 
172   SDValue getRsqrtEstimate(SDValue Operand,
173                            DAGCombinerInfo &DCI,
174                            unsigned &RefinementSteps,
175                            bool &UseOneConstNR) const override;
176   SDValue getRecipEstimate(SDValue Operand,
177                            DAGCombinerInfo &DCI,
178                            unsigned &RefinementSteps) const override;
179 
180   virtual SDNode *PostISelFolding(MachineSDNode *N,
181                                   SelectionDAG &DAG) const = 0;
182 
183   /// \brief Determine which of the bits specified in \p Mask are known to be
184   /// either zero or one and return them in the \p KnownZero and \p KnownOne
185   /// bitsets.
186   void computeKnownBitsForTargetNode(const SDValue Op,
187                                      APInt &KnownZero,
188                                      APInt &KnownOne,
189                                      const SelectionDAG &DAG,
190                                      unsigned Depth = 0) const override;
191 
192   unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG,
193                                            unsigned Depth = 0) const override;
194 
195   /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
196   /// MachineFunction.
197   ///
198   /// \returns a RegisterSDNode representing Reg.
199   virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
200                                        const TargetRegisterClass *RC,
201                                        unsigned Reg, EVT VT) const;
202 
203   enum ImplicitParameter {
204     FIRST_IMPLICIT,
205     GRID_DIM = FIRST_IMPLICIT,
206     GRID_OFFSET,
207   };
208 
209   /// \brief Helper function that returns the byte offset of the given
210   /// type of implicit parameter.
211   uint32_t getImplicitParameterOffset(const AMDGPUMachineFunction *MFI,
212                                       const ImplicitParameter Param) const;
213 };
214 
215 namespace AMDGPUISD {
216 
217 enum NodeType : unsigned {
218   // AMDIL ISD Opcodes
219   FIRST_NUMBER = ISD::BUILTIN_OP_END,
220   CALL,        // Function call based on a single integer
221   UMUL,        // 32bit unsigned multiplication
222   BRANCH_COND,
223   // End AMDIL ISD Opcodes
224   ENDPGM,
225   RETURN,
226   DWORDADDR,
227   FRACT,
228   CLAMP,
229 
230   // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
231   // Denormals handled on some parts.
232   COS_HW,
233   SIN_HW,
234   FMAX_LEGACY,
235   FMIN_LEGACY,
236   FMAX3,
237   SMAX3,
238   UMAX3,
239   FMIN3,
240   SMIN3,
241   UMIN3,
242   FMED3,
243   SMED3,
244   UMED3,
245   URECIP,
246   DIV_SCALE,
247   DIV_FMAS,
248   DIV_FIXUP,
249   TRIG_PREOP, // 1 ULP max error for f64
250 
251   // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
252   //            For f64, max error 2^29 ULP, handles denormals.
253   RCP,
254   RSQ,
255   RSQ_LEGACY,
256   RSQ_CLAMP,
257   LDEXP,
258   FP_CLASS,
259   DOT4,
260   CARRY,
261   BORROW,
262   BFE_U32, // Extract range of bits with zero extension to 32-bits.
263   BFE_I32, // Extract range of bits with sign extension to 32-bits.
264   BFI, // (src0 & src1) | (~src0 & src2)
265   BFM, // Insert a range of bits into a 32-bit word.
266   FFBH_U32, // ctlz with -1 if input is zero.
267   MUL_U24,
268   MUL_I24,
269   MAD_U24,
270   MAD_I24,
271   TEXTURE_FETCH,
272   EXPORT,
273   CONST_ADDRESS,
274   REGISTER_LOAD,
275   REGISTER_STORE,
276   LOAD_INPUT,
277   SAMPLE,
278   SAMPLEB,
279   SAMPLED,
280   SAMPLEL,
281 
282   // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
283   CVT_F32_UBYTE0,
284   CVT_F32_UBYTE1,
285   CVT_F32_UBYTE2,
286   CVT_F32_UBYTE3,
287   /// This node is for VLIW targets and it is used to represent a vector
288   /// that is stored in consecutive registers with the same channel.
289   /// For example:
290   ///   |X  |Y|Z|W|
291   /// T0|v.x| | | |
292   /// T1|v.y| | | |
293   /// T2|v.z| | | |
294   /// T3|v.w| | | |
295   BUILD_VERTICAL_VECTOR,
296   /// Pointer to the start of the shader's constant data.
297   CONST_DATA_PTR,
298   SENDMSG,
299   INTERP_MOV,
300   INTERP_P1,
301   INTERP_P2,
302   PC_ADD_REL_OFFSET,
303   FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
304   STORE_MSKOR,
305   LOAD_CONSTANT,
306   TBUFFER_STORE_FORMAT,
307   ATOMIC_CMP_SWAP,
308   ATOMIC_INC,
309   ATOMIC_DEC,
310   LAST_AMDGPU_ISD_NUMBER
311 };
312 
313 
314 } // End namespace AMDGPUISD
315 
316 } // End namespace llvm
317 
318 #endif
319