1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Interface definition of the TargetLowering class that is common
12 /// to all AMD GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
17 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
18 
19 #include "llvm/Target/TargetLowering.h"
20 
21 namespace llvm {
22 
23 class AMDGPUMachineFunction;
24 class AMDGPUSubtarget;
25 class MachineRegisterInfo;
26 
27 class AMDGPUTargetLowering : public TargetLowering {
28 protected:
29   const AMDGPUSubtarget *Subtarget;
30 
31   SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV,
32                                    const SDValue &InitPtr,
33                                    SDValue Chain,
34                                    SelectionDAG &DAG) const;
35   SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
36   SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
37   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
38   /// \brief Lower vector stores by merging the vector elements into an integer
39   /// of the same bitwidth.
40   SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
41   /// \brief Split a vector store into multiple scalar stores.
42   /// \returns The resulting chain.
43 
44   SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
45   SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
46   SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
47   SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
48   SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
49 
50   SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const;
51   SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
52   SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
53   SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
54 
55   SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
56 
57   SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
58   SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
59   SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
60   SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
61 
62   SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
63   SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
64   SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
65 
66   SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
67 
68 protected:
69   SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
70   SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
71   SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
72   SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
73   SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
74   SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
75   SDValue performCtlzCombine(SDLoc SL, SDValue Cond, SDValue LHS, SDValue RHS,
76                              DAGCombinerInfo &DCI) const;
77   SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
78 
79   static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
80   static EVT getEquivalentLoadRegType(LLVMContext &Context, EVT VT);
81 
82   virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
83                                      SelectionDAG &DAG) const;
84 
85   /// Return 64-bit value Op as two 32-bit integers.
86   std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
87                                               SelectionDAG &DAG) const;
88   SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
89   SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
90 
91   /// \brief Split a vector load into a scalar load of each component.
92   SDValue ScalarizeVectorLoad(SDValue Op, SelectionDAG &DAG) const;
93 
94   /// \brief Split a vector load into 2 loads of half the vector.
95   SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
96 
97   /// \brief Split a vector store into a scalar store of each component.
98   SDValue ScalarizeVectorStore(SDValue Op, SelectionDAG &DAG) const;
99 
100   /// \brief Split a vector store into 2 stores of half the vector.
101   SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
102 
103   SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
104   SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
105   SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
106   SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
107   void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
108                                     SmallVectorImpl<SDValue> &Results) const;
109   /// The SelectionDAGBuilder will automatically promote function arguments
110   /// with illegal types.  However, this does not work for the AMDGPU targets
111   /// since the function arguments are stored in memory as these illegal types.
112   /// In order to handle this properly we need to get the origianl types sizes
113   /// from the LLVM IR Function and fixup the ISD:InputArg values before
114   /// passing them to AnalyzeFormalArguments()
115   void getOriginalFunctionArgs(SelectionDAG &DAG,
116                                const Function *F,
117                                const SmallVectorImpl<ISD::InputArg> &Ins,
118                                SmallVectorImpl<ISD::InputArg> &OrigIns) const;
119   void AnalyzeFormalArguments(CCState &State,
120                               const SmallVectorImpl<ISD::InputArg> &Ins) const;
121   void AnalyzeReturn(CCState &State,
122                      const SmallVectorImpl<ISD::OutputArg> &Outs) const;
123 
124 public:
125   AMDGPUTargetLowering(TargetMachine &TM, const AMDGPUSubtarget &STI);
126 
127   bool isFAbsFree(EVT VT) const override;
128   bool isFNegFree(EVT VT) const override;
129   bool isTruncateFree(EVT Src, EVT Dest) const override;
130   bool isTruncateFree(Type *Src, Type *Dest) const override;
131 
132   bool isZExtFree(Type *Src, Type *Dest) const override;
133   bool isZExtFree(EVT Src, EVT Dest) const override;
134   bool isZExtFree(SDValue Val, EVT VT2) const override;
135 
136   bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
137 
138   MVT getVectorIdxTy(const DataLayout &) const override;
139   bool isSelectSupported(SelectSupportKind) const override;
140 
141   bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
142   bool ShouldShrinkFPConstant(EVT VT) const override;
143   bool shouldReduceLoadWidth(SDNode *Load,
144                              ISD::LoadExtType ExtType,
145                              EVT ExtVT) const override;
146 
147   bool isLoadBitCastBeneficial(EVT, EVT) const override;
148 
149   bool storeOfVectorConstantIsCheap(EVT MemVT,
150                                     unsigned NumElem,
151                                     unsigned AS) const override;
152   bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
153   bool isCheapToSpeculateCttz() const override;
154   bool isCheapToSpeculateCtlz() const override;
155 
156   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
157                       bool isVarArg,
158                       const SmallVectorImpl<ISD::OutputArg> &Outs,
159                       const SmallVectorImpl<SDValue> &OutVals,
160                       SDLoc DL, SelectionDAG &DAG) const override;
161   SDValue LowerCall(CallLoweringInfo &CLI,
162                     SmallVectorImpl<SDValue> &InVals) const override;
163 
164   SDValue LowerDYNAMIC_STACKALLOC(SDValue Op,
165                                   SelectionDAG &DAG) const;
166 
167   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
168   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
169   void ReplaceNodeResults(SDNode * N,
170                           SmallVectorImpl<SDValue> &Results,
171                           SelectionDAG &DAG) const override;
172 
173   SDValue CombineFMinMaxLegacy(SDLoc DL,
174                                EVT VT,
175                                SDValue LHS,
176                                SDValue RHS,
177                                SDValue True,
178                                SDValue False,
179                                SDValue CC,
180                                DAGCombinerInfo &DCI) const;
181 
182   const char* getTargetNodeName(unsigned Opcode) const override;
183 
184   SDValue getRsqrtEstimate(SDValue Operand,
185                            DAGCombinerInfo &DCI,
186                            unsigned &RefinementSteps,
187                            bool &UseOneConstNR) const override;
188   SDValue getRecipEstimate(SDValue Operand,
189                            DAGCombinerInfo &DCI,
190                            unsigned &RefinementSteps) const override;
191 
192   virtual SDNode *PostISelFolding(MachineSDNode *N,
193                                   SelectionDAG &DAG) const = 0;
194 
195   /// \brief Determine which of the bits specified in \p Mask are known to be
196   /// either zero or one and return them in the \p KnownZero and \p KnownOne
197   /// bitsets.
198   void computeKnownBitsForTargetNode(const SDValue Op,
199                                      APInt &KnownZero,
200                                      APInt &KnownOne,
201                                      const SelectionDAG &DAG,
202                                      unsigned Depth = 0) const override;
203 
204   unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG,
205                                            unsigned Depth = 0) const override;
206 
207   /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
208   /// MachineFunction.
209   ///
210   /// \returns a RegisterSDNode representing Reg.
211   virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
212                                        const TargetRegisterClass *RC,
213                                        unsigned Reg, EVT VT) const;
214 
215   enum ImplicitParameter {
216     GRID_DIM,
217     GRID_OFFSET
218   };
219 
220   /// \brief Helper function that returns the byte offset of the given
221   /// type of implicit parameter.
222   uint32_t getImplicitParameterOffset(const AMDGPUMachineFunction *MFI,
223                                       const ImplicitParameter Param) const;
224 };
225 
226 namespace AMDGPUISD {
227 
228 enum NodeType : unsigned {
229   // AMDIL ISD Opcodes
230   FIRST_NUMBER = ISD::BUILTIN_OP_END,
231   CALL,        // Function call based on a single integer
232   UMUL,        // 32bit unsigned multiplication
233   RET_FLAG,
234   BRANCH_COND,
235   // End AMDIL ISD Opcodes
236   DWORDADDR,
237   FRACT,
238   CLAMP,
239 
240   // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
241   // Denormals handled on some parts.
242   COS_HW,
243   SIN_HW,
244   FMAX_LEGACY,
245   FMIN_LEGACY,
246   FMAX3,
247   SMAX3,
248   UMAX3,
249   FMIN3,
250   SMIN3,
251   UMIN3,
252   FMED3,
253   SMED3,
254   UMED3,
255   URECIP,
256   DIV_SCALE,
257   DIV_FMAS,
258   DIV_FIXUP,
259   TRIG_PREOP, // 1 ULP max error for f64
260 
261   // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
262   //            For f64, max error 2^29 ULP, handles denormals.
263   RCP,
264   RSQ,
265   RSQ_LEGACY,
266   RSQ_CLAMP,
267   LDEXP,
268   FP_CLASS,
269   DOT4,
270   CARRY,
271   BORROW,
272   BFE_U32, // Extract range of bits with zero extension to 32-bits.
273   BFE_I32, // Extract range of bits with sign extension to 32-bits.
274   BFI, // (src0 & src1) | (~src0 & src2)
275   BFM, // Insert a range of bits into a 32-bit word.
276   FFBH_U32, // ctlz with -1 if input is zero.
277   MUL_U24,
278   MUL_I24,
279   MAD_U24,
280   MAD_I24,
281   TEXTURE_FETCH,
282   EXPORT,
283   CONST_ADDRESS,
284   REGISTER_LOAD,
285   REGISTER_STORE,
286   LOAD_INPUT,
287   SAMPLE,
288   SAMPLEB,
289   SAMPLED,
290   SAMPLEL,
291 
292   // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
293   CVT_F32_UBYTE0,
294   CVT_F32_UBYTE1,
295   CVT_F32_UBYTE2,
296   CVT_F32_UBYTE3,
297   /// This node is for VLIW targets and it is used to represent a vector
298   /// that is stored in consecutive registers with the same channel.
299   /// For example:
300   ///   |X  |Y|Z|W|
301   /// T0|v.x| | | |
302   /// T1|v.y| | | |
303   /// T2|v.z| | | |
304   /// T3|v.w| | | |
305   BUILD_VERTICAL_VECTOR,
306   /// Pointer to the start of the shader's constant data.
307   CONST_DATA_PTR,
308   SENDMSG,
309   INTERP_MOV,
310   INTERP_P1,
311   INTERP_P2,
312   FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
313   STORE_MSKOR,
314   LOAD_CONSTANT,
315   TBUFFER_STORE_FORMAT,
316   LAST_AMDGPU_ISD_NUMBER
317 };
318 
319 
320 } // End namespace AMDGPUISD
321 
322 } // End namespace llvm
323 
324 #endif
325