1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Interface definition of the TargetLowering class that is common
12 /// to all AMD GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
17 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
18 
19 #include "llvm/Target/TargetLowering.h"
20 
21 namespace llvm {
22 
23 class AMDGPUMachineFunction;
24 class AMDGPUSubtarget;
25 class MachineRegisterInfo;
26 
27 class AMDGPUTargetLowering : public TargetLowering {
28 private:
29   /// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been
30   /// legalized from a smaller type VT. Need to match pre-legalized type because
31   /// the generic legalization inserts the add/sub between the select and
32   /// compare.
33   SDValue getFFBH_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL) const;
34 
35 protected:
36   const AMDGPUSubtarget *Subtarget;
37 
38   SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
39   SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
40   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
41   /// \brief Split a vector store into multiple scalar stores.
42   /// \returns The resulting chain.
43 
44   SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
45   SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
46   SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
47   SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
48   SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
49 
50   SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const;
51   SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
52   SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
53   SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
54 
55   SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
56 
57   SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
58   SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
59   SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
60   SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
61 
62   SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
63   SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
64   SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
65   SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
66 
67   SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
68 
69 protected:
70   bool shouldCombineMemoryType(EVT VT) const;
71   SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
72   SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
73 
74   SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL,
75                                        unsigned Opc, SDValue LHS,
76                                        uint32_t ValLo, uint32_t ValHi) const;
77   SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
78   SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
79   SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
80   SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
81   SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
82   SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const;
83   SDValue performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) const;
84   SDValue performCtlzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
85                              SDValue RHS, DAGCombinerInfo &DCI) const;
86   SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
87 
88   static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
89 
90   virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
91                                      SelectionDAG &DAG) const;
92 
93   /// Return 64-bit value Op as two 32-bit integers.
94   std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
95                                               SelectionDAG &DAG) const;
96   SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
97   SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
98 
99   /// \brief Split a vector load into 2 loads of half the vector.
100   SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
101 
102   /// \brief Split a vector store into 2 stores of half the vector.
103   SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
104 
105   SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
106   SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
107   SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
108   SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
109   void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
110                                     SmallVectorImpl<SDValue> &Results) const;
111   void analyzeFormalArgumentsCompute(CCState &State,
112                               const SmallVectorImpl<ISD::InputArg> &Ins) const;
113   void AnalyzeFormalArguments(CCState &State,
114                               const SmallVectorImpl<ISD::InputArg> &Ins) const;
115   void AnalyzeReturn(CCState &State,
116                      const SmallVectorImpl<ISD::OutputArg> &Outs) const;
117 
118 public:
119   AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
120 
121   bool isFAbsFree(EVT VT) const override;
122   bool isFNegFree(EVT VT) const override;
123   bool isTruncateFree(EVT Src, EVT Dest) const override;
124   bool isTruncateFree(Type *Src, Type *Dest) const override;
125 
126   bool isZExtFree(Type *Src, Type *Dest) const override;
127   bool isZExtFree(EVT Src, EVT Dest) const override;
128   bool isZExtFree(SDValue Val, EVT VT2) const override;
129 
130   bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
131 
132   MVT getVectorIdxTy(const DataLayout &) const override;
133   bool isSelectSupported(SelectSupportKind) const override;
134 
135   bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
136   bool ShouldShrinkFPConstant(EVT VT) const override;
137   bool shouldReduceLoadWidth(SDNode *Load,
138                              ISD::LoadExtType ExtType,
139                              EVT ExtVT) const override;
140 
141   bool isLoadBitCastBeneficial(EVT, EVT) const final;
142 
143   bool storeOfVectorConstantIsCheap(EVT MemVT,
144                                     unsigned NumElem,
145                                     unsigned AS) const override;
146   bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
147   bool isCheapToSpeculateCttz() const override;
148   bool isCheapToSpeculateCtlz() const override;
149 
150   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
151                       const SmallVectorImpl<ISD::OutputArg> &Outs,
152                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
153                       SelectionDAG &DAG) const override;
154   SDValue LowerCall(CallLoweringInfo &CLI,
155                     SmallVectorImpl<SDValue> &InVals) const override;
156 
157   SDValue LowerDYNAMIC_STACKALLOC(SDValue Op,
158                                   SelectionDAG &DAG) const;
159 
160   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
161   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
162   void ReplaceNodeResults(SDNode * N,
163                           SmallVectorImpl<SDValue> &Results,
164                           SelectionDAG &DAG) const override;
165 
166   SDValue CombineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
167                                SDValue RHS, SDValue True, SDValue False,
168                                SDValue CC, DAGCombinerInfo &DCI) const;
169 
170   const char* getTargetNodeName(unsigned Opcode) const override;
171 
172   bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
173     return true;
174   }
175   SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
176                            int &RefinementSteps, bool &UseOneConstNR,
177                            bool Reciprocal) const override;
178   SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
179                            int &RefinementSteps) const override;
180 
181   virtual SDNode *PostISelFolding(MachineSDNode *N,
182                                   SelectionDAG &DAG) const = 0;
183 
184   /// \brief Determine which of the bits specified in \p Mask are known to be
185   /// either zero or one and return them in the \p KnownZero and \p KnownOne
186   /// bitsets.
187   void computeKnownBitsForTargetNode(const SDValue Op,
188                                      APInt &KnownZero,
189                                      APInt &KnownOne,
190                                      const SelectionDAG &DAG,
191                                      unsigned Depth = 0) const override;
192 
193   unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG,
194                                            unsigned Depth = 0) const override;
195 
196   /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
197   /// MachineFunction.
198   ///
199   /// \returns a RegisterSDNode representing Reg.
200   virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
201                                        const TargetRegisterClass *RC,
202                                        unsigned Reg, EVT VT) const;
203 
204   enum ImplicitParameter {
205     FIRST_IMPLICIT,
206     GRID_DIM = FIRST_IMPLICIT,
207     GRID_OFFSET,
208   };
209 
210   /// \brief Helper function that returns the byte offset of the given
211   /// type of implicit parameter.
212   uint32_t getImplicitParameterOffset(const AMDGPUMachineFunction *MFI,
213                                       const ImplicitParameter Param) const;
214 };
215 
216 namespace AMDGPUISD {
217 
218 enum NodeType : unsigned {
219   // AMDIL ISD Opcodes
220   FIRST_NUMBER = ISD::BUILTIN_OP_END,
221   CALL,        // Function call based on a single integer
222   UMUL,        // 32bit unsigned multiplication
223   BRANCH_COND,
224   // End AMDIL ISD Opcodes
225   ENDPGM,
226   RETURN,
227   DWORDADDR,
228   FRACT,
229   CLAMP,
230   // This is SETCC with the full mask result which is used for a compare with a
231   // result bit per item in the wavefront.
232   SETCC,
233   SETREG,
234   // FP ops with input and output chain.
235   FMA_W_CHAIN,
236   FMUL_W_CHAIN,
237 
238   // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
239   // Denormals handled on some parts.
240   COS_HW,
241   SIN_HW,
242   FMAX_LEGACY,
243   FMIN_LEGACY,
244   FMAX3,
245   SMAX3,
246   UMAX3,
247   FMIN3,
248   SMIN3,
249   UMIN3,
250   FMED3,
251   SMED3,
252   UMED3,
253   URECIP,
254   DIV_SCALE,
255   DIV_FMAS,
256   DIV_FIXUP,
257   TRIG_PREOP, // 1 ULP max error for f64
258 
259   // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
260   //            For f64, max error 2^29 ULP, handles denormals.
261   RCP,
262   RSQ,
263   RCP_LEGACY,
264   RSQ_LEGACY,
265   FMUL_LEGACY,
266   RSQ_CLAMP,
267   LDEXP,
268   FP_CLASS,
269   DOT4,
270   CARRY,
271   BORROW,
272   BFE_U32, // Extract range of bits with zero extension to 32-bits.
273   BFE_I32, // Extract range of bits with sign extension to 32-bits.
274   BFI, // (src0 & src1) | (~src0 & src2)
275   BFM, // Insert a range of bits into a 32-bit word.
276   FFBH_U32, // ctlz with -1 if input is zero.
277   FFBH_I32,
278   MUL_U24,
279   MUL_I24,
280   MULHI_U24,
281   MULHI_I24,
282   MAD_U24,
283   MAD_I24,
284   MUL_LOHI_I24,
285   MUL_LOHI_U24,
286   TEXTURE_FETCH,
287   EXPORT, // exp on SI+
288   EXPORT_DONE, // exp on SI+ with done bit set
289   R600_EXPORT,
290   CONST_ADDRESS,
291   REGISTER_LOAD,
292   REGISTER_STORE,
293   LOAD_INPUT,
294   SAMPLE,
295   SAMPLEB,
296   SAMPLED,
297   SAMPLEL,
298 
299   // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
300   CVT_F32_UBYTE0,
301   CVT_F32_UBYTE1,
302   CVT_F32_UBYTE2,
303   CVT_F32_UBYTE3,
304   /// This node is for VLIW targets and it is used to represent a vector
305   /// that is stored in consecutive registers with the same channel.
306   /// For example:
307   ///   |X  |Y|Z|W|
308   /// T0|v.x| | | |
309   /// T1|v.y| | | |
310   /// T2|v.z| | | |
311   /// T3|v.w| | | |
312   BUILD_VERTICAL_VECTOR,
313   /// Pointer to the start of the shader's constant data.
314   CONST_DATA_PTR,
315   SENDMSG,
316   INTERP_MOV,
317   INTERP_P1,
318   INTERP_P2,
319   PC_ADD_REL_OFFSET,
320   KILL,
321   FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
322   STORE_MSKOR,
323   LOAD_CONSTANT,
324   TBUFFER_STORE_FORMAT,
325   ATOMIC_CMP_SWAP,
326   ATOMIC_INC,
327   ATOMIC_DEC,
328   LAST_AMDGPU_ISD_NUMBER
329 };
330 
331 
332 } // End namespace AMDGPUISD
333 
334 } // End namespace llvm
335 
336 #endif
337