1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Interface definition of the TargetLowering class that is common
12 /// to all AMD GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
17 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
18 
19 #include "AMDGPU.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/Target/TargetLowering.h"
22 
23 namespace llvm {
24 
25 class AMDGPUMachineFunction;
26 class AMDGPUSubtarget;
27 struct ArgDescriptor;
28 
29 class AMDGPUTargetLowering : public TargetLowering {
30 private:
31   /// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been
32   /// legalized from a smaller type VT. Need to match pre-legalized type because
33   /// the generic legalization inserts the add/sub between the select and
34   /// compare.
35   SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
36 
37 public:
38   static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
39   static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
40 
41 protected:
42   const AMDGPUSubtarget *Subtarget;
43   AMDGPUAS AMDGPUASI;
44 
45   SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
46   SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
47   /// \brief Split a vector store into multiple scalar stores.
48   /// \returns The resulting chain.
49 
50   SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
51   SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
52   SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
53   SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
54   SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
55 
56   SDValue LowerFROUND32_16(SDValue Op, SelectionDAG &DAG) const;
57   SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
58   SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
59   SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
60 
61   SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const;
62 
63   SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
64   SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
65   SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
66   SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
67 
68   SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
69   SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
70   SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
71   SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
72 
73   SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
74 
75 protected:
76   bool shouldCombineMemoryType(EVT VT) const;
77   SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
78   SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
79   SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const;
80   SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const;
81 
82   SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL,
83                                        unsigned Opc, SDValue LHS,
84                                        uint32_t ValLo, uint32_t ValHi) const;
85   SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
86   SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
87   SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
88   SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
89   SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
90   SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const;
91   SDValue performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) const;
92   SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
93                              SDValue RHS, DAGCombinerInfo &DCI) const;
94   SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
95   SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
96   SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
97 
98   static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
99 
100   virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
101                                      SelectionDAG &DAG) const;
102 
103   /// Return 64-bit value Op as two 32-bit integers.
104   std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
105                                               SelectionDAG &DAG) const;
106   SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
107   SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
108 
109   /// \brief Split a vector load into 2 loads of half the vector.
110   SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
111 
112   /// \brief Split a vector store into 2 stores of half the vector.
113   SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
114 
115   SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
116   SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
117   SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
118   SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
119   void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
120                                     SmallVectorImpl<SDValue> &Results) const;
121   void analyzeFormalArgumentsCompute(CCState &State,
122                               const SmallVectorImpl<ISD::InputArg> &Ins) const;
123 public:
124   AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
125 
126   bool mayIgnoreSignedZero(SDValue Op) const {
127     if (getTargetMachine().Options.NoSignedZerosFPMath)
128       return true;
129 
130     const auto Flags = Op.getNode()->getFlags();
131     if (Flags.isDefined())
132       return Flags.hasNoSignedZeros();
133 
134     return false;
135   }
136 
137   static bool allUsesHaveSourceMods(const SDNode *N,
138                                     unsigned CostThreshold = 4);
139   bool isFAbsFree(EVT VT) const override;
140   bool isFNegFree(EVT VT) const override;
141   bool isTruncateFree(EVT Src, EVT Dest) const override;
142   bool isTruncateFree(Type *Src, Type *Dest) const override;
143 
144   bool isZExtFree(Type *Src, Type *Dest) const override;
145   bool isZExtFree(EVT Src, EVT Dest) const override;
146   bool isZExtFree(SDValue Val, EVT VT2) const override;
147   bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const override;
148 
149   bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
150 
151   MVT getVectorIdxTy(const DataLayout &) const override;
152   bool isSelectSupported(SelectSupportKind) const override;
153 
154   bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
155   bool ShouldShrinkFPConstant(EVT VT) const override;
156   bool shouldReduceLoadWidth(SDNode *Load,
157                              ISD::LoadExtType ExtType,
158                              EVT ExtVT) const override;
159 
160   bool isLoadBitCastBeneficial(EVT, EVT) const final;
161 
162   bool storeOfVectorConstantIsCheap(EVT MemVT,
163                                     unsigned NumElem,
164                                     unsigned AS) const override;
165   bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
166   bool isCheapToSpeculateCttz() const override;
167   bool isCheapToSpeculateCtlz() const override;
168 
169   static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
170   static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
171 
172   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
173                       const SmallVectorImpl<ISD::OutputArg> &Outs,
174                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
175                       SelectionDAG &DAG) const override;
176 
177   SDValue addTokenForArgument(SDValue Chain,
178                               SelectionDAG &DAG,
179                               MachineFrameInfo &MFI,
180                               int ClobberedFI) const;
181 
182   SDValue lowerUnhandledCall(CallLoweringInfo &CLI,
183                              SmallVectorImpl<SDValue> &InVals,
184                              StringRef Reason) const;
185   SDValue LowerCall(CallLoweringInfo &CLI,
186                     SmallVectorImpl<SDValue> &InVals) const override;
187 
188   SDValue LowerDYNAMIC_STACKALLOC(SDValue Op,
189                                   SelectionDAG &DAG) const;
190 
191   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
192   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
193   void ReplaceNodeResults(SDNode * N,
194                           SmallVectorImpl<SDValue> &Results,
195                           SelectionDAG &DAG) const override;
196 
197   SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
198                                SDValue RHS, SDValue True, SDValue False,
199                                SDValue CC, DAGCombinerInfo &DCI) const;
200 
201   const char* getTargetNodeName(unsigned Opcode) const override;
202 
203   bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
204     return true;
205   }
206   SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
207                            int &RefinementSteps, bool &UseOneConstNR,
208                            bool Reciprocal) const override;
209   SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
210                            int &RefinementSteps) const override;
211 
212   virtual SDNode *PostISelFolding(MachineSDNode *N,
213                                   SelectionDAG &DAG) const = 0;
214 
215   /// \brief Determine which of the bits specified in \p Mask are known to be
216   /// either zero or one and return them in the \p KnownZero and \p KnownOne
217   /// bitsets.
218   void computeKnownBitsForTargetNode(const SDValue Op,
219                                      KnownBits &Known,
220                                      const APInt &DemandedElts,
221                                      const SelectionDAG &DAG,
222                                      unsigned Depth = 0) const override;
223 
224   unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
225                                            const SelectionDAG &DAG,
226                                            unsigned Depth = 0) const override;
227 
228   /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
229   /// MachineFunction.
230   ///
231   /// \returns a RegisterSDNode representing Reg if \p RawReg is true, otherwise
232   /// a copy from the register.
233   SDValue CreateLiveInRegister(SelectionDAG &DAG,
234                                const TargetRegisterClass *RC,
235                                unsigned Reg, EVT VT,
236                                const SDLoc &SL,
237                                bool RawReg = false) const;
238   SDValue CreateLiveInRegister(SelectionDAG &DAG,
239                                const TargetRegisterClass *RC,
240                                unsigned Reg, EVT VT) const {
241     return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()));
242   }
243 
244   // Returns the raw live in register rather than a copy from it.
245   SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG,
246                                   const TargetRegisterClass *RC,
247                                   unsigned Reg, EVT VT) const {
248     return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()), true);
249   }
250 
251   /// Similar to CreateLiveInRegister, except value maybe loaded from a stack
252   /// slot rather than passed in a register.
253   SDValue loadStackInputValue(SelectionDAG &DAG,
254                               EVT VT,
255                               const SDLoc &SL,
256                               int64_t Offset) const;
257 
258   SDValue storeStackInputValue(SelectionDAG &DAG,
259                                const SDLoc &SL,
260                                SDValue Chain,
261                                SDValue StackPtr,
262                                SDValue ArgVal,
263                                int64_t Offset) const;
264 
265   SDValue loadInputValue(SelectionDAG &DAG,
266                          const TargetRegisterClass *RC,
267                          EVT VT, const SDLoc &SL,
268                          const ArgDescriptor &Arg) const;
269 
270   enum ImplicitParameter {
271     FIRST_IMPLICIT,
272     GRID_DIM = FIRST_IMPLICIT,
273     GRID_OFFSET,
274   };
275 
276   /// \brief Helper function that returns the byte offset of the given
277   /// type of implicit parameter.
278   uint32_t getImplicitParameterOffset(const AMDGPUMachineFunction *MFI,
279                                       const ImplicitParameter Param) const;
280 
281   AMDGPUAS getAMDGPUAS() const {
282     return AMDGPUASI;
283   }
284 
285   MVT getFenceOperandTy(const DataLayout &DL) const override {
286     return MVT::i32;
287   }
288 };
289 
290 namespace AMDGPUISD {
291 
292 enum NodeType : unsigned {
293   // AMDIL ISD Opcodes
294   FIRST_NUMBER = ISD::BUILTIN_OP_END,
295   UMUL,        // 32bit unsigned multiplication
296   BRANCH_COND,
297   // End AMDIL ISD Opcodes
298 
299   // Function call.
300   CALL,
301   TC_RETURN,
302   TRAP,
303 
304   // Masked control flow nodes.
305   IF,
306   ELSE,
307   LOOP,
308 
309   // A uniform kernel return that terminates the wavefront.
310   ENDPGM,
311 
312   // Return to a shader part's epilog code.
313   RETURN_TO_EPILOG,
314 
315   // Return with values from a non-entry function.
316   RET_FLAG,
317 
318   DWORDADDR,
319   FRACT,
320 
321   /// CLAMP value between 0.0 and 1.0. NaN clamped to 0, following clamp output
322   /// modifier behavior with dx10_enable.
323   CLAMP,
324 
325   // This is SETCC with the full mask result which is used for a compare with a
326   // result bit per item in the wavefront.
327   SETCC,
328   SETREG,
329   // FP ops with input and output chain.
330   FMA_W_CHAIN,
331   FMUL_W_CHAIN,
332 
333   // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
334   // Denormals handled on some parts.
335   COS_HW,
336   SIN_HW,
337   FMAX_LEGACY,
338   FMIN_LEGACY,
339   FMAX3,
340   SMAX3,
341   UMAX3,
342   FMIN3,
343   SMIN3,
344   UMIN3,
345   FMED3,
346   SMED3,
347   UMED3,
348   URECIP,
349   DIV_SCALE,
350   DIV_FMAS,
351   DIV_FIXUP,
352   // For emitting ISD::FMAD when f32 denormals are enabled because mac/mad is
353   // treated as an illegal operation.
354   FMAD_FTZ,
355   TRIG_PREOP, // 1 ULP max error for f64
356 
357   // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
358   //            For f64, max error 2^29 ULP, handles denormals.
359   RCP,
360   RSQ,
361   RCP_LEGACY,
362   RSQ_LEGACY,
363   FMUL_LEGACY,
364   RSQ_CLAMP,
365   LDEXP,
366   FP_CLASS,
367   DOT4,
368   CARRY,
369   BORROW,
370   BFE_U32, // Extract range of bits with zero extension to 32-bits.
371   BFE_I32, // Extract range of bits with sign extension to 32-bits.
372   BFI, // (src0 & src1) | (~src0 & src2)
373   BFM, // Insert a range of bits into a 32-bit word.
374   FFBH_U32, // ctlz with -1 if input is zero.
375   FFBH_I32,
376   FFBL_B32, // cttz with -1 if input is zero.
377   MUL_U24,
378   MUL_I24,
379   MULHI_U24,
380   MULHI_I24,
381   MAD_U24,
382   MAD_I24,
383   MAD_U64_U32,
384   MAD_I64_I32,
385   MUL_LOHI_I24,
386   MUL_LOHI_U24,
387   TEXTURE_FETCH,
388   EXPORT, // exp on SI+
389   EXPORT_DONE, // exp on SI+ with done bit set
390   R600_EXPORT,
391   CONST_ADDRESS,
392   REGISTER_LOAD,
393   REGISTER_STORE,
394   SAMPLE,
395   SAMPLEB,
396   SAMPLED,
397   SAMPLEL,
398 
399   // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
400   CVT_F32_UBYTE0,
401   CVT_F32_UBYTE1,
402   CVT_F32_UBYTE2,
403   CVT_F32_UBYTE3,
404 
405   // Convert two float 32 numbers into a single register holding two packed f16
406   // with round to zero.
407   CVT_PKRTZ_F16_F32,
408 
409   // Same as the standard node, except the high bits of the resulting integer
410   // are known 0.
411   FP_TO_FP16,
412 
413   // Wrapper around fp16 results that are known to zero the high bits.
414   FP16_ZEXT,
415 
416   /// This node is for VLIW targets and it is used to represent a vector
417   /// that is stored in consecutive registers with the same channel.
418   /// For example:
419   ///   |X  |Y|Z|W|
420   /// T0|v.x| | | |
421   /// T1|v.y| | | |
422   /// T2|v.z| | | |
423   /// T3|v.w| | | |
424   BUILD_VERTICAL_VECTOR,
425   /// Pointer to the start of the shader's constant data.
426   CONST_DATA_PTR,
427   INIT_EXEC,
428   INIT_EXEC_FROM_INPUT,
429   SENDMSG,
430   SENDMSGHALT,
431   INTERP_MOV,
432   INTERP_P1,
433   INTERP_P2,
434   PC_ADD_REL_OFFSET,
435   KILL,
436   DUMMY_CHAIN,
437   FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
438   STORE_MSKOR,
439   LOAD_CONSTANT,
440   TBUFFER_STORE_FORMAT,
441   TBUFFER_STORE_FORMAT_X3,
442   TBUFFER_LOAD_FORMAT,
443   ATOMIC_CMP_SWAP,
444   ATOMIC_INC,
445   ATOMIC_DEC,
446   BUFFER_LOAD,
447   BUFFER_LOAD_FORMAT,
448   LAST_AMDGPU_ISD_NUMBER
449 };
450 
451 
452 } // End namespace AMDGPUISD
453 
454 } // End namespace llvm
455 
456 #endif
457