1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// Interface definition of the TargetLowering class that is common
12 /// to all AMD GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
17 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
18 
19 #include "AMDGPU.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/TargetLowering.h"
22 
23 namespace llvm {
24 
25 class AMDGPUMachineFunction;
26 class AMDGPUSubtarget;
27 struct ArgDescriptor;
28 
29 class AMDGPUTargetLowering : public TargetLowering {
30 private:
31   /// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been
32   /// legalized from a smaller type VT. Need to match pre-legalized type because
33   /// the generic legalization inserts the add/sub between the select and
34   /// compare.
35   SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
36 
37 public:
38   static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
39   static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
40 
41 protected:
42   const AMDGPUSubtarget *Subtarget;
43   AMDGPUAS AMDGPUASI;
44 
45   SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
46   SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
47   /// Split a vector store into multiple scalar stores.
48   /// \returns The resulting chain.
49 
50   SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
51   SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
52   SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
53   SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
54   SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
55 
56   SDValue LowerFROUND32_16(SDValue Op, SelectionDAG &DAG) const;
57   SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
58   SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
59   SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
60   SDValue LowerFLOG(SDValue Op, SelectionDAG &Dag,
61                     double Log2BaseInverted) const;
62 
63   SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const;
64 
65   SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
66   SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
67   SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
68   SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
69 
70   SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
71   SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
72   SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
73   SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
74 
75   SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
76 
77 protected:
78   bool shouldCombineMemoryType(EVT VT) const;
79   SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
80   SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
81   SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const;
82 
83   SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL,
84                                        unsigned Opc, SDValue LHS,
85                                        uint32_t ValLo, uint32_t ValHi) const;
86   SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
87   SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
88   SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
89   SDValue performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) const;
90   SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
91   SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
92   SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const;
93   SDValue performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) const;
94   SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
95                              SDValue RHS, DAGCombinerInfo &DCI) const;
96   SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
97   SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
98   SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
99 
100   static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
101 
102   virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
103                                      SelectionDAG &DAG) const;
104 
105   /// Return 64-bit value Op as two 32-bit integers.
106   std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
107                                               SelectionDAG &DAG) const;
108   SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
109   SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
110 
111   /// Split a vector load into 2 loads of half the vector.
112   SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
113 
114   /// Split a vector store into 2 stores of half the vector.
115   SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
116 
117   SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
118   SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
119   SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
120   SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
121   void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
122                                     SmallVectorImpl<SDValue> &Results) const;
123   void analyzeFormalArgumentsCompute(CCState &State,
124                               const SmallVectorImpl<ISD::InputArg> &Ins) const;
125 public:
126   AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
127 
128   bool mayIgnoreSignedZero(SDValue Op) const {
129     if (getTargetMachine().Options.NoSignedZerosFPMath)
130       return true;
131 
132     const auto Flags = Op.getNode()->getFlags();
133     if (Flags.isDefined())
134       return Flags.hasNoSignedZeros();
135 
136     return false;
137   }
138 
139   static inline SDValue stripBitcast(SDValue Val) {
140     return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(0) : Val;
141   }
142 
143   static bool allUsesHaveSourceMods(const SDNode *N,
144                                     unsigned CostThreshold = 4);
145   bool isFAbsFree(EVT VT) const override;
146   bool isFNegFree(EVT VT) const override;
147   bool isTruncateFree(EVT Src, EVT Dest) const override;
148   bool isTruncateFree(Type *Src, Type *Dest) const override;
149 
150   bool isZExtFree(Type *Src, Type *Dest) const override;
151   bool isZExtFree(EVT Src, EVT Dest) const override;
152   bool isZExtFree(SDValue Val, EVT VT2) const override;
153 
154   bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
155 
156   MVT getVectorIdxTy(const DataLayout &) const override;
157   bool isSelectSupported(SelectSupportKind) const override;
158 
159   bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
160   bool ShouldShrinkFPConstant(EVT VT) const override;
161   bool shouldReduceLoadWidth(SDNode *Load,
162                              ISD::LoadExtType ExtType,
163                              EVT ExtVT) const override;
164 
165   bool isLoadBitCastBeneficial(EVT, EVT) const final;
166 
167   bool storeOfVectorConstantIsCheap(EVT MemVT,
168                                     unsigned NumElem,
169                                     unsigned AS) const override;
170   bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
171   bool isCheapToSpeculateCttz() const override;
172   bool isCheapToSpeculateCtlz() const override;
173 
174   bool isSDNodeAlwaysUniform(const SDNode *N) const override;
175   static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
176   static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
177 
178   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
179                       const SmallVectorImpl<ISD::OutputArg> &Outs,
180                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
181                       SelectionDAG &DAG) const override;
182 
183   SDValue addTokenForArgument(SDValue Chain,
184                               SelectionDAG &DAG,
185                               MachineFrameInfo &MFI,
186                               int ClobberedFI) const;
187 
188   SDValue lowerUnhandledCall(CallLoweringInfo &CLI,
189                              SmallVectorImpl<SDValue> &InVals,
190                              StringRef Reason) const;
191   SDValue LowerCall(CallLoweringInfo &CLI,
192                     SmallVectorImpl<SDValue> &InVals) const override;
193 
194   SDValue LowerDYNAMIC_STACKALLOC(SDValue Op,
195                                   SelectionDAG &DAG) const;
196 
197   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
198   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
199   void ReplaceNodeResults(SDNode * N,
200                           SmallVectorImpl<SDValue> &Results,
201                           SelectionDAG &DAG) const override;
202 
203   SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
204                                SDValue RHS, SDValue True, SDValue False,
205                                SDValue CC, DAGCombinerInfo &DCI) const;
206 
207   const char* getTargetNodeName(unsigned Opcode) const override;
208 
209   // FIXME: Turn off MergeConsecutiveStores() before Instruction Selection
210   // for AMDGPU.
211   // A commit ( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319036
212   // 91177308-0d34-0410-b5e6-96231b3b80d8 ) turned on
213   // MergeConsecutiveStores() before Instruction Selection for all targets.
214   // Enough AMDGPU compiles go into an infinite loop ( MergeConsecutiveStores()
215   // merges two stores; LegalizeStoreOps() un-merges; MergeConsecutiveStores()
216   // re-merges, etc. ) to warrant turning it off for now.
217   bool mergeStoresAfterLegalization() const override { return false; }
218 
219   bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
220     return true;
221   }
222   SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
223                            int &RefinementSteps, bool &UseOneConstNR,
224                            bool Reciprocal) const override;
225   SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
226                            int &RefinementSteps) const override;
227 
228   virtual SDNode *PostISelFolding(MachineSDNode *N,
229                                   SelectionDAG &DAG) const = 0;
230 
231   /// Determine which of the bits specified in \p Mask are known to be
232   /// either zero or one and return them in the \p KnownZero and \p KnownOne
233   /// bitsets.
234   void computeKnownBitsForTargetNode(const SDValue Op,
235                                      KnownBits &Known,
236                                      const APInt &DemandedElts,
237                                      const SelectionDAG &DAG,
238                                      unsigned Depth = 0) const override;
239 
240   unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
241                                            const SelectionDAG &DAG,
242                                            unsigned Depth = 0) const override;
243 
244   /// Helper function that adds Reg to the LiveIn list of the DAG's
245   /// MachineFunction.
246   ///
247   /// \returns a RegisterSDNode representing Reg if \p RawReg is true, otherwise
248   /// a copy from the register.
249   SDValue CreateLiveInRegister(SelectionDAG &DAG,
250                                const TargetRegisterClass *RC,
251                                unsigned Reg, EVT VT,
252                                const SDLoc &SL,
253                                bool RawReg = false) const;
254   SDValue CreateLiveInRegister(SelectionDAG &DAG,
255                                const TargetRegisterClass *RC,
256                                unsigned Reg, EVT VT) const {
257     return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()));
258   }
259 
260   // Returns the raw live in register rather than a copy from it.
261   SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG,
262                                   const TargetRegisterClass *RC,
263                                   unsigned Reg, EVT VT) const {
264     return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()), true);
265   }
266 
267   /// Similar to CreateLiveInRegister, except value maybe loaded from a stack
268   /// slot rather than passed in a register.
269   SDValue loadStackInputValue(SelectionDAG &DAG,
270                               EVT VT,
271                               const SDLoc &SL,
272                               int64_t Offset) const;
273 
274   SDValue storeStackInputValue(SelectionDAG &DAG,
275                                const SDLoc &SL,
276                                SDValue Chain,
277                                SDValue StackPtr,
278                                SDValue ArgVal,
279                                int64_t Offset) const;
280 
281   SDValue loadInputValue(SelectionDAG &DAG,
282                          const TargetRegisterClass *RC,
283                          EVT VT, const SDLoc &SL,
284                          const ArgDescriptor &Arg) const;
285 
286   enum ImplicitParameter {
287     FIRST_IMPLICIT,
288     GRID_DIM = FIRST_IMPLICIT,
289     GRID_OFFSET,
290   };
291 
292   /// Helper function that returns the byte offset of the given
293   /// type of implicit parameter.
294   uint32_t getImplicitParameterOffset(const AMDGPUMachineFunction *MFI,
295                                       const ImplicitParameter Param) const;
296 
297   AMDGPUAS getAMDGPUAS() const {
298     return AMDGPUASI;
299   }
300 
301   MVT getFenceOperandTy(const DataLayout &DL) const override {
302     return MVT::i32;
303   }
304 };
305 
306 namespace AMDGPUISD {
307 
308 enum NodeType : unsigned {
309   // AMDIL ISD Opcodes
310   FIRST_NUMBER = ISD::BUILTIN_OP_END,
311   UMUL,        // 32bit unsigned multiplication
312   BRANCH_COND,
313   // End AMDIL ISD Opcodes
314 
315   // Function call.
316   CALL,
317   TC_RETURN,
318   TRAP,
319 
320   // Masked control flow nodes.
321   IF,
322   ELSE,
323   LOOP,
324 
325   // A uniform kernel return that terminates the wavefront.
326   ENDPGM,
327 
328   // Return to a shader part's epilog code.
329   RETURN_TO_EPILOG,
330 
331   // Return with values from a non-entry function.
332   RET_FLAG,
333 
334   DWORDADDR,
335   FRACT,
336 
337   /// CLAMP value between 0.0 and 1.0. NaN clamped to 0, following clamp output
338   /// modifier behavior with dx10_enable.
339   CLAMP,
340 
341   // This is SETCC with the full mask result which is used for a compare with a
342   // result bit per item in the wavefront.
343   SETCC,
344   SETREG,
345   // FP ops with input and output chain.
346   FMA_W_CHAIN,
347   FMUL_W_CHAIN,
348 
349   // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
350   // Denormals handled on some parts.
351   COS_HW,
352   SIN_HW,
353   FMAX_LEGACY,
354   FMIN_LEGACY,
355   FMAX3,
356   SMAX3,
357   UMAX3,
358   FMIN3,
359   SMIN3,
360   UMIN3,
361   FMED3,
362   SMED3,
363   UMED3,
364   URECIP,
365   DIV_SCALE,
366   DIV_FMAS,
367   DIV_FIXUP,
368   // For emitting ISD::FMAD when f32 denormals are enabled because mac/mad is
369   // treated as an illegal operation.
370   FMAD_FTZ,
371   TRIG_PREOP, // 1 ULP max error for f64
372 
373   // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
374   //            For f64, max error 2^29 ULP, handles denormals.
375   RCP,
376   RSQ,
377   RCP_LEGACY,
378   RSQ_LEGACY,
379   FMUL_LEGACY,
380   RSQ_CLAMP,
381   LDEXP,
382   FP_CLASS,
383   DOT4,
384   CARRY,
385   BORROW,
386   BFE_U32, // Extract range of bits with zero extension to 32-bits.
387   BFE_I32, // Extract range of bits with sign extension to 32-bits.
388   BFI, // (src0 & src1) | (~src0 & src2)
389   BFM, // Insert a range of bits into a 32-bit word.
390   FFBH_U32, // ctlz with -1 if input is zero.
391   FFBH_I32,
392   FFBL_B32, // cttz with -1 if input is zero.
393   MUL_U24,
394   MUL_I24,
395   MULHI_U24,
396   MULHI_I24,
397   MAD_U24,
398   MAD_I24,
399   MAD_U64_U32,
400   MAD_I64_I32,
401   MUL_LOHI_I24,
402   MUL_LOHI_U24,
403   PERM,
404   TEXTURE_FETCH,
405   EXPORT, // exp on SI+
406   EXPORT_DONE, // exp on SI+ with done bit set
407   R600_EXPORT,
408   CONST_ADDRESS,
409   REGISTER_LOAD,
410   REGISTER_STORE,
411   SAMPLE,
412   SAMPLEB,
413   SAMPLED,
414   SAMPLEL,
415 
416   // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
417   CVT_F32_UBYTE0,
418   CVT_F32_UBYTE1,
419   CVT_F32_UBYTE2,
420   CVT_F32_UBYTE3,
421 
422   // Convert two float 32 numbers into a single register holding two packed f16
423   // with round to zero.
424   CVT_PKRTZ_F16_F32,
425   CVT_PKNORM_I16_F32,
426   CVT_PKNORM_U16_F32,
427   CVT_PK_I16_I32,
428   CVT_PK_U16_U32,
429 
430   // Same as the standard node, except the high bits of the resulting integer
431   // are known 0.
432   FP_TO_FP16,
433 
434   // Wrapper around fp16 results that are known to zero the high bits.
435   FP16_ZEXT,
436 
437   /// This node is for VLIW targets and it is used to represent a vector
438   /// that is stored in consecutive registers with the same channel.
439   /// For example:
440   ///   |X  |Y|Z|W|
441   /// T0|v.x| | | |
442   /// T1|v.y| | | |
443   /// T2|v.z| | | |
444   /// T3|v.w| | | |
445   BUILD_VERTICAL_VECTOR,
446   /// Pointer to the start of the shader's constant data.
447   CONST_DATA_PTR,
448   INIT_EXEC,
449   INIT_EXEC_FROM_INPUT,
450   SENDMSG,
451   SENDMSGHALT,
452   INTERP_MOV,
453   INTERP_P1,
454   INTERP_P2,
455   PC_ADD_REL_OFFSET,
456   KILL,
457   DUMMY_CHAIN,
458   FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
459   STORE_MSKOR,
460   LOAD_CONSTANT,
461   TBUFFER_STORE_FORMAT,
462   TBUFFER_STORE_FORMAT_X3,
463   TBUFFER_STORE_FORMAT_D16,
464   TBUFFER_LOAD_FORMAT,
465   TBUFFER_LOAD_FORMAT_D16,
466   ATOMIC_CMP_SWAP,
467   ATOMIC_INC,
468   ATOMIC_DEC,
469   ATOMIC_LOAD_FADD,
470   ATOMIC_LOAD_FMIN,
471   ATOMIC_LOAD_FMAX,
472   BUFFER_LOAD,
473   BUFFER_LOAD_FORMAT,
474   BUFFER_LOAD_FORMAT_D16,
475   BUFFER_STORE,
476   BUFFER_STORE_FORMAT,
477   BUFFER_STORE_FORMAT_D16,
478   BUFFER_ATOMIC_SWAP,
479   BUFFER_ATOMIC_ADD,
480   BUFFER_ATOMIC_SUB,
481   BUFFER_ATOMIC_SMIN,
482   BUFFER_ATOMIC_UMIN,
483   BUFFER_ATOMIC_SMAX,
484   BUFFER_ATOMIC_UMAX,
485   BUFFER_ATOMIC_AND,
486   BUFFER_ATOMIC_OR,
487   BUFFER_ATOMIC_XOR,
488   BUFFER_ATOMIC_CMPSWAP,
489 
490   LAST_AMDGPU_ISD_NUMBER
491 };
492 
493 
494 } // End namespace AMDGPUISD
495 
496 } // End namespace llvm
497 
498 #endif
499