1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief Interface definition of the TargetLowering class that is common 12 /// to all AMD GPUs. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H 17 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H 18 19 #include "llvm/Target/TargetLowering.h" 20 21 namespace llvm { 22 23 class AMDGPUMachineFunction; 24 class AMDGPUSubtarget; 25 class MachineRegisterInfo; 26 27 class AMDGPUTargetLowering : public TargetLowering { 28 private: 29 /// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been 30 /// legalized from a smaller type VT. Need to match pre-legalized type because 31 /// the generic legalization inserts the add/sub between the select and 32 /// compare. 33 SDValue getFFBH_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL) const; 34 35 protected: 36 const AMDGPUSubtarget *Subtarget; 37 38 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 39 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const; 40 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 41 /// \brief Split a vector store into multiple scalar stores. 42 /// \returns The resulting chain. 43 44 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const; 45 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const; 46 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const; 47 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const; 48 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const; 49 50 SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const; 51 SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const; 52 SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const; 53 SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const; 54 55 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const; 56 57 SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const; 58 SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const; 59 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 60 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 61 62 SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const; 63 SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const; 64 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const; 65 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const; 66 67 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; 68 69 protected: 70 bool shouldCombineMemoryType(EVT VT) const; 71 SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const; 72 SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const; 73 SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const; 74 75 SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL, 76 unsigned Opc, SDValue LHS, 77 uint32_t ValLo, uint32_t ValHi) const; 78 SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const; 79 SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const; 80 SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const; 81 SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const; 82 SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const; 83 SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const; 84 SDValue performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) const; 85 SDValue performCtlzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS, 86 SDValue RHS, DAGCombinerInfo &DCI) const; 87 SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const; 88 SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const; 89 SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const; 90 91 static EVT getEquivalentMemType(LLVMContext &Context, EVT VT); 92 93 virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, 94 SelectionDAG &DAG) const; 95 96 /// Return 64-bit value Op as two 32-bit integers. 97 std::pair<SDValue, SDValue> split64BitValue(SDValue Op, 98 SelectionDAG &DAG) const; 99 SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const; 100 SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const; 101 102 /// \brief Split a vector load into 2 loads of half the vector. 103 SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const; 104 105 /// \brief Split a vector store into 2 stores of half the vector. 106 SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const; 107 108 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 109 SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const; 110 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const; 111 SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const; 112 void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG, 113 SmallVectorImpl<SDValue> &Results) const; 114 void analyzeFormalArgumentsCompute(CCState &State, 115 const SmallVectorImpl<ISD::InputArg> &Ins) const; 116 void AnalyzeFormalArguments(CCState &State, 117 const SmallVectorImpl<ISD::InputArg> &Ins) const; 118 void AnalyzeReturn(CCState &State, 119 const SmallVectorImpl<ISD::OutputArg> &Outs) const; 120 121 public: 122 AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI); 123 124 bool mayIgnoreSignedZero(SDValue Op) const { 125 if (getTargetMachine().Options.NoSignedZerosFPMath) 126 return true; 127 128 if (const auto *BO = dyn_cast<BinaryWithFlagsSDNode>(Op)) 129 return BO->Flags.hasNoSignedZeros(); 130 131 return false; 132 } 133 134 bool isFAbsFree(EVT VT) const override; 135 bool isFNegFree(EVT VT) const override; 136 bool isTruncateFree(EVT Src, EVT Dest) const override; 137 bool isTruncateFree(Type *Src, Type *Dest) const override; 138 139 bool isZExtFree(Type *Src, Type *Dest) const override; 140 bool isZExtFree(EVT Src, EVT Dest) const override; 141 bool isZExtFree(SDValue Val, EVT VT2) const override; 142 143 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override; 144 145 MVT getVectorIdxTy(const DataLayout &) const override; 146 bool isSelectSupported(SelectSupportKind) const override; 147 148 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override; 149 bool ShouldShrinkFPConstant(EVT VT) const override; 150 bool shouldReduceLoadWidth(SDNode *Load, 151 ISD::LoadExtType ExtType, 152 EVT ExtVT) const override; 153 154 bool isLoadBitCastBeneficial(EVT, EVT) const final; 155 156 bool storeOfVectorConstantIsCheap(EVT MemVT, 157 unsigned NumElem, 158 unsigned AS) const override; 159 bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override; 160 bool isCheapToSpeculateCttz() const override; 161 bool isCheapToSpeculateCtlz() const override; 162 163 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 164 const SmallVectorImpl<ISD::OutputArg> &Outs, 165 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 166 SelectionDAG &DAG) const override; 167 SDValue LowerCall(CallLoweringInfo &CLI, 168 SmallVectorImpl<SDValue> &InVals) const override; 169 170 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, 171 SelectionDAG &DAG) const; 172 173 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 174 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 175 void ReplaceNodeResults(SDNode * N, 176 SmallVectorImpl<SDValue> &Results, 177 SelectionDAG &DAG) const override; 178 179 SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS, 180 SDValue RHS, SDValue True, SDValue False, 181 SDValue CC, DAGCombinerInfo &DCI) const; 182 183 const char* getTargetNodeName(unsigned Opcode) const override; 184 185 bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override { 186 return true; 187 } 188 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 189 int &RefinementSteps, bool &UseOneConstNR, 190 bool Reciprocal) const override; 191 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 192 int &RefinementSteps) const override; 193 194 virtual SDNode *PostISelFolding(MachineSDNode *N, 195 SelectionDAG &DAG) const = 0; 196 197 /// \brief Determine which of the bits specified in \p Mask are known to be 198 /// either zero or one and return them in the \p KnownZero and \p KnownOne 199 /// bitsets. 200 void computeKnownBitsForTargetNode(const SDValue Op, 201 APInt &KnownZero, 202 APInt &KnownOne, 203 const SelectionDAG &DAG, 204 unsigned Depth = 0) const override; 205 206 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG, 207 unsigned Depth = 0) const override; 208 209 /// \brief Helper function that adds Reg to the LiveIn list of the DAG's 210 /// MachineFunction. 211 /// 212 /// \returns a RegisterSDNode representing Reg. 213 virtual SDValue CreateLiveInRegister(SelectionDAG &DAG, 214 const TargetRegisterClass *RC, 215 unsigned Reg, EVT VT) const; 216 217 enum ImplicitParameter { 218 FIRST_IMPLICIT, 219 GRID_DIM = FIRST_IMPLICIT, 220 GRID_OFFSET, 221 }; 222 223 /// \brief Helper function that returns the byte offset of the given 224 /// type of implicit parameter. 225 uint32_t getImplicitParameterOffset(const AMDGPUMachineFunction *MFI, 226 const ImplicitParameter Param) const; 227 }; 228 229 namespace AMDGPUISD { 230 231 enum NodeType : unsigned { 232 // AMDIL ISD Opcodes 233 FIRST_NUMBER = ISD::BUILTIN_OP_END, 234 CALL, // Function call based on a single integer 235 UMUL, // 32bit unsigned multiplication 236 BRANCH_COND, 237 // End AMDIL ISD Opcodes 238 ENDPGM, 239 RETURN, 240 DWORDADDR, 241 FRACT, 242 243 /// CLAMP value between 0.0 and 1.0. NaN clamped to 0, following clamp output 244 /// modifier behavior with dx10_enable. 245 CLAMP, 246 247 // This is SETCC with the full mask result which is used for a compare with a 248 // result bit per item in the wavefront. 249 SETCC, 250 SETREG, 251 // FP ops with input and output chain. 252 FMA_W_CHAIN, 253 FMUL_W_CHAIN, 254 255 // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi. 256 // Denormals handled on some parts. 257 COS_HW, 258 SIN_HW, 259 FMAX_LEGACY, 260 FMIN_LEGACY, 261 FMAX3, 262 SMAX3, 263 UMAX3, 264 FMIN3, 265 SMIN3, 266 UMIN3, 267 FMED3, 268 SMED3, 269 UMED3, 270 URECIP, 271 DIV_SCALE, 272 DIV_FMAS, 273 DIV_FIXUP, 274 TRIG_PREOP, // 1 ULP max error for f64 275 276 // RCP, RSQ - For f32, 1 ULP max error, no denormal handling. 277 // For f64, max error 2^29 ULP, handles denormals. 278 RCP, 279 RSQ, 280 RCP_LEGACY, 281 RSQ_LEGACY, 282 FMUL_LEGACY, 283 RSQ_CLAMP, 284 LDEXP, 285 FP_CLASS, 286 DOT4, 287 CARRY, 288 BORROW, 289 BFE_U32, // Extract range of bits with zero extension to 32-bits. 290 BFE_I32, // Extract range of bits with sign extension to 32-bits. 291 BFI, // (src0 & src1) | (~src0 & src2) 292 BFM, // Insert a range of bits into a 32-bit word. 293 FFBH_U32, // ctlz with -1 if input is zero. 294 FFBH_I32, 295 MUL_U24, 296 MUL_I24, 297 MULHI_U24, 298 MULHI_I24, 299 MAD_U24, 300 MAD_I24, 301 MUL_LOHI_I24, 302 MUL_LOHI_U24, 303 TEXTURE_FETCH, 304 EXPORT, // exp on SI+ 305 EXPORT_DONE, // exp on SI+ with done bit set 306 R600_EXPORT, 307 CONST_ADDRESS, 308 REGISTER_LOAD, 309 REGISTER_STORE, 310 LOAD_INPUT, 311 SAMPLE, 312 SAMPLEB, 313 SAMPLED, 314 SAMPLEL, 315 316 // These cvt_f32_ubyte* nodes need to remain consecutive and in order. 317 CVT_F32_UBYTE0, 318 CVT_F32_UBYTE1, 319 CVT_F32_UBYTE2, 320 CVT_F32_UBYTE3, 321 322 // Convert two float 32 numbers into a single register holding two packed f16 323 // with round to zero. 324 CVT_PKRTZ_F16_F32, 325 326 /// This node is for VLIW targets and it is used to represent a vector 327 /// that is stored in consecutive registers with the same channel. 328 /// For example: 329 /// |X |Y|Z|W| 330 /// T0|v.x| | | | 331 /// T1|v.y| | | | 332 /// T2|v.z| | | | 333 /// T3|v.w| | | | 334 BUILD_VERTICAL_VECTOR, 335 /// Pointer to the start of the shader's constant data. 336 CONST_DATA_PTR, 337 SENDMSG, 338 SENDMSGHALT, 339 INTERP_MOV, 340 INTERP_P1, 341 INTERP_P2, 342 PC_ADD_REL_OFFSET, 343 KILL, 344 DUMMY_CHAIN, 345 FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE, 346 STORE_MSKOR, 347 LOAD_CONSTANT, 348 TBUFFER_STORE_FORMAT, 349 ATOMIC_CMP_SWAP, 350 ATOMIC_INC, 351 ATOMIC_DEC, 352 BUFFER_LOAD, 353 BUFFER_LOAD_FORMAT, 354 LAST_AMDGPU_ISD_NUMBER 355 }; 356 357 358 } // End namespace AMDGPUISD 359 360 } // End namespace llvm 361 362 #endif 363