1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Interface definition of the TargetLowering class that is common
12 /// to all AMD GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
17 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
18 
19 #include "AMDGPU.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/Target/TargetLowering.h"
22 
23 namespace llvm {
24 
25 class AMDGPUMachineFunction;
26 class AMDGPUSubtarget;
27 struct ArgDescriptor;
28 
29 class AMDGPUTargetLowering : public TargetLowering {
30 private:
31   /// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been
32   /// legalized from a smaller type VT. Need to match pre-legalized type because
33   /// the generic legalization inserts the add/sub between the select and
34   /// compare.
35   SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
36 
37 public:
38   static bool isOrEquivalentToAdd(SelectionDAG &DAG, SDValue Op);
39 
40 protected:
41   const AMDGPUSubtarget *Subtarget;
42   AMDGPUAS AMDGPUASI;
43 
44   SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
45   SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
46   /// \brief Split a vector store into multiple scalar stores.
47   /// \returns The resulting chain.
48 
49   SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
50   SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
51   SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
52   SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
53   SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
54 
55   SDValue LowerFROUND32_16(SDValue Op, SelectionDAG &DAG) const;
56   SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
57   SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
58   SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
59 
60   SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const;
61 
62   SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
63   SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
64   SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
65   SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
66 
67   SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
68   SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
69   SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
70   SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
71 
72   SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
73 
74 protected:
75   bool shouldCombineMemoryType(EVT VT) const;
76   SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
77   SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
78   SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const;
79   SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const;
80 
81   SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL,
82                                        unsigned Opc, SDValue LHS,
83                                        uint32_t ValLo, uint32_t ValHi) const;
84   SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
85   SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
86   SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
87   SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
88   SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
89   SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const;
90   SDValue performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) const;
91   SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
92                              SDValue RHS, DAGCombinerInfo &DCI) const;
93   SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
94   SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
95   SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
96 
97   static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
98 
99   virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
100                                      SelectionDAG &DAG) const;
101 
102   /// Return 64-bit value Op as two 32-bit integers.
103   std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
104                                               SelectionDAG &DAG) const;
105   SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
106   SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
107 
108   /// \brief Split a vector load into 2 loads of half the vector.
109   SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
110 
111   /// \brief Split a vector store into 2 stores of half the vector.
112   SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
113 
114   SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
115   SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
116   SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
117   SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
118   void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
119                                     SmallVectorImpl<SDValue> &Results) const;
120   void analyzeFormalArgumentsCompute(CCState &State,
121                               const SmallVectorImpl<ISD::InputArg> &Ins) const;
122 public:
123   AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
124 
125   bool mayIgnoreSignedZero(SDValue Op) const {
126     if (getTargetMachine().Options.NoSignedZerosFPMath)
127       return true;
128 
129     const auto Flags = Op.getNode()->getFlags();
130     if (Flags.isDefined())
131       return Flags.hasNoSignedZeros();
132 
133     return false;
134   }
135 
136   static bool allUsesHaveSourceMods(const SDNode *N,
137                                     unsigned CostThreshold = 4);
138   bool isFAbsFree(EVT VT) const override;
139   bool isFNegFree(EVT VT) const override;
140   bool isTruncateFree(EVT Src, EVT Dest) const override;
141   bool isTruncateFree(Type *Src, Type *Dest) const override;
142 
143   bool isZExtFree(Type *Src, Type *Dest) const override;
144   bool isZExtFree(EVT Src, EVT Dest) const override;
145   bool isZExtFree(SDValue Val, EVT VT2) const override;
146 
147   bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
148 
149   MVT getVectorIdxTy(const DataLayout &) const override;
150   bool isSelectSupported(SelectSupportKind) const override;
151 
152   bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
153   bool ShouldShrinkFPConstant(EVT VT) const override;
154   bool shouldReduceLoadWidth(SDNode *Load,
155                              ISD::LoadExtType ExtType,
156                              EVT ExtVT) const override;
157 
158   bool isLoadBitCastBeneficial(EVT, EVT) const final;
159 
160   bool storeOfVectorConstantIsCheap(EVT MemVT,
161                                     unsigned NumElem,
162                                     unsigned AS) const override;
163   bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
164   bool isCheapToSpeculateCttz() const override;
165   bool isCheapToSpeculateCtlz() const override;
166 
167   static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
168   static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
169 
170   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
171                       const SmallVectorImpl<ISD::OutputArg> &Outs,
172                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
173                       SelectionDAG &DAG) const override;
174 
175   SDValue addTokenForArgument(SDValue Chain,
176                               SelectionDAG &DAG,
177                               MachineFrameInfo &MFI,
178                               int ClobberedFI) const;
179 
180   SDValue lowerUnhandledCall(CallLoweringInfo &CLI,
181                              SmallVectorImpl<SDValue> &InVals,
182                              StringRef Reason) const;
183   SDValue LowerCall(CallLoweringInfo &CLI,
184                     SmallVectorImpl<SDValue> &InVals) const override;
185 
186   SDValue LowerDYNAMIC_STACKALLOC(SDValue Op,
187                                   SelectionDAG &DAG) const;
188 
189   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
190   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
191   void ReplaceNodeResults(SDNode * N,
192                           SmallVectorImpl<SDValue> &Results,
193                           SelectionDAG &DAG) const override;
194 
195   SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
196                                SDValue RHS, SDValue True, SDValue False,
197                                SDValue CC, DAGCombinerInfo &DCI) const;
198 
199   const char* getTargetNodeName(unsigned Opcode) const override;
200 
201   bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
202     return true;
203   }
204   SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
205                            int &RefinementSteps, bool &UseOneConstNR,
206                            bool Reciprocal) const override;
207   SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
208                            int &RefinementSteps) const override;
209 
210   virtual SDNode *PostISelFolding(MachineSDNode *N,
211                                   SelectionDAG &DAG) const = 0;
212 
213   /// \brief Determine which of the bits specified in \p Mask are known to be
214   /// either zero or one and return them in the \p KnownZero and \p KnownOne
215   /// bitsets.
216   void computeKnownBitsForTargetNode(const SDValue Op,
217                                      KnownBits &Known,
218                                      const APInt &DemandedElts,
219                                      const SelectionDAG &DAG,
220                                      unsigned Depth = 0) const override;
221 
222   unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
223                                            const SelectionDAG &DAG,
224                                            unsigned Depth = 0) const override;
225 
226   /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
227   /// MachineFunction.
228   ///
229   /// \returns a RegisterSDNode representing Reg if \p RawReg is true, otherwise
230   /// a copy from the register.
231   SDValue CreateLiveInRegister(SelectionDAG &DAG,
232                                const TargetRegisterClass *RC,
233                                unsigned Reg, EVT VT,
234                                const SDLoc &SL,
235                                bool RawReg = false) const;
236   SDValue CreateLiveInRegister(SelectionDAG &DAG,
237                                const TargetRegisterClass *RC,
238                                unsigned Reg, EVT VT) const {
239     return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()));
240   }
241 
242   // Returns the raw live in register rather than a copy from it.
243   SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG,
244                                   const TargetRegisterClass *RC,
245                                   unsigned Reg, EVT VT) const {
246     return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()), true);
247   }
248 
249   /// Similar to CreateLiveInRegister, except value maybe loaded from a stack
250   /// slot rather than passed in a register.
251   SDValue loadStackInputValue(SelectionDAG &DAG,
252                               EVT VT,
253                               const SDLoc &SL,
254                               int64_t Offset) const;
255 
256   SDValue storeStackInputValue(SelectionDAG &DAG,
257                                const SDLoc &SL,
258                                SDValue Chain,
259                                SDValue StackPtr,
260                                SDValue ArgVal,
261                                int64_t Offset) const;
262 
263   SDValue loadInputValue(SelectionDAG &DAG,
264                          const TargetRegisterClass *RC,
265                          EVT VT, const SDLoc &SL,
266                          const ArgDescriptor &Arg) const;
267 
268   enum ImplicitParameter {
269     FIRST_IMPLICIT,
270     GRID_DIM = FIRST_IMPLICIT,
271     GRID_OFFSET,
272   };
273 
274   /// \brief Helper function that returns the byte offset of the given
275   /// type of implicit parameter.
276   uint32_t getImplicitParameterOffset(const AMDGPUMachineFunction *MFI,
277                                       const ImplicitParameter Param) const;
278 
279   AMDGPUAS getAMDGPUAS() const {
280     return AMDGPUASI;
281   }
282 
283   MVT getFenceOperandTy(const DataLayout &DL) const override {
284     return MVT::i32;
285   }
286 };
287 
288 namespace AMDGPUISD {
289 
290 enum NodeType : unsigned {
291   // AMDIL ISD Opcodes
292   FIRST_NUMBER = ISD::BUILTIN_OP_END,
293   UMUL,        // 32bit unsigned multiplication
294   BRANCH_COND,
295   // End AMDIL ISD Opcodes
296 
297   // Function call.
298   CALL,
299   TC_RETURN,
300   TRAP,
301 
302   // Masked control flow nodes.
303   IF,
304   ELSE,
305   LOOP,
306 
307   // A uniform kernel return that terminates the wavefront.
308   ENDPGM,
309 
310   // Return to a shader part's epilog code.
311   RETURN_TO_EPILOG,
312 
313   // Return with values from a non-entry function.
314   RET_FLAG,
315 
316   DWORDADDR,
317   FRACT,
318 
319   /// CLAMP value between 0.0 and 1.0. NaN clamped to 0, following clamp output
320   /// modifier behavior with dx10_enable.
321   CLAMP,
322 
323   // This is SETCC with the full mask result which is used for a compare with a
324   // result bit per item in the wavefront.
325   SETCC,
326   SETREG,
327   // FP ops with input and output chain.
328   FMA_W_CHAIN,
329   FMUL_W_CHAIN,
330 
331   // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
332   // Denormals handled on some parts.
333   COS_HW,
334   SIN_HW,
335   FMAX_LEGACY,
336   FMIN_LEGACY,
337   FMAX3,
338   SMAX3,
339   UMAX3,
340   FMIN3,
341   SMIN3,
342   UMIN3,
343   FMED3,
344   SMED3,
345   UMED3,
346   URECIP,
347   DIV_SCALE,
348   DIV_FMAS,
349   DIV_FIXUP,
350   // For emitting ISD::FMAD when f32 denormals are enabled because mac/mad is
351   // treated as an illegal operation.
352   FMAD_FTZ,
353   TRIG_PREOP, // 1 ULP max error for f64
354 
355   // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
356   //            For f64, max error 2^29 ULP, handles denormals.
357   RCP,
358   RSQ,
359   RCP_LEGACY,
360   RSQ_LEGACY,
361   FMUL_LEGACY,
362   RSQ_CLAMP,
363   LDEXP,
364   FP_CLASS,
365   DOT4,
366   CARRY,
367   BORROW,
368   BFE_U32, // Extract range of bits with zero extension to 32-bits.
369   BFE_I32, // Extract range of bits with sign extension to 32-bits.
370   BFI, // (src0 & src1) | (~src0 & src2)
371   BFM, // Insert a range of bits into a 32-bit word.
372   FFBH_U32, // ctlz with -1 if input is zero.
373   FFBH_I32,
374   FFBL_B32, // cttz with -1 if input is zero.
375   MUL_U24,
376   MUL_I24,
377   MULHI_U24,
378   MULHI_I24,
379   MAD_U24,
380   MAD_I24,
381   MUL_LOHI_I24,
382   MUL_LOHI_U24,
383   TEXTURE_FETCH,
384   EXPORT, // exp on SI+
385   EXPORT_DONE, // exp on SI+ with done bit set
386   R600_EXPORT,
387   CONST_ADDRESS,
388   REGISTER_LOAD,
389   REGISTER_STORE,
390   SAMPLE,
391   SAMPLEB,
392   SAMPLED,
393   SAMPLEL,
394 
395   // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
396   CVT_F32_UBYTE0,
397   CVT_F32_UBYTE1,
398   CVT_F32_UBYTE2,
399   CVT_F32_UBYTE3,
400 
401   // Convert two float 32 numbers into a single register holding two packed f16
402   // with round to zero.
403   CVT_PKRTZ_F16_F32,
404 
405   // Same as the standard node, except the high bits of the resulting integer
406   // are known 0.
407   FP_TO_FP16,
408 
409   // Wrapper around fp16 results that are known to zero the high bits.
410   FP16_ZEXT,
411 
412   /// This node is for VLIW targets and it is used to represent a vector
413   /// that is stored in consecutive registers with the same channel.
414   /// For example:
415   ///   |X  |Y|Z|W|
416   /// T0|v.x| | | |
417   /// T1|v.y| | | |
418   /// T2|v.z| | | |
419   /// T3|v.w| | | |
420   BUILD_VERTICAL_VECTOR,
421   /// Pointer to the start of the shader's constant data.
422   CONST_DATA_PTR,
423   INIT_EXEC,
424   INIT_EXEC_FROM_INPUT,
425   SENDMSG,
426   SENDMSGHALT,
427   INTERP_MOV,
428   INTERP_P1,
429   INTERP_P2,
430   PC_ADD_REL_OFFSET,
431   KILL,
432   DUMMY_CHAIN,
433   FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
434   STORE_MSKOR,
435   LOAD_CONSTANT,
436   TBUFFER_STORE_FORMAT,
437   TBUFFER_STORE_FORMAT_X3,
438   TBUFFER_LOAD_FORMAT,
439   ATOMIC_CMP_SWAP,
440   ATOMIC_INC,
441   ATOMIC_DEC,
442   BUFFER_LOAD,
443   BUFFER_LOAD_FORMAT,
444   LAST_AMDGPU_ISD_NUMBER
445 };
446 
447 
448 } // End namespace AMDGPUISD
449 
450 } // End namespace llvm
451 
452 #endif
453