1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition of the TargetLowering class that is common
11 /// to all AMD GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
17 
18 #include "AMDGPU.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/TargetLowering.h"
21 
22 namespace llvm {
23 
24 class AMDGPUMachineFunction;
25 class AMDGPUSubtarget;
26 struct ArgDescriptor;
27 
28 class AMDGPUTargetLowering : public TargetLowering {
29 private:
30   const AMDGPUSubtarget *Subtarget;
31 
32   /// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been
33   /// legalized from a smaller type VT. Need to match pre-legalized type because
34   /// the generic legalization inserts the add/sub between the select and
35   /// compare.
36   SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
37 
38 public:
39   static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
40   static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
41   static bool hasDefinedInitializer(const GlobalValue *GV);
42 
43 protected:
44   SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
45   SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
46   /// Split a vector store into multiple scalar stores.
47   /// \returns The resulting chain.
48 
49   SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
50   SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
51   SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
52   SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
53   SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
54 
55   SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
56   SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
57   SDValue LowerFLOG(SDValue Op, SelectionDAG &DAG,
58                     double Log2BaseInverted) const;
59   SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const;
60 
61   SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const;
62 
63   SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
64   SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
65   SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
66   SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
67 
68   SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
69   SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
70   SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
71   SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
72 
73   SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
74 
75 protected:
76   bool shouldCombineMemoryType(EVT VT) const;
77   SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
78   SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
79   SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const;
80   SDValue performIntrinsicWOChainCombine(SDNode *N, DAGCombinerInfo &DCI) const;
81 
82   SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL,
83                                        unsigned Opc, SDValue LHS,
84                                        uint32_t ValLo, uint32_t ValHi) const;
85   SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
86   SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
87   SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
88   SDValue performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) const;
89   SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
90   SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
91   SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const;
92   SDValue performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) const;
93   SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
94                              SDValue RHS, DAGCombinerInfo &DCI) const;
95   SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
96 
97   bool isConstantCostlierToNegate(SDValue N) const;
98   SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
99   SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
100   SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
101 
102   static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
103 
104   virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
105                                      SelectionDAG &DAG) const;
106 
107   /// Return 64-bit value Op as two 32-bit integers.
108   std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
109                                               SelectionDAG &DAG) const;
110   SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
111   SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
112 
113   /// Split a vector type into two parts. The first part is a power of two
114   /// vector. The second part is whatever is left over, and is a scalar if it
115   /// would otherwise be a 1-vector.
116   std::pair<EVT, EVT> getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const;
117 
118   /// Split a vector value into two parts of types LoVT and HiVT. HiVT could be
119   /// scalar.
120   std::pair<SDValue, SDValue> splitVector(const SDValue &N, const SDLoc &DL,
121                                           const EVT &LoVT, const EVT &HighVT,
122                                           SelectionDAG &DAG) const;
123 
124   /// Split a vector load into 2 loads of half the vector.
125   SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
126 
127   /// Widen a vector load from vec3 to vec4.
128   SDValue WidenVectorLoad(SDValue Op, SelectionDAG &DAG) const;
129 
130   /// Split a vector store into 2 stores of half the vector.
131   SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
132 
133   SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
134   SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
135   SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
136   SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
137   void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
138                                     SmallVectorImpl<SDValue> &Results) const;
139 
140   void analyzeFormalArgumentsCompute(
141     CCState &State,
142     const SmallVectorImpl<ISD::InputArg> &Ins) const;
143 
144 public:
145   AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
146 
147   bool mayIgnoreSignedZero(SDValue Op) const {
148     if (getTargetMachine().Options.NoSignedZerosFPMath)
149       return true;
150 
151     const auto Flags = Op.getNode()->getFlags();
152     if (Flags.isDefined())
153       return Flags.hasNoSignedZeros();
154 
155     return false;
156   }
157 
158   static inline SDValue stripBitcast(SDValue Val) {
159     return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(0) : Val;
160   }
161 
162   static bool allUsesHaveSourceMods(const SDNode *N,
163                                     unsigned CostThreshold = 4);
164   bool isFAbsFree(EVT VT) const override;
165   bool isFNegFree(EVT VT) const override;
166   bool isTruncateFree(EVT Src, EVT Dest) const override;
167   bool isTruncateFree(Type *Src, Type *Dest) const override;
168 
169   bool isZExtFree(Type *Src, Type *Dest) const override;
170   bool isZExtFree(EVT Src, EVT Dest) const override;
171   bool isZExtFree(SDValue Val, EVT VT2) const override;
172 
173   NegatibleCost getNegatibleCost(SDValue Op, SelectionDAG &DAG,
174                                  bool LegalOperations, bool ForCodeSize,
175                                  unsigned Depth) const override;
176 
177   bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
178 
179   EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
180                           ISD::NodeType ExtendKind) const override;
181 
182   MVT getVectorIdxTy(const DataLayout &) const override;
183   bool isSelectSupported(SelectSupportKind) const override;
184 
185   bool isFPImmLegal(const APFloat &Imm, EVT VT,
186                     bool ForCodeSize) const override;
187   bool ShouldShrinkFPConstant(EVT VT) const override;
188   bool shouldReduceLoadWidth(SDNode *Load,
189                              ISD::LoadExtType ExtType,
190                              EVT ExtVT) const override;
191 
192   bool isLoadBitCastBeneficial(EVT, EVT, const SelectionDAG &DAG,
193                                const MachineMemOperand &MMO) const final;
194 
195   bool storeOfVectorConstantIsCheap(EVT MemVT,
196                                     unsigned NumElem,
197                                     unsigned AS) const override;
198   bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
199   bool isCheapToSpeculateCttz() const override;
200   bool isCheapToSpeculateCtlz() const override;
201 
202   bool isSDNodeAlwaysUniform(const SDNode *N) const override;
203   static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
204   static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
205 
206   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
207                       const SmallVectorImpl<ISD::OutputArg> &Outs,
208                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
209                       SelectionDAG &DAG) const override;
210 
211   SDValue addTokenForArgument(SDValue Chain,
212                               SelectionDAG &DAG,
213                               MachineFrameInfo &MFI,
214                               int ClobberedFI) const;
215 
216   SDValue lowerUnhandledCall(CallLoweringInfo &CLI,
217                              SmallVectorImpl<SDValue> &InVals,
218                              StringRef Reason) const;
219   SDValue LowerCall(CallLoweringInfo &CLI,
220                     SmallVectorImpl<SDValue> &InVals) const override;
221 
222   SDValue LowerDYNAMIC_STACKALLOC(SDValue Op,
223                                   SelectionDAG &DAG) const;
224 
225   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
226   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
227   void ReplaceNodeResults(SDNode * N,
228                           SmallVectorImpl<SDValue> &Results,
229                           SelectionDAG &DAG) const override;
230 
231   SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
232                                SDValue RHS, SDValue True, SDValue False,
233                                SDValue CC, DAGCombinerInfo &DCI) const;
234 
235   const char* getTargetNodeName(unsigned Opcode) const override;
236 
237   // FIXME: Turn off MergeConsecutiveStores() before Instruction Selection for
238   // AMDGPU.  Commit r319036,
239   // (https://github.com/llvm/llvm-project/commit/db77e57ea86d941a4262ef60261692f4cb6893e6)
240   // turned on MergeConsecutiveStores() before Instruction Selection for all
241   // targets.  Enough AMDGPU compiles go into an infinite loop (
242   // MergeConsecutiveStores() merges two stores; LegalizeStoreOps() un-merges;
243   // MergeConsecutiveStores() re-merges, etc. ) to warrant turning it off for
244   // now.
245   bool mergeStoresAfterLegalization(EVT) const override { return false; }
246 
247   bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
248     return true;
249   }
250   SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
251                            int &RefinementSteps, bool &UseOneConstNR,
252                            bool Reciprocal) const override;
253   SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
254                            int &RefinementSteps) const override;
255 
256   virtual SDNode *PostISelFolding(MachineSDNode *N,
257                                   SelectionDAG &DAG) const = 0;
258 
259   /// Determine which of the bits specified in \p Mask are known to be
260   /// either zero or one and return them in the \p KnownZero and \p KnownOne
261   /// bitsets.
262   void computeKnownBitsForTargetNode(const SDValue Op,
263                                      KnownBits &Known,
264                                      const APInt &DemandedElts,
265                                      const SelectionDAG &DAG,
266                                      unsigned Depth = 0) const override;
267 
268   unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
269                                            const SelectionDAG &DAG,
270                                            unsigned Depth = 0) const override;
271 
272   unsigned computeNumSignBitsForTargetInstr(GISelKnownBits &Analysis,
273                                             Register R,
274                                             const APInt &DemandedElts,
275                                             const MachineRegisterInfo &MRI,
276                                             unsigned Depth = 0) const override;
277 
278   bool isKnownNeverNaNForTargetNode(SDValue Op,
279                                     const SelectionDAG &DAG,
280                                     bool SNaN = false,
281                                     unsigned Depth = 0) const override;
282 
283   /// Helper function that adds Reg to the LiveIn list of the DAG's
284   /// MachineFunction.
285   ///
286   /// \returns a RegisterSDNode representing Reg if \p RawReg is true, otherwise
287   /// a copy from the register.
288   SDValue CreateLiveInRegister(SelectionDAG &DAG,
289                                const TargetRegisterClass *RC,
290                                unsigned Reg, EVT VT,
291                                const SDLoc &SL,
292                                bool RawReg = false) const;
293   SDValue CreateLiveInRegister(SelectionDAG &DAG,
294                                const TargetRegisterClass *RC,
295                                unsigned Reg, EVT VT) const {
296     return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()));
297   }
298 
299   // Returns the raw live in register rather than a copy from it.
300   SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG,
301                                   const TargetRegisterClass *RC,
302                                   unsigned Reg, EVT VT) const {
303     return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()), true);
304   }
305 
306   /// Similar to CreateLiveInRegister, except value maybe loaded from a stack
307   /// slot rather than passed in a register.
308   SDValue loadStackInputValue(SelectionDAG &DAG,
309                               EVT VT,
310                               const SDLoc &SL,
311                               int64_t Offset) const;
312 
313   SDValue storeStackInputValue(SelectionDAG &DAG,
314                                const SDLoc &SL,
315                                SDValue Chain,
316                                SDValue ArgVal,
317                                int64_t Offset) const;
318 
319   SDValue loadInputValue(SelectionDAG &DAG,
320                          const TargetRegisterClass *RC,
321                          EVT VT, const SDLoc &SL,
322                          const ArgDescriptor &Arg) const;
323 
324   enum ImplicitParameter {
325     FIRST_IMPLICIT,
326     GRID_DIM = FIRST_IMPLICIT,
327     GRID_OFFSET,
328   };
329 
330   /// Helper function that returns the byte offset of the given
331   /// type of implicit parameter.
332   uint32_t getImplicitParameterOffset(const MachineFunction &MF,
333                                       const ImplicitParameter Param) const;
334 
335   MVT getFenceOperandTy(const DataLayout &DL) const override {
336     return MVT::i32;
337   }
338 
339   AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override;
340 };
341 
342 namespace AMDGPUISD {
343 
344 enum NodeType : unsigned {
345   // AMDIL ISD Opcodes
346   FIRST_NUMBER = ISD::BUILTIN_OP_END,
347   UMUL,        // 32bit unsigned multiplication
348   BRANCH_COND,
349   // End AMDIL ISD Opcodes
350 
351   // Function call.
352   CALL,
353   TC_RETURN,
354   TRAP,
355 
356   // Masked control flow nodes.
357   IF,
358   ELSE,
359   LOOP,
360 
361   // A uniform kernel return that terminates the wavefront.
362   ENDPGM,
363 
364   // Return to a shader part's epilog code.
365   RETURN_TO_EPILOG,
366 
367   // Return with values from a non-entry function.
368   RET_FLAG,
369 
370   DWORDADDR,
371   FRACT,
372 
373   /// CLAMP value between 0.0 and 1.0. NaN clamped to 0, following clamp output
374   /// modifier behavior with dx10_enable.
375   CLAMP,
376 
377   // This is SETCC with the full mask result which is used for a compare with a
378   // result bit per item in the wavefront.
379   SETCC,
380   SETREG,
381 
382   DENORM_MODE,
383 
384   // FP ops with input and output chain.
385   FMA_W_CHAIN,
386   FMUL_W_CHAIN,
387 
388   // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
389   // Denormals handled on some parts.
390   COS_HW,
391   SIN_HW,
392   FMAX_LEGACY,
393   FMIN_LEGACY,
394 
395   FMAX3,
396   SMAX3,
397   UMAX3,
398   FMIN3,
399   SMIN3,
400   UMIN3,
401   FMED3,
402   SMED3,
403   UMED3,
404   FDOT2,
405   URECIP,
406   DIV_SCALE,
407   DIV_FMAS,
408   DIV_FIXUP,
409   // For emitting ISD::FMAD when f32 denormals are enabled because mac/mad is
410   // treated as an illegal operation.
411   FMAD_FTZ,
412   TRIG_PREOP, // 1 ULP max error for f64
413 
414   // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
415   //            For f64, max error 2^29 ULP, handles denormals.
416   RCP,
417   RSQ,
418   RCP_LEGACY,
419   RSQ_LEGACY,
420   RCP_IFLAG,
421   FMUL_LEGACY,
422   RSQ_CLAMP,
423   LDEXP,
424   FP_CLASS,
425   DOT4,
426   CARRY,
427   BORROW,
428   BFE_U32, // Extract range of bits with zero extension to 32-bits.
429   BFE_I32, // Extract range of bits with sign extension to 32-bits.
430   BFI, // (src0 & src1) | (~src0 & src2)
431   BFM, // Insert a range of bits into a 32-bit word.
432   FFBH_U32, // ctlz with -1 if input is zero.
433   FFBH_I32,
434   FFBL_B32, // cttz with -1 if input is zero.
435   MUL_U24,
436   MUL_I24,
437   MULHI_U24,
438   MULHI_I24,
439   MAD_U24,
440   MAD_I24,
441   MAD_U64_U32,
442   MAD_I64_I32,
443   MUL_LOHI_I24,
444   MUL_LOHI_U24,
445   PERM,
446   TEXTURE_FETCH,
447   R600_EXPORT,
448   CONST_ADDRESS,
449   REGISTER_LOAD,
450   REGISTER_STORE,
451   SAMPLE,
452   SAMPLEB,
453   SAMPLED,
454   SAMPLEL,
455 
456   // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
457   CVT_F32_UBYTE0,
458   CVT_F32_UBYTE1,
459   CVT_F32_UBYTE2,
460   CVT_F32_UBYTE3,
461 
462   // Convert two float 32 numbers into a single register holding two packed f16
463   // with round to zero.
464   CVT_PKRTZ_F16_F32,
465   CVT_PKNORM_I16_F32,
466   CVT_PKNORM_U16_F32,
467   CVT_PK_I16_I32,
468   CVT_PK_U16_U32,
469 
470   // Same as the standard node, except the high bits of the resulting integer
471   // are known 0.
472   FP_TO_FP16,
473 
474   // Wrapper around fp16 results that are known to zero the high bits.
475   FP16_ZEXT,
476 
477   /// This node is for VLIW targets and it is used to represent a vector
478   /// that is stored in consecutive registers with the same channel.
479   /// For example:
480   ///   |X  |Y|Z|W|
481   /// T0|v.x| | | |
482   /// T1|v.y| | | |
483   /// T2|v.z| | | |
484   /// T3|v.w| | | |
485   BUILD_VERTICAL_VECTOR,
486   /// Pointer to the start of the shader's constant data.
487   CONST_DATA_PTR,
488   PC_ADD_REL_OFFSET,
489   LDS,
490   DUMMY_CHAIN,
491   FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
492   LOAD_D16_HI,
493   LOAD_D16_LO,
494   LOAD_D16_HI_I8,
495   LOAD_D16_HI_U8,
496   LOAD_D16_LO_I8,
497   LOAD_D16_LO_U8,
498 
499   STORE_MSKOR,
500   LOAD_CONSTANT,
501   TBUFFER_STORE_FORMAT,
502   TBUFFER_STORE_FORMAT_D16,
503   TBUFFER_LOAD_FORMAT,
504   TBUFFER_LOAD_FORMAT_D16,
505   DS_ORDERED_COUNT,
506   ATOMIC_CMP_SWAP,
507   ATOMIC_INC,
508   ATOMIC_DEC,
509   ATOMIC_LOAD_FMIN,
510   ATOMIC_LOAD_FMAX,
511   BUFFER_LOAD,
512   BUFFER_LOAD_UBYTE,
513   BUFFER_LOAD_USHORT,
514   BUFFER_LOAD_BYTE,
515   BUFFER_LOAD_SHORT,
516   BUFFER_LOAD_FORMAT,
517   BUFFER_LOAD_FORMAT_D16,
518   SBUFFER_LOAD,
519   BUFFER_STORE,
520   BUFFER_STORE_BYTE,
521   BUFFER_STORE_SHORT,
522   BUFFER_STORE_FORMAT,
523   BUFFER_STORE_FORMAT_D16,
524   BUFFER_ATOMIC_SWAP,
525   BUFFER_ATOMIC_ADD,
526   BUFFER_ATOMIC_SUB,
527   BUFFER_ATOMIC_SMIN,
528   BUFFER_ATOMIC_UMIN,
529   BUFFER_ATOMIC_SMAX,
530   BUFFER_ATOMIC_UMAX,
531   BUFFER_ATOMIC_AND,
532   BUFFER_ATOMIC_OR,
533   BUFFER_ATOMIC_XOR,
534   BUFFER_ATOMIC_INC,
535   BUFFER_ATOMIC_DEC,
536   BUFFER_ATOMIC_CMPSWAP,
537   BUFFER_ATOMIC_FADD,
538   BUFFER_ATOMIC_PK_FADD,
539   ATOMIC_PK_FADD,
540 
541   LAST_AMDGPU_ISD_NUMBER
542 };
543 
544 
545 } // End namespace AMDGPUISD
546 
547 } // End namespace llvm
548 
549 #endif
550