1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Interface definition of the TargetLowering class that is common
12 /// to all AMD GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
17 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
18 
19 #include "llvm/Target/TargetLowering.h"
20 
21 namespace llvm {
22 
23 class AMDGPUMachineFunction;
24 class AMDGPUSubtarget;
25 class MachineRegisterInfo;
26 
27 class AMDGPUTargetLowering : public TargetLowering {
28 protected:
29   const AMDGPUSubtarget *Subtarget;
30 
31   SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV,
32                                    const SDValue &InitPtr,
33                                    SDValue Chain,
34                                    SelectionDAG &DAG) const;
35   SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
36   SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
37   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
38   /// \brief Lower vector stores by merging the vector elements into an integer
39   /// of the same bitwidth.
40   SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
41   /// \brief Split a vector store into multiple scalar stores.
42   /// \returns The resulting chain.
43 
44   SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
45   SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
46   SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
47   SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
48   SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
49 
50   SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const;
51   SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
52   SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
53   SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
54 
55   SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
56 
57   SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
58   SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
59   SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
60   SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
61 
62   SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
63   SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
64   SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
65 
66   SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
67 
68 protected:
69   SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
70   SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
71   SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
72   SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
73   SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
74   SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
75   SDValue performCtlzCombine(SDLoc SL, SDValue Cond, SDValue LHS, SDValue RHS,
76                              DAGCombinerInfo &DCI) const;
77   SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
78 
79   static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
80   static EVT getEquivalentLoadRegType(LLVMContext &Context, EVT VT);
81 
82   virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
83                                      SelectionDAG &DAG) const;
84 
85   /// Return 64-bit value Op as two 32-bit integers.
86   std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
87                                               SelectionDAG &DAG) const;
88   SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
89   SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
90 
91   /// \brief Split a vector load into 2 loads of half the vector.
92   SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
93 
94   /// \brief Split a vector store into 2 stores of half the vector.
95   SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
96 
97   SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
98   SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
99   SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
100   SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
101   void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
102                                     SmallVectorImpl<SDValue> &Results) const;
103   /// The SelectionDAGBuilder will automatically promote function arguments
104   /// with illegal types.  However, this does not work for the AMDGPU targets
105   /// since the function arguments are stored in memory as these illegal types.
106   /// In order to handle this properly we need to get the origianl types sizes
107   /// from the LLVM IR Function and fixup the ISD:InputArg values before
108   /// passing them to AnalyzeFormalArguments()
109   void getOriginalFunctionArgs(SelectionDAG &DAG,
110                                const Function *F,
111                                const SmallVectorImpl<ISD::InputArg> &Ins,
112                                SmallVectorImpl<ISD::InputArg> &OrigIns) const;
113   void AnalyzeFormalArguments(CCState &State,
114                               const SmallVectorImpl<ISD::InputArg> &Ins) const;
115   void AnalyzeReturn(CCState &State,
116                      const SmallVectorImpl<ISD::OutputArg> &Outs) const;
117 
118 public:
119   AMDGPUTargetLowering(TargetMachine &TM, const AMDGPUSubtarget &STI);
120 
121   bool isFAbsFree(EVT VT) const override;
122   bool isFNegFree(EVT VT) const override;
123   bool isTruncateFree(EVT Src, EVT Dest) const override;
124   bool isTruncateFree(Type *Src, Type *Dest) const override;
125 
126   bool isZExtFree(Type *Src, Type *Dest) const override;
127   bool isZExtFree(EVT Src, EVT Dest) const override;
128   bool isZExtFree(SDValue Val, EVT VT2) const override;
129 
130   bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
131 
132   MVT getVectorIdxTy(const DataLayout &) const override;
133   bool isSelectSupported(SelectSupportKind) const override;
134 
135   bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
136   bool ShouldShrinkFPConstant(EVT VT) const override;
137   bool shouldReduceLoadWidth(SDNode *Load,
138                              ISD::LoadExtType ExtType,
139                              EVT ExtVT) const override;
140 
141   bool isLoadBitCastBeneficial(EVT, EVT) const override;
142 
143   bool storeOfVectorConstantIsCheap(EVT MemVT,
144                                     unsigned NumElem,
145                                     unsigned AS) const override;
146   bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
147   bool isCheapToSpeculateCttz() const override;
148   bool isCheapToSpeculateCtlz() const override;
149 
150   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
151                       bool isVarArg,
152                       const SmallVectorImpl<ISD::OutputArg> &Outs,
153                       const SmallVectorImpl<SDValue> &OutVals,
154                       SDLoc DL, SelectionDAG &DAG) const override;
155   SDValue LowerCall(CallLoweringInfo &CLI,
156                     SmallVectorImpl<SDValue> &InVals) const override;
157 
158   SDValue LowerDYNAMIC_STACKALLOC(SDValue Op,
159                                   SelectionDAG &DAG) const;
160 
161   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
162   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
163   void ReplaceNodeResults(SDNode * N,
164                           SmallVectorImpl<SDValue> &Results,
165                           SelectionDAG &DAG) const override;
166 
167   SDValue CombineFMinMaxLegacy(SDLoc DL,
168                                EVT VT,
169                                SDValue LHS,
170                                SDValue RHS,
171                                SDValue True,
172                                SDValue False,
173                                SDValue CC,
174                                DAGCombinerInfo &DCI) const;
175 
176   const char* getTargetNodeName(unsigned Opcode) const override;
177 
178   SDValue getRsqrtEstimate(SDValue Operand,
179                            DAGCombinerInfo &DCI,
180                            unsigned &RefinementSteps,
181                            bool &UseOneConstNR) const override;
182   SDValue getRecipEstimate(SDValue Operand,
183                            DAGCombinerInfo &DCI,
184                            unsigned &RefinementSteps) const override;
185 
186   virtual SDNode *PostISelFolding(MachineSDNode *N,
187                                   SelectionDAG &DAG) const = 0;
188 
189   /// \brief Determine which of the bits specified in \p Mask are known to be
190   /// either zero or one and return them in the \p KnownZero and \p KnownOne
191   /// bitsets.
192   void computeKnownBitsForTargetNode(const SDValue Op,
193                                      APInt &KnownZero,
194                                      APInt &KnownOne,
195                                      const SelectionDAG &DAG,
196                                      unsigned Depth = 0) const override;
197 
198   unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG,
199                                            unsigned Depth = 0) const override;
200 
201   /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
202   /// MachineFunction.
203   ///
204   /// \returns a RegisterSDNode representing Reg.
205   virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
206                                        const TargetRegisterClass *RC,
207                                        unsigned Reg, EVT VT) const;
208 
209   enum ImplicitParameter {
210     GRID_DIM,
211     GRID_OFFSET
212   };
213 
214   /// \brief Helper function that returns the byte offset of the given
215   /// type of implicit parameter.
216   uint32_t getImplicitParameterOffset(const AMDGPUMachineFunction *MFI,
217                                       const ImplicitParameter Param) const;
218 };
219 
220 namespace AMDGPUISD {
221 
222 enum NodeType : unsigned {
223   // AMDIL ISD Opcodes
224   FIRST_NUMBER = ISD::BUILTIN_OP_END,
225   CALL,        // Function call based on a single integer
226   UMUL,        // 32bit unsigned multiplication
227   RET_FLAG,
228   BRANCH_COND,
229   // End AMDIL ISD Opcodes
230   DWORDADDR,
231   FRACT,
232   CLAMP,
233 
234   // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
235   // Denormals handled on some parts.
236   COS_HW,
237   SIN_HW,
238   FMAX_LEGACY,
239   FMIN_LEGACY,
240   FMAX3,
241   SMAX3,
242   UMAX3,
243   FMIN3,
244   SMIN3,
245   UMIN3,
246   FMED3,
247   SMED3,
248   UMED3,
249   URECIP,
250   DIV_SCALE,
251   DIV_FMAS,
252   DIV_FIXUP,
253   TRIG_PREOP, // 1 ULP max error for f64
254 
255   // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
256   //            For f64, max error 2^29 ULP, handles denormals.
257   RCP,
258   RSQ,
259   RSQ_LEGACY,
260   RSQ_CLAMP,
261   LDEXP,
262   FP_CLASS,
263   DOT4,
264   CARRY,
265   BORROW,
266   BFE_U32, // Extract range of bits with zero extension to 32-bits.
267   BFE_I32, // Extract range of bits with sign extension to 32-bits.
268   BFI, // (src0 & src1) | (~src0 & src2)
269   BFM, // Insert a range of bits into a 32-bit word.
270   FFBH_U32, // ctlz with -1 if input is zero.
271   MUL_U24,
272   MUL_I24,
273   MAD_U24,
274   MAD_I24,
275   TEXTURE_FETCH,
276   EXPORT,
277   CONST_ADDRESS,
278   REGISTER_LOAD,
279   REGISTER_STORE,
280   LOAD_INPUT,
281   SAMPLE,
282   SAMPLEB,
283   SAMPLED,
284   SAMPLEL,
285 
286   // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
287   CVT_F32_UBYTE0,
288   CVT_F32_UBYTE1,
289   CVT_F32_UBYTE2,
290   CVT_F32_UBYTE3,
291   /// This node is for VLIW targets and it is used to represent a vector
292   /// that is stored in consecutive registers with the same channel.
293   /// For example:
294   ///   |X  |Y|Z|W|
295   /// T0|v.x| | | |
296   /// T1|v.y| | | |
297   /// T2|v.z| | | |
298   /// T3|v.w| | | |
299   BUILD_VERTICAL_VECTOR,
300   /// Pointer to the start of the shader's constant data.
301   CONST_DATA_PTR,
302   SENDMSG,
303   INTERP_MOV,
304   INTERP_P1,
305   INTERP_P2,
306   FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
307   STORE_MSKOR,
308   LOAD_CONSTANT,
309   TBUFFER_STORE_FORMAT,
310   ATOMIC_CMP_SWAP,
311   ATOMIC_INC,
312   ATOMIC_DEC,
313   LAST_AMDGPU_ISD_NUMBER
314 };
315 
316 
317 } // End namespace AMDGPUISD
318 
319 } // End namespace llvm
320 
321 #endif
322