1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Interface definition of the TargetLowering class that is common
12 /// to all AMD GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_R600_AMDGPUISELLOWERING_H
17 #define LLVM_LIB_TARGET_R600_AMDGPUISELLOWERING_H
18 
19 #include "llvm/Target/TargetLowering.h"
20 
21 namespace llvm {
22 
23 class AMDGPUMachineFunction;
24 class AMDGPUSubtarget;
25 class MachineRegisterInfo;
26 
27 class AMDGPUTargetLowering : public TargetLowering {
28 protected:
29   const AMDGPUSubtarget *Subtarget;
30 
31   SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV,
32                                    const SDValue &InitPtr,
33                                    SDValue Chain,
34                                    SelectionDAG &DAG) const;
35   SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
36   SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
37   SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
38   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
39   /// \brief Lower vector stores by merging the vector elements into an integer
40   /// of the same bitwidth.
41   SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
42   /// \brief Split a vector store into multiple scalar stores.
43   /// \returns The resulting chain.
44 
45   SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
46   SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
47   SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
48   SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
49   SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
50 
51   SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const;
52   SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
53   SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
54   SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
55 
56   SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
57 
58   SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
59   SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
60   SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
61   SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
62 
63   SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
64   SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
65   SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
66 
67   SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
68 
69 protected:
70   SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
71   SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
72   SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
73   SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
74   SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
75   SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
76   SDValue performCtlzCombine(SDLoc SL, SDValue Cond, SDValue LHS, SDValue RHS,
77                              DAGCombinerInfo &DCI) const;
78   SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
79 
80   static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
81   static EVT getEquivalentLoadRegType(LLVMContext &Context, EVT VT);
82 
83   virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
84                                      SelectionDAG &DAG) const;
85 
86   /// Return 64-bit value Op as two 32-bit integers.
87   std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
88                                               SelectionDAG &DAG) const;
89   SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
90   SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
91 
92   /// \brief Split a vector load into a scalar load of each component.
93   SDValue ScalarizeVectorLoad(SDValue Op, SelectionDAG &DAG) const;
94 
95   /// \brief Split a vector load into 2 loads of half the vector.
96   SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
97 
98   /// \brief Split a vector store into a scalar store of each component.
99   SDValue ScalarizeVectorStore(SDValue Op, SelectionDAG &DAG) const;
100 
101   /// \brief Split a vector store into 2 stores of half the vector.
102   SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
103 
104   SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
105   SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
106   SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
107   SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
108   void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
109                                     SmallVectorImpl<SDValue> &Results) const;
110   bool isHWTrueValue(SDValue Op) const;
111   bool isHWFalseValue(SDValue Op) const;
112 
113   /// The SelectionDAGBuilder will automatically promote function arguments
114   /// with illegal types.  However, this does not work for the AMDGPU targets
115   /// since the function arguments are stored in memory as these illegal types.
116   /// In order to handle this properly we need to get the origianl types sizes
117   /// from the LLVM IR Function and fixup the ISD:InputArg values before
118   /// passing them to AnalyzeFormalArguments()
119   void getOriginalFunctionArgs(SelectionDAG &DAG,
120                                const Function *F,
121                                const SmallVectorImpl<ISD::InputArg> &Ins,
122                                SmallVectorImpl<ISD::InputArg> &OrigIns) const;
123   void AnalyzeFormalArguments(CCState &State,
124                               const SmallVectorImpl<ISD::InputArg> &Ins) const;
125   void AnalyzeReturn(CCState &State,
126                      const SmallVectorImpl<ISD::OutputArg> &Outs) const;
127 
128 public:
129   AMDGPUTargetLowering(TargetMachine &TM, const AMDGPUSubtarget &STI);
130 
131   bool isFAbsFree(EVT VT) const override;
132   bool isFNegFree(EVT VT) const override;
133   bool isTruncateFree(EVT Src, EVT Dest) const override;
134   bool isTruncateFree(Type *Src, Type *Dest) const override;
135 
136   bool isZExtFree(Type *Src, Type *Dest) const override;
137   bool isZExtFree(EVT Src, EVT Dest) const override;
138   bool isZExtFree(SDValue Val, EVT VT2) const override;
139 
140   bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
141 
142   MVT getVectorIdxTy(const DataLayout &) const override;
143   bool isSelectSupported(SelectSupportKind) const override;
144 
145   bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
146   bool ShouldShrinkFPConstant(EVT VT) const override;
147   bool shouldReduceLoadWidth(SDNode *Load,
148                              ISD::LoadExtType ExtType,
149                              EVT ExtVT) const override;
150 
151   bool isLoadBitCastBeneficial(EVT, EVT) const override;
152 
153   bool storeOfVectorConstantIsCheap(EVT MemVT,
154                                     unsigned NumElem,
155                                     unsigned AS) const override;
156   bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
157   bool isCheapToSpeculateCttz() const override;
158   bool isCheapToSpeculateCtlz() const override;
159 
160   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
161                       bool isVarArg,
162                       const SmallVectorImpl<ISD::OutputArg> &Outs,
163                       const SmallVectorImpl<SDValue> &OutVals,
164                       SDLoc DL, SelectionDAG &DAG) const override;
165   SDValue LowerCall(CallLoweringInfo &CLI,
166                     SmallVectorImpl<SDValue> &InVals) const override;
167 
168   SDValue LowerDYNAMIC_STACKALLOC(SDValue Op,
169                                   SelectionDAG &DAG) const;
170 
171   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
172   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
173   void ReplaceNodeResults(SDNode * N,
174                           SmallVectorImpl<SDValue> &Results,
175                           SelectionDAG &DAG) const override;
176 
177   SDValue CombineFMinMaxLegacy(SDLoc DL,
178                                EVT VT,
179                                SDValue LHS,
180                                SDValue RHS,
181                                SDValue True,
182                                SDValue False,
183                                SDValue CC,
184                                DAGCombinerInfo &DCI) const;
185 
186   const char* getTargetNodeName(unsigned Opcode) const override;
187 
188   SDValue getRsqrtEstimate(SDValue Operand,
189                            DAGCombinerInfo &DCI,
190                            unsigned &RefinementSteps,
191                            bool &UseOneConstNR) const override;
192   SDValue getRecipEstimate(SDValue Operand,
193                            DAGCombinerInfo &DCI,
194                            unsigned &RefinementSteps) const override;
195 
196   virtual SDNode *PostISelFolding(MachineSDNode *N,
197                                   SelectionDAG &DAG) const {
198     return N;
199   }
200 
201   /// \brief Determine which of the bits specified in \p Mask are known to be
202   /// either zero or one and return them in the \p KnownZero and \p KnownOne
203   /// bitsets.
204   void computeKnownBitsForTargetNode(const SDValue Op,
205                                      APInt &KnownZero,
206                                      APInt &KnownOne,
207                                      const SelectionDAG &DAG,
208                                      unsigned Depth = 0) const override;
209 
210   unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG,
211                                            unsigned Depth = 0) const override;
212 
213   /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
214   /// MachineFunction.
215   ///
216   /// \returns a RegisterSDNode representing Reg.
217   virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
218                                        const TargetRegisterClass *RC,
219                                        unsigned Reg, EVT VT) const;
220 
221   enum ImplicitParameter {
222     GRID_DIM,
223     GRID_OFFSET
224   };
225 
226   /// \brief Helper function that returns the byte offset of the given
227   /// type of implicit parameter.
228   uint32_t getImplicitParameterOffset(const AMDGPUMachineFunction *MFI,
229                                       const ImplicitParameter Param) const;
230 };
231 
232 namespace AMDGPUISD {
233 
234 enum NodeType : unsigned {
235   // AMDIL ISD Opcodes
236   FIRST_NUMBER = ISD::BUILTIN_OP_END,
237   CALL,        // Function call based on a single integer
238   UMUL,        // 32bit unsigned multiplication
239   RET_FLAG,
240   BRANCH_COND,
241   // End AMDIL ISD Opcodes
242   DWORDADDR,
243   FRACT,
244   CLAMP,
245 
246   // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
247   // Denormals handled on some parts.
248   COS_HW,
249   SIN_HW,
250   FMAX_LEGACY,
251   FMIN_LEGACY,
252   FMAX3,
253   SMAX3,
254   UMAX3,
255   FMIN3,
256   SMIN3,
257   UMIN3,
258   FMED3,
259   SMED3,
260   UMED3,
261   URECIP,
262   DIV_SCALE,
263   DIV_FMAS,
264   DIV_FIXUP,
265   TRIG_PREOP, // 1 ULP max error for f64
266 
267   // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
268   //            For f64, max error 2^29 ULP, handles denormals.
269   RCP,
270   RSQ,
271   RSQ_LEGACY,
272   RSQ_CLAMP,
273   LDEXP,
274   FP_CLASS,
275   DOT4,
276   CARRY,
277   BORROW,
278   BFE_U32, // Extract range of bits with zero extension to 32-bits.
279   BFE_I32, // Extract range of bits with sign extension to 32-bits.
280   BFI, // (src0 & src1) | (~src0 & src2)
281   BFM, // Insert a range of bits into a 32-bit word.
282   FFBH_U32, // ctlz with -1 if input is zero.
283   MUL_U24,
284   MUL_I24,
285   MAD_U24,
286   MAD_I24,
287   TEXTURE_FETCH,
288   EXPORT,
289   CONST_ADDRESS,
290   REGISTER_LOAD,
291   REGISTER_STORE,
292   LOAD_INPUT,
293   SAMPLE,
294   SAMPLEB,
295   SAMPLED,
296   SAMPLEL,
297 
298   // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
299   CVT_F32_UBYTE0,
300   CVT_F32_UBYTE1,
301   CVT_F32_UBYTE2,
302   CVT_F32_UBYTE3,
303   /// This node is for VLIW targets and it is used to represent a vector
304   /// that is stored in consecutive registers with the same channel.
305   /// For example:
306   ///   |X  |Y|Z|W|
307   /// T0|v.x| | | |
308   /// T1|v.y| | | |
309   /// T2|v.z| | | |
310   /// T3|v.w| | | |
311   BUILD_VERTICAL_VECTOR,
312   /// Pointer to the start of the shader's constant data.
313   CONST_DATA_PTR,
314   SENDMSG,
315   INTERP_MOV,
316   INTERP_P1,
317   INTERP_P2,
318   FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
319   STORE_MSKOR,
320   LOAD_CONSTANT,
321   TBUFFER_STORE_FORMAT,
322   LAST_AMDGPU_ISD_NUMBER
323 };
324 
325 
326 } // End namespace AMDGPUISD
327 
328 } // End namespace llvm
329 
330 #endif
331