1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition of the TargetLowering class that is common
11 /// to all AMD GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
17 
18 #include "AMDGPU.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/TargetLowering.h"
21 
22 namespace llvm {
23 
24 class AMDGPUMachineFunction;
25 class AMDGPUSubtarget;
26 struct ArgDescriptor;
27 
28 class AMDGPUTargetLowering : public TargetLowering {
29 private:
30   const AMDGPUSubtarget *Subtarget;
31 
32   /// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been
33   /// legalized from a smaller type VT. Need to match pre-legalized type because
34   /// the generic legalization inserts the add/sub between the select and
35   /// compare.
36   SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
37 
38 public:
39   static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
40   static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
41 
42 protected:
43   SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
44   SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
45   /// Split a vector store into multiple scalar stores.
46   /// \returns The resulting chain.
47 
48   SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
49   SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
50   SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
51   SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
52   SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
53 
54   SDValue LowerFROUND32_16(SDValue Op, SelectionDAG &DAG) const;
55   SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
56   SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
57   SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
58   SDValue LowerFLOG(SDValue Op, SelectionDAG &DAG,
59                     double Log2BaseInverted) const;
60   SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const;
61 
62   SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const;
63 
64   SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
65   SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
66   SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
67   SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
68 
69   SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
70   SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
71   SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
72   SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
73 
74   SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
75 
76 protected:
77   bool shouldCombineMemoryType(EVT VT) const;
78   SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
79   SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
80   SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const;
81 
82   SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL,
83                                        unsigned Opc, SDValue LHS,
84                                        uint32_t ValLo, uint32_t ValHi) const;
85   SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
86   SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
87   SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
88   SDValue performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) const;
89   SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
90   SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
91   SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const;
92   SDValue performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) const;
93   SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
94                              SDValue RHS, DAGCombinerInfo &DCI) const;
95   SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
96 
97   bool isConstantCostlierToNegate(SDValue N) const;
98   SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
99   SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
100   SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
101 
102   static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
103 
104   virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
105                                      SelectionDAG &DAG) const;
106 
107   /// Return 64-bit value Op as two 32-bit integers.
108   std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
109                                               SelectionDAG &DAG) const;
110   SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
111   SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
112 
113   /// Split a vector type into two parts. The first part is a power of two
114   /// vector. The second part is whatever is left over, and is a scalar if it
115   /// would otherwise be a 1-vector.
116   std::pair<EVT, EVT> getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const;
117 
118   /// Split a vector value into two parts of types LoVT and HiVT. HiVT could be
119   /// scalar.
120   std::pair<SDValue, SDValue> splitVector(const SDValue &N, const SDLoc &DL,
121                                           const EVT &LoVT, const EVT &HighVT,
122                                           SelectionDAG &DAG) const;
123 
124   /// Split a vector load into 2 loads of half the vector.
125   SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
126 
127   /// Widen a vector load from vec3 to vec4.
128   SDValue WidenVectorLoad(SDValue Op, SelectionDAG &DAG) const;
129 
130   /// Split a vector store into 2 stores of half the vector.
131   SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
132 
133   SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
134   SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
135   SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
136   SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
137   void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
138                                     SmallVectorImpl<SDValue> &Results) const;
139 
140   void analyzeFormalArgumentsCompute(
141     CCState &State,
142     const SmallVectorImpl<ISD::InputArg> &Ins) const;
143 
144 public:
145   AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
146 
147   bool mayIgnoreSignedZero(SDValue Op) const {
148     if (getTargetMachine().Options.NoSignedZerosFPMath)
149       return true;
150 
151     const auto Flags = Op.getNode()->getFlags();
152     if (Flags.isDefined())
153       return Flags.hasNoSignedZeros();
154 
155     return false;
156   }
157 
158   static inline SDValue stripBitcast(SDValue Val) {
159     return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(0) : Val;
160   }
161 
162   static bool allUsesHaveSourceMods(const SDNode *N,
163                                     unsigned CostThreshold = 4);
164   bool isFAbsFree(EVT VT) const override;
165   bool isFNegFree(EVT VT) const override;
166   bool isTruncateFree(EVT Src, EVT Dest) const override;
167   bool isTruncateFree(Type *Src, Type *Dest) const override;
168 
169   bool isZExtFree(Type *Src, Type *Dest) const override;
170   bool isZExtFree(EVT Src, EVT Dest) const override;
171   bool isZExtFree(SDValue Val, EVT VT2) const override;
172 
173   bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
174 
175   MVT getVectorIdxTy(const DataLayout &) const override;
176   bool isSelectSupported(SelectSupportKind) const override;
177 
178   bool isFPImmLegal(const APFloat &Imm, EVT VT,
179                     bool ForCodeSize) const override;
180   bool ShouldShrinkFPConstant(EVT VT) const override;
181   bool shouldReduceLoadWidth(SDNode *Load,
182                              ISD::LoadExtType ExtType,
183                              EVT ExtVT) const override;
184 
185   bool isLoadBitCastBeneficial(EVT, EVT) const final;
186 
187   bool storeOfVectorConstantIsCheap(EVT MemVT,
188                                     unsigned NumElem,
189                                     unsigned AS) const override;
190   bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
191   bool isCheapToSpeculateCttz() const override;
192   bool isCheapToSpeculateCtlz() const override;
193 
194   bool isSDNodeAlwaysUniform(const SDNode *N) const override;
195   static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
196   static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
197 
198   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
199                       const SmallVectorImpl<ISD::OutputArg> &Outs,
200                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
201                       SelectionDAG &DAG) const override;
202 
203   SDValue addTokenForArgument(SDValue Chain,
204                               SelectionDAG &DAG,
205                               MachineFrameInfo &MFI,
206                               int ClobberedFI) const;
207 
208   SDValue lowerUnhandledCall(CallLoweringInfo &CLI,
209                              SmallVectorImpl<SDValue> &InVals,
210                              StringRef Reason) const;
211   SDValue LowerCall(CallLoweringInfo &CLI,
212                     SmallVectorImpl<SDValue> &InVals) const override;
213 
214   SDValue LowerDYNAMIC_STACKALLOC(SDValue Op,
215                                   SelectionDAG &DAG) const;
216 
217   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
218   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
219   void ReplaceNodeResults(SDNode * N,
220                           SmallVectorImpl<SDValue> &Results,
221                           SelectionDAG &DAG) const override;
222 
223   SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
224                                SDValue RHS, SDValue True, SDValue False,
225                                SDValue CC, DAGCombinerInfo &DCI) const;
226 
227   const char* getTargetNodeName(unsigned Opcode) const override;
228 
229   // FIXME: Turn off MergeConsecutiveStores() before Instruction Selection for
230   // AMDGPU.  Commit r319036,
231   // (https://github.com/llvm/llvm-project/commit/db77e57ea86d941a4262ef60261692f4cb6893e6)
232   // turned on MergeConsecutiveStores() before Instruction Selection for all
233   // targets.  Enough AMDGPU compiles go into an infinite loop (
234   // MergeConsecutiveStores() merges two stores; LegalizeStoreOps() un-merges;
235   // MergeConsecutiveStores() re-merges, etc. ) to warrant turning it off for
236   // now.
237   bool mergeStoresAfterLegalization(EVT) const override { return false; }
238 
239   bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
240     return true;
241   }
242   SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
243                            int &RefinementSteps, bool &UseOneConstNR,
244                            bool Reciprocal) const override;
245   SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
246                            int &RefinementSteps) const override;
247 
248   virtual SDNode *PostISelFolding(MachineSDNode *N,
249                                   SelectionDAG &DAG) const = 0;
250 
251   /// Determine which of the bits specified in \p Mask are known to be
252   /// either zero or one and return them in the \p KnownZero and \p KnownOne
253   /// bitsets.
254   void computeKnownBitsForTargetNode(const SDValue Op,
255                                      KnownBits &Known,
256                                      const APInt &DemandedElts,
257                                      const SelectionDAG &DAG,
258                                      unsigned Depth = 0) const override;
259 
260   unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
261                                            const SelectionDAG &DAG,
262                                            unsigned Depth = 0) const override;
263 
264   bool isKnownNeverNaNForTargetNode(SDValue Op,
265                                     const SelectionDAG &DAG,
266                                     bool SNaN = false,
267                                     unsigned Depth = 0) const override;
268 
269   /// Helper function that adds Reg to the LiveIn list of the DAG's
270   /// MachineFunction.
271   ///
272   /// \returns a RegisterSDNode representing Reg if \p RawReg is true, otherwise
273   /// a copy from the register.
274   SDValue CreateLiveInRegister(SelectionDAG &DAG,
275                                const TargetRegisterClass *RC,
276                                unsigned Reg, EVT VT,
277                                const SDLoc &SL,
278                                bool RawReg = false) const;
279   SDValue CreateLiveInRegister(SelectionDAG &DAG,
280                                const TargetRegisterClass *RC,
281                                unsigned Reg, EVT VT) const {
282     return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()));
283   }
284 
285   // Returns the raw live in register rather than a copy from it.
286   SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG,
287                                   const TargetRegisterClass *RC,
288                                   unsigned Reg, EVT VT) const {
289     return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()), true);
290   }
291 
292   /// Similar to CreateLiveInRegister, except value maybe loaded from a stack
293   /// slot rather than passed in a register.
294   SDValue loadStackInputValue(SelectionDAG &DAG,
295                               EVT VT,
296                               const SDLoc &SL,
297                               int64_t Offset) const;
298 
299   SDValue storeStackInputValue(SelectionDAG &DAG,
300                                const SDLoc &SL,
301                                SDValue Chain,
302                                SDValue ArgVal,
303                                int64_t Offset) const;
304 
305   SDValue loadInputValue(SelectionDAG &DAG,
306                          const TargetRegisterClass *RC,
307                          EVT VT, const SDLoc &SL,
308                          const ArgDescriptor &Arg) const;
309 
310   enum ImplicitParameter {
311     FIRST_IMPLICIT,
312     GRID_DIM = FIRST_IMPLICIT,
313     GRID_OFFSET,
314   };
315 
316   /// Helper function that returns the byte offset of the given
317   /// type of implicit parameter.
318   uint32_t getImplicitParameterOffset(const MachineFunction &MF,
319                                       const ImplicitParameter Param) const;
320 
321   MVT getFenceOperandTy(const DataLayout &DL) const override {
322     return MVT::i32;
323   }
324 
325   AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override;
326 
327   bool SelectFlatOffset(bool IsSigned, SelectionDAG &DAG, SDNode *N,
328                         SDValue Addr, SDValue &VAddr, SDValue &Offset,
329                         SDValue &SLC) const;
330 };
331 
332 namespace AMDGPUISD {
333 
334 enum NodeType : unsigned {
335   // AMDIL ISD Opcodes
336   FIRST_NUMBER = ISD::BUILTIN_OP_END,
337   UMUL,        // 32bit unsigned multiplication
338   BRANCH_COND,
339   // End AMDIL ISD Opcodes
340 
341   // Function call.
342   CALL,
343   TC_RETURN,
344   TRAP,
345 
346   // Masked control flow nodes.
347   IF,
348   ELSE,
349   LOOP,
350 
351   // A uniform kernel return that terminates the wavefront.
352   ENDPGM,
353 
354   // Return to a shader part's epilog code.
355   RETURN_TO_EPILOG,
356 
357   // Return with values from a non-entry function.
358   RET_FLAG,
359 
360   DWORDADDR,
361   FRACT,
362 
363   /// CLAMP value between 0.0 and 1.0. NaN clamped to 0, following clamp output
364   /// modifier behavior with dx10_enable.
365   CLAMP,
366 
367   // This is SETCC with the full mask result which is used for a compare with a
368   // result bit per item in the wavefront.
369   SETCC,
370   SETREG,
371   // FP ops with input and output chain.
372   FMA_W_CHAIN,
373   FMUL_W_CHAIN,
374 
375   // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
376   // Denormals handled on some parts.
377   COS_HW,
378   SIN_HW,
379   FMAX_LEGACY,
380   FMIN_LEGACY,
381 
382   FMAX3,
383   SMAX3,
384   UMAX3,
385   FMIN3,
386   SMIN3,
387   UMIN3,
388   FMED3,
389   SMED3,
390   UMED3,
391   FDOT2,
392   URECIP,
393   DIV_SCALE,
394   DIV_FMAS,
395   DIV_FIXUP,
396   // For emitting ISD::FMAD when f32 denormals are enabled because mac/mad is
397   // treated as an illegal operation.
398   FMAD_FTZ,
399   TRIG_PREOP, // 1 ULP max error for f64
400 
401   // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
402   //            For f64, max error 2^29 ULP, handles denormals.
403   RCP,
404   RSQ,
405   RCP_LEGACY,
406   RSQ_LEGACY,
407   RCP_IFLAG,
408   FMUL_LEGACY,
409   RSQ_CLAMP,
410   LDEXP,
411   FP_CLASS,
412   DOT4,
413   CARRY,
414   BORROW,
415   BFE_U32, // Extract range of bits with zero extension to 32-bits.
416   BFE_I32, // Extract range of bits with sign extension to 32-bits.
417   BFI, // (src0 & src1) | (~src0 & src2)
418   BFM, // Insert a range of bits into a 32-bit word.
419   FFBH_U32, // ctlz with -1 if input is zero.
420   FFBH_I32,
421   FFBL_B32, // cttz with -1 if input is zero.
422   MUL_U24,
423   MUL_I24,
424   MULHI_U24,
425   MULHI_I24,
426   MAD_U24,
427   MAD_I24,
428   MAD_U64_U32,
429   MAD_I64_I32,
430   MUL_LOHI_I24,
431   MUL_LOHI_U24,
432   PERM,
433   TEXTURE_FETCH,
434   EXPORT, // exp on SI+
435   EXPORT_DONE, // exp on SI+ with done bit set
436   R600_EXPORT,
437   CONST_ADDRESS,
438   REGISTER_LOAD,
439   REGISTER_STORE,
440   SAMPLE,
441   SAMPLEB,
442   SAMPLED,
443   SAMPLEL,
444 
445   // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
446   CVT_F32_UBYTE0,
447   CVT_F32_UBYTE1,
448   CVT_F32_UBYTE2,
449   CVT_F32_UBYTE3,
450 
451   // Convert two float 32 numbers into a single register holding two packed f16
452   // with round to zero.
453   CVT_PKRTZ_F16_F32,
454   CVT_PKNORM_I16_F32,
455   CVT_PKNORM_U16_F32,
456   CVT_PK_I16_I32,
457   CVT_PK_U16_U32,
458 
459   // Same as the standard node, except the high bits of the resulting integer
460   // are known 0.
461   FP_TO_FP16,
462 
463   // Wrapper around fp16 results that are known to zero the high bits.
464   FP16_ZEXT,
465 
466   /// This node is for VLIW targets and it is used to represent a vector
467   /// that is stored in consecutive registers with the same channel.
468   /// For example:
469   ///   |X  |Y|Z|W|
470   /// T0|v.x| | | |
471   /// T1|v.y| | | |
472   /// T2|v.z| | | |
473   /// T3|v.w| | | |
474   BUILD_VERTICAL_VECTOR,
475   /// Pointer to the start of the shader's constant data.
476   CONST_DATA_PTR,
477   INIT_EXEC,
478   INIT_EXEC_FROM_INPUT,
479   SENDMSG,
480   SENDMSGHALT,
481   INTERP_MOV,
482   INTERP_P1,
483   INTERP_P2,
484   INTERP_P1LL_F16,
485   INTERP_P1LV_F16,
486   INTERP_P2_F16,
487   PC_ADD_REL_OFFSET,
488   KILL,
489   DUMMY_CHAIN,
490   FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
491   LOAD_D16_HI,
492   LOAD_D16_LO,
493   LOAD_D16_HI_I8,
494   LOAD_D16_HI_U8,
495   LOAD_D16_LO_I8,
496   LOAD_D16_LO_U8,
497 
498   STORE_MSKOR,
499   LOAD_CONSTANT,
500   TBUFFER_STORE_FORMAT,
501   TBUFFER_STORE_FORMAT_D16,
502   TBUFFER_LOAD_FORMAT,
503   TBUFFER_LOAD_FORMAT_D16,
504   DS_ORDERED_COUNT,
505   ATOMIC_CMP_SWAP,
506   ATOMIC_INC,
507   ATOMIC_DEC,
508   ATOMIC_LOAD_FMIN,
509   ATOMIC_LOAD_FMAX,
510   BUFFER_LOAD,
511   BUFFER_LOAD_UBYTE,
512   BUFFER_LOAD_USHORT,
513   BUFFER_LOAD_BYTE,
514   BUFFER_LOAD_SHORT,
515   BUFFER_LOAD_FORMAT,
516   BUFFER_LOAD_FORMAT_D16,
517   SBUFFER_LOAD,
518   BUFFER_STORE,
519   BUFFER_STORE_BYTE,
520   BUFFER_STORE_SHORT,
521   BUFFER_STORE_FORMAT,
522   BUFFER_STORE_FORMAT_D16,
523   BUFFER_ATOMIC_SWAP,
524   BUFFER_ATOMIC_ADD,
525   BUFFER_ATOMIC_SUB,
526   BUFFER_ATOMIC_SMIN,
527   BUFFER_ATOMIC_UMIN,
528   BUFFER_ATOMIC_SMAX,
529   BUFFER_ATOMIC_UMAX,
530   BUFFER_ATOMIC_AND,
531   BUFFER_ATOMIC_OR,
532   BUFFER_ATOMIC_XOR,
533   BUFFER_ATOMIC_CMPSWAP,
534 
535   LAST_AMDGPU_ISD_NUMBER
536 };
537 
538 
539 } // End namespace AMDGPUISD
540 
541 } // End namespace llvm
542 
543 #endif
544