1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Interface definition of the TargetLowering class that is common
12 /// to all AMD GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
17 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
18 
19 #include "llvm/Target/TargetLowering.h"
20 
21 namespace llvm {
22 
23 class AMDGPUMachineFunction;
24 class AMDGPUSubtarget;
25 class MachineRegisterInfo;
26 
27 class AMDGPUTargetLowering : public TargetLowering {
28 private:
29   /// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been
30   /// legalized from a smaller type VT. Need to match pre-legalized type because
31   /// the generic legalization inserts the add/sub between the select and
32   /// compare.
33   SDValue getFFBH_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL) const;
34 
35 protected:
36   const AMDGPUSubtarget *Subtarget;
37 
38   SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
39   SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
40   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
41   /// \brief Split a vector store into multiple scalar stores.
42   /// \returns The resulting chain.
43 
44   SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
45   SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
46   SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
47   SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
48   SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
49 
50   SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const;
51   SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
52   SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
53   SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
54 
55   SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
56 
57   SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
58   SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
59   SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
60   SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
61 
62   SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
63   SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
64   SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
65   SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
66 
67   SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
68 
69 protected:
70   bool shouldCombineMemoryType(EVT VT) const;
71   SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
72   SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
73 
74   SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL,
75                                        unsigned Opc, SDValue LHS,
76                                        uint32_t ValLo, uint32_t ValHi) const;
77   SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
78   SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
79   SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
80   SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
81   SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
82   SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const;
83   SDValue performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) const;
84   SDValue performCtlzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
85                              SDValue RHS, DAGCombinerInfo &DCI) const;
86   SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
87   SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
88 
89   static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
90 
91   virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
92                                      SelectionDAG &DAG) const;
93 
94   /// Return 64-bit value Op as two 32-bit integers.
95   std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
96                                               SelectionDAG &DAG) const;
97   SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
98   SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
99 
100   /// \brief Split a vector load into 2 loads of half the vector.
101   SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
102 
103   /// \brief Split a vector store into 2 stores of half the vector.
104   SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
105 
106   SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
107   SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
108   SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
109   SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
110   void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
111                                     SmallVectorImpl<SDValue> &Results) const;
112   void analyzeFormalArgumentsCompute(CCState &State,
113                               const SmallVectorImpl<ISD::InputArg> &Ins) const;
114   void AnalyzeFormalArguments(CCState &State,
115                               const SmallVectorImpl<ISD::InputArg> &Ins) const;
116   void AnalyzeReturn(CCState &State,
117                      const SmallVectorImpl<ISD::OutputArg> &Outs) const;
118 
119 public:
120   AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
121 
122   bool isFAbsFree(EVT VT) const override;
123   bool isFNegFree(EVT VT) const override;
124   bool isTruncateFree(EVT Src, EVT Dest) const override;
125   bool isTruncateFree(Type *Src, Type *Dest) const override;
126 
127   bool isZExtFree(Type *Src, Type *Dest) const override;
128   bool isZExtFree(EVT Src, EVT Dest) const override;
129   bool isZExtFree(SDValue Val, EVT VT2) const override;
130 
131   bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
132 
133   MVT getVectorIdxTy(const DataLayout &) const override;
134   bool isSelectSupported(SelectSupportKind) const override;
135 
136   bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
137   bool ShouldShrinkFPConstant(EVT VT) const override;
138   bool shouldReduceLoadWidth(SDNode *Load,
139                              ISD::LoadExtType ExtType,
140                              EVT ExtVT) const override;
141 
142   bool isLoadBitCastBeneficial(EVT, EVT) const final;
143 
144   bool storeOfVectorConstantIsCheap(EVT MemVT,
145                                     unsigned NumElem,
146                                     unsigned AS) const override;
147   bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
148   bool isCheapToSpeculateCttz() const override;
149   bool isCheapToSpeculateCtlz() const override;
150 
151   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
152                       const SmallVectorImpl<ISD::OutputArg> &Outs,
153                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
154                       SelectionDAG &DAG) const override;
155   SDValue LowerCall(CallLoweringInfo &CLI,
156                     SmallVectorImpl<SDValue> &InVals) const override;
157 
158   SDValue LowerDYNAMIC_STACKALLOC(SDValue Op,
159                                   SelectionDAG &DAG) const;
160 
161   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
162   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
163   void ReplaceNodeResults(SDNode * N,
164                           SmallVectorImpl<SDValue> &Results,
165                           SelectionDAG &DAG) const override;
166 
167   SDValue CombineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
168                                SDValue RHS, SDValue True, SDValue False,
169                                SDValue CC, DAGCombinerInfo &DCI) const;
170 
171   const char* getTargetNodeName(unsigned Opcode) const override;
172 
173   bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
174     return true;
175   }
176   SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
177                            int &RefinementSteps, bool &UseOneConstNR,
178                            bool Reciprocal) const override;
179   SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
180                            int &RefinementSteps) const override;
181 
182   virtual SDNode *PostISelFolding(MachineSDNode *N,
183                                   SelectionDAG &DAG) const = 0;
184 
185   /// \brief Determine which of the bits specified in \p Mask are known to be
186   /// either zero or one and return them in the \p KnownZero and \p KnownOne
187   /// bitsets.
188   void computeKnownBitsForTargetNode(const SDValue Op,
189                                      APInt &KnownZero,
190                                      APInt &KnownOne,
191                                      const SelectionDAG &DAG,
192                                      unsigned Depth = 0) const override;
193 
194   unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG,
195                                            unsigned Depth = 0) const override;
196 
197   /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
198   /// MachineFunction.
199   ///
200   /// \returns a RegisterSDNode representing Reg.
201   virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
202                                        const TargetRegisterClass *RC,
203                                        unsigned Reg, EVT VT) const;
204 
205   enum ImplicitParameter {
206     FIRST_IMPLICIT,
207     GRID_DIM = FIRST_IMPLICIT,
208     GRID_OFFSET,
209   };
210 
211   /// \brief Helper function that returns the byte offset of the given
212   /// type of implicit parameter.
213   uint32_t getImplicitParameterOffset(const AMDGPUMachineFunction *MFI,
214                                       const ImplicitParameter Param) const;
215 };
216 
217 namespace AMDGPUISD {
218 
219 enum NodeType : unsigned {
220   // AMDIL ISD Opcodes
221   FIRST_NUMBER = ISD::BUILTIN_OP_END,
222   CALL,        // Function call based on a single integer
223   UMUL,        // 32bit unsigned multiplication
224   BRANCH_COND,
225   // End AMDIL ISD Opcodes
226   ENDPGM,
227   RETURN,
228   DWORDADDR,
229   FRACT,
230   CLAMP,
231   // This is SETCC with the full mask result which is used for a compare with a
232   // result bit per item in the wavefront.
233   SETCC,
234   SETREG,
235   // FP ops with input and output chain.
236   FMA_W_CHAIN,
237   FMUL_W_CHAIN,
238 
239   // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
240   // Denormals handled on some parts.
241   COS_HW,
242   SIN_HW,
243   FMAX_LEGACY,
244   FMIN_LEGACY,
245   FMAX3,
246   SMAX3,
247   UMAX3,
248   FMIN3,
249   SMIN3,
250   UMIN3,
251   FMED3,
252   SMED3,
253   UMED3,
254   URECIP,
255   DIV_SCALE,
256   DIV_FMAS,
257   DIV_FIXUP,
258   TRIG_PREOP, // 1 ULP max error for f64
259 
260   // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
261   //            For f64, max error 2^29 ULP, handles denormals.
262   RCP,
263   RSQ,
264   RCP_LEGACY,
265   RSQ_LEGACY,
266   FMUL_LEGACY,
267   RSQ_CLAMP,
268   LDEXP,
269   FP_CLASS,
270   DOT4,
271   CARRY,
272   BORROW,
273   BFE_U32, // Extract range of bits with zero extension to 32-bits.
274   BFE_I32, // Extract range of bits with sign extension to 32-bits.
275   BFI, // (src0 & src1) | (~src0 & src2)
276   BFM, // Insert a range of bits into a 32-bit word.
277   FFBH_U32, // ctlz with -1 if input is zero.
278   FFBH_I32,
279   MUL_U24,
280   MUL_I24,
281   MULHI_U24,
282   MULHI_I24,
283   MAD_U24,
284   MAD_I24,
285   MUL_LOHI_I24,
286   MUL_LOHI_U24,
287   TEXTURE_FETCH,
288   EXPORT, // exp on SI+
289   EXPORT_DONE, // exp on SI+ with done bit set
290   R600_EXPORT,
291   CONST_ADDRESS,
292   REGISTER_LOAD,
293   REGISTER_STORE,
294   LOAD_INPUT,
295   SAMPLE,
296   SAMPLEB,
297   SAMPLED,
298   SAMPLEL,
299 
300   // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
301   CVT_F32_UBYTE0,
302   CVT_F32_UBYTE1,
303   CVT_F32_UBYTE2,
304   CVT_F32_UBYTE3,
305   /// This node is for VLIW targets and it is used to represent a vector
306   /// that is stored in consecutive registers with the same channel.
307   /// For example:
308   ///   |X  |Y|Z|W|
309   /// T0|v.x| | | |
310   /// T1|v.y| | | |
311   /// T2|v.z| | | |
312   /// T3|v.w| | | |
313   BUILD_VERTICAL_VECTOR,
314   /// Pointer to the start of the shader's constant data.
315   CONST_DATA_PTR,
316   SENDMSG,
317   SENDMSGHALT,
318   INTERP_MOV,
319   INTERP_P1,
320   INTERP_P2,
321   PC_ADD_REL_OFFSET,
322   KILL,
323   FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
324   STORE_MSKOR,
325   LOAD_CONSTANT,
326   TBUFFER_STORE_FORMAT,
327   ATOMIC_CMP_SWAP,
328   ATOMIC_INC,
329   ATOMIC_DEC,
330   BUFFER_LOAD,
331   BUFFER_LOAD_FORMAT,
332   LAST_AMDGPU_ISD_NUMBER
333 };
334 
335 
336 } // End namespace AMDGPUISD
337 
338 } // End namespace llvm
339 
340 #endif
341