1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief This is the parent TargetLowering class for hardware code gen
12 /// targets.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUISelLowering.h"
17 #include "AMDGPU.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUIntrinsicInfo.h"
20 #include "AMDGPURegisterInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DiagnosticInfo.h"
31 #include "SIInstrInfo.h"
32 using namespace llvm;
33 
34 static bool allocateKernArg(unsigned ValNo, MVT ValVT, MVT LocVT,
35                             CCValAssign::LocInfo LocInfo,
36                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
37   MachineFunction &MF = State.getMachineFunction();
38   AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
39 
40   uint64_t Offset = MFI->allocateKernArg(ValVT.getStoreSize(),
41                                          ArgFlags.getOrigAlign());
42   State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, Offset, LocVT, LocInfo));
43   return true;
44 }
45 
46 #include "AMDGPUGenCallingConv.inc"
47 
48 // Find a larger type to do a load / store of a vector with.
49 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
50   unsigned StoreSize = VT.getStoreSizeInBits();
51   if (StoreSize <= 32)
52     return EVT::getIntegerVT(Ctx, StoreSize);
53 
54   assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
55   return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
56 }
57 
58 // Type for a vector that will be loaded to.
59 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
60   unsigned StoreSize = VT.getStoreSizeInBits();
61   if (StoreSize <= 32)
62     return EVT::getIntegerVT(Ctx, 32);
63 
64   return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
65 }
66 
67 AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
68                                            const AMDGPUSubtarget &STI)
69     : TargetLowering(TM), Subtarget(&STI) {
70   // Lower floating point store/load to integer store/load to reduce the number
71   // of patterns in tablegen.
72   setOperationAction(ISD::LOAD, MVT::f32, Promote);
73   AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
74 
75   setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
76   AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
77 
78   setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
79   AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
80 
81   setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
82   AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
83 
84   setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
85   AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
86 
87   setOperationAction(ISD::LOAD, MVT::i64, Promote);
88   AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
89 
90   setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
91   AddPromotedToType(ISD::LOAD, MVT::v2i64, MVT::v4i32);
92 
93   setOperationAction(ISD::LOAD, MVT::f64, Promote);
94   AddPromotedToType(ISD::LOAD, MVT::f64, MVT::v2i32);
95 
96   setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
97   AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v4i32);
98 
99   // There are no 64-bit extloads. These should be done as a 32-bit extload and
100   // an extension to 64-bit.
101   for (MVT VT : MVT::integer_valuetypes()) {
102     setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand);
103     setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand);
104     setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand);
105   }
106 
107   for (MVT VT : MVT::integer_valuetypes()) {
108     if (VT == MVT::i64)
109       continue;
110 
111     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
112     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Legal);
113     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Legal);
114     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
115 
116     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
117     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal);
118     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal);
119     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
120 
121     setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
122     setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Legal);
123     setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Legal);
124     setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
125   }
126 
127   for (MVT VT : MVT::integer_vector_valuetypes()) {
128     setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand);
129     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand);
130     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand);
131     setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand);
132     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand);
133     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand);
134     setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand);
135     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand);
136     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand);
137     setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand);
138     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand);
139     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand);
140   }
141 
142   setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
143   setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
144   setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
145   setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, MVT::v8f16, Expand);
146 
147   setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
148   setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand);
149   setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand);
150   setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f32, Expand);
151 
152   setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
153   setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
154   setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
155   setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f16, Expand);
156 
157   setOperationAction(ISD::STORE, MVT::f32, Promote);
158   AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
159 
160   setOperationAction(ISD::STORE, MVT::v2f32, Promote);
161   AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
162 
163   setOperationAction(ISD::STORE, MVT::v4f32, Promote);
164   AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
165 
166   setOperationAction(ISD::STORE, MVT::v8f32, Promote);
167   AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
168 
169   setOperationAction(ISD::STORE, MVT::v16f32, Promote);
170   AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
171 
172   setOperationAction(ISD::STORE, MVT::i64, Promote);
173   AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
174 
175   setOperationAction(ISD::STORE, MVT::v2i64, Promote);
176   AddPromotedToType(ISD::STORE, MVT::v2i64, MVT::v4i32);
177 
178   setOperationAction(ISD::STORE, MVT::f64, Promote);
179   AddPromotedToType(ISD::STORE, MVT::f64, MVT::v2i32);
180 
181   setOperationAction(ISD::STORE, MVT::v2f64, Promote);
182   AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v4i32);
183 
184   setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
185   setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
186 
187   setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
188   setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
189 
190   setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
191   setTruncStoreAction(MVT::v16i32, MVT::v16i8, Expand);
192   setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
193 
194   setTruncStoreAction(MVT::i64, MVT::i1, Expand);
195   setTruncStoreAction(MVT::i64, MVT::i8, Expand);
196   setTruncStoreAction(MVT::i64, MVT::i16, Expand);
197   setTruncStoreAction(MVT::i64, MVT::i32, Expand);
198 
199   setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
200   setTruncStoreAction(MVT::v2i64, MVT::v2i8, Expand);
201   setTruncStoreAction(MVT::v2i64, MVT::v2i16, Expand);
202   setTruncStoreAction(MVT::v2i64, MVT::v2i32, Expand);
203 
204   setTruncStoreAction(MVT::f32, MVT::f16, Expand);
205   setTruncStoreAction(MVT::v2f32, MVT::v2f16, Expand);
206   setTruncStoreAction(MVT::v4f32, MVT::v4f16, Expand);
207   setTruncStoreAction(MVT::v8f32, MVT::v8f16, Expand);
208 
209   setTruncStoreAction(MVT::f64, MVT::f16, Expand);
210   setTruncStoreAction(MVT::f64, MVT::f32, Expand);
211 
212   setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
213   setTruncStoreAction(MVT::v2f64, MVT::v2f16, Expand);
214 
215   setTruncStoreAction(MVT::v4f64, MVT::v4f32, Expand);
216   setTruncStoreAction(MVT::v4f64, MVT::v4f16, Expand);
217 
218   setTruncStoreAction(MVT::v8f64, MVT::v8f32, Expand);
219   setTruncStoreAction(MVT::v8f64, MVT::v8f16, Expand);
220 
221 
222   setOperationAction(ISD::Constant, MVT::i32, Legal);
223   setOperationAction(ISD::Constant, MVT::i64, Legal);
224   setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
225   setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
226 
227   setOperationAction(ISD::BR_JT, MVT::Other, Expand);
228   setOperationAction(ISD::BRIND, MVT::Other, Expand);
229 
230   // This is totally unsupported, just custom lower to produce an error.
231   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
232 
233   // We need to custom lower some of the intrinsics
234   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
235   setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
236 
237   // Library functions.  These default to Expand, but we have instructions
238   // for them.
239   setOperationAction(ISD::FCEIL,  MVT::f32, Legal);
240   setOperationAction(ISD::FEXP2,  MVT::f32, Legal);
241   setOperationAction(ISD::FPOW,   MVT::f32, Legal);
242   setOperationAction(ISD::FLOG2,  MVT::f32, Legal);
243   setOperationAction(ISD::FABS,   MVT::f32, Legal);
244   setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
245   setOperationAction(ISD::FRINT,  MVT::f32, Legal);
246   setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
247   setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
248   setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
249 
250   setOperationAction(ISD::FROUND, MVT::f32, Custom);
251   setOperationAction(ISD::FROUND, MVT::f64, Custom);
252 
253   setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
254   setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
255 
256   setOperationAction(ISD::FREM, MVT::f32, Custom);
257   setOperationAction(ISD::FREM, MVT::f64, Custom);
258 
259   // v_mad_f32 does not support denormals according to some sources.
260   if (!Subtarget->hasFP32Denormals())
261     setOperationAction(ISD::FMAD, MVT::f32, Legal);
262 
263   // Expand to fneg + fadd.
264   setOperationAction(ISD::FSUB, MVT::f64, Expand);
265 
266   setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
267   setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
268   setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
269   setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
270   setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
271   setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
272   setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
273   setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
274   setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
275   setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
276 
277   if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
278     setOperationAction(ISD::FCEIL, MVT::f64, Custom);
279     setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
280     setOperationAction(ISD::FRINT, MVT::f64, Custom);
281     setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
282   }
283 
284   if (!Subtarget->hasBFI()) {
285     // fcopysign can be done in a single instruction with BFI.
286     setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
287     setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
288   }
289 
290   setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
291 
292   const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
293   for (MVT VT : ScalarIntVTs) {
294     // These should use [SU]DIVREM, so set them to expand
295     setOperationAction(ISD::SDIV, VT, Expand);
296     setOperationAction(ISD::UDIV, VT, Expand);
297     setOperationAction(ISD::SREM, VT, Expand);
298     setOperationAction(ISD::UREM, VT, Expand);
299 
300     // GPU does not have divrem function for signed or unsigned.
301     setOperationAction(ISD::SDIVREM, VT, Custom);
302     setOperationAction(ISD::UDIVREM, VT, Custom);
303 
304     // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
305     setOperationAction(ISD::SMUL_LOHI, VT, Expand);
306     setOperationAction(ISD::UMUL_LOHI, VT, Expand);
307 
308     setOperationAction(ISD::BSWAP, VT, Expand);
309     setOperationAction(ISD::CTTZ, VT, Expand);
310     setOperationAction(ISD::CTLZ, VT, Expand);
311   }
312 
313   if (!Subtarget->hasBCNT(32))
314     setOperationAction(ISD::CTPOP, MVT::i32, Expand);
315 
316   if (!Subtarget->hasBCNT(64))
317     setOperationAction(ISD::CTPOP, MVT::i64, Expand);
318 
319   // The hardware supports 32-bit ROTR, but not ROTL.
320   setOperationAction(ISD::ROTL, MVT::i32, Expand);
321   setOperationAction(ISD::ROTL, MVT::i64, Expand);
322   setOperationAction(ISD::ROTR, MVT::i64, Expand);
323 
324   setOperationAction(ISD::MUL, MVT::i64, Expand);
325   setOperationAction(ISD::MULHU, MVT::i64, Expand);
326   setOperationAction(ISD::MULHS, MVT::i64, Expand);
327   setOperationAction(ISD::UDIV, MVT::i32, Expand);
328   setOperationAction(ISD::UREM, MVT::i32, Expand);
329   setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
330   setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
331   setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
332   setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
333   setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
334 
335   setOperationAction(ISD::SMIN, MVT::i32, Legal);
336   setOperationAction(ISD::UMIN, MVT::i32, Legal);
337   setOperationAction(ISD::SMAX, MVT::i32, Legal);
338   setOperationAction(ISD::UMAX, MVT::i32, Legal);
339 
340   if (Subtarget->hasFFBH())
341     setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Custom);
342 
343   if (Subtarget->hasFFBL())
344     setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Legal);
345 
346   setOperationAction(ISD::CTLZ, MVT::i64, Custom);
347   setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
348 
349   // We only really have 32-bit BFE instructions (and 16-bit on VI).
350   //
351   // On SI+ there are 64-bit BFEs, but they are scalar only and there isn't any
352   // effort to match them now. We want this to be false for i64 cases when the
353   // extraction isn't restricted to the upper or lower half. Ideally we would
354   // have some pass reduce 64-bit extracts to 32-bit if possible. Extracts that
355   // span the midpoint are probably relatively rare, so don't worry about them
356   // for now.
357   if (Subtarget->hasBFE())
358     setHasExtractBitsInsn(true);
359 
360   static const MVT::SimpleValueType VectorIntTypes[] = {
361     MVT::v2i32, MVT::v4i32
362   };
363 
364   for (MVT VT : VectorIntTypes) {
365     // Expand the following operations for the current type by default.
366     setOperationAction(ISD::ADD,  VT, Expand);
367     setOperationAction(ISD::AND,  VT, Expand);
368     setOperationAction(ISD::FP_TO_SINT, VT, Expand);
369     setOperationAction(ISD::FP_TO_UINT, VT, Expand);
370     setOperationAction(ISD::MUL,  VT, Expand);
371     setOperationAction(ISD::OR,   VT, Expand);
372     setOperationAction(ISD::SHL,  VT, Expand);
373     setOperationAction(ISD::SRA,  VT, Expand);
374     setOperationAction(ISD::SRL,  VT, Expand);
375     setOperationAction(ISD::ROTL, VT, Expand);
376     setOperationAction(ISD::ROTR, VT, Expand);
377     setOperationAction(ISD::SUB,  VT, Expand);
378     setOperationAction(ISD::SINT_TO_FP, VT, Expand);
379     setOperationAction(ISD::UINT_TO_FP, VT, Expand);
380     setOperationAction(ISD::SDIV, VT, Expand);
381     setOperationAction(ISD::UDIV, VT, Expand);
382     setOperationAction(ISD::SREM, VT, Expand);
383     setOperationAction(ISD::UREM, VT, Expand);
384     setOperationAction(ISD::SMUL_LOHI, VT, Expand);
385     setOperationAction(ISD::UMUL_LOHI, VT, Expand);
386     setOperationAction(ISD::SDIVREM, VT, Custom);
387     setOperationAction(ISD::UDIVREM, VT, Expand);
388     setOperationAction(ISD::ADDC, VT, Expand);
389     setOperationAction(ISD::SUBC, VT, Expand);
390     setOperationAction(ISD::ADDE, VT, Expand);
391     setOperationAction(ISD::SUBE, VT, Expand);
392     setOperationAction(ISD::SELECT, VT, Expand);
393     setOperationAction(ISD::VSELECT, VT, Expand);
394     setOperationAction(ISD::SELECT_CC, VT, Expand);
395     setOperationAction(ISD::XOR,  VT, Expand);
396     setOperationAction(ISD::BSWAP, VT, Expand);
397     setOperationAction(ISD::CTPOP, VT, Expand);
398     setOperationAction(ISD::CTTZ, VT, Expand);
399     setOperationAction(ISD::CTLZ, VT, Expand);
400     setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
401   }
402 
403   static const MVT::SimpleValueType FloatVectorTypes[] = {
404     MVT::v2f32, MVT::v4f32
405   };
406 
407   for (MVT VT : FloatVectorTypes) {
408     setOperationAction(ISD::FABS, VT, Expand);
409     setOperationAction(ISD::FMINNUM, VT, Expand);
410     setOperationAction(ISD::FMAXNUM, VT, Expand);
411     setOperationAction(ISD::FADD, VT, Expand);
412     setOperationAction(ISD::FCEIL, VT, Expand);
413     setOperationAction(ISD::FCOS, VT, Expand);
414     setOperationAction(ISD::FDIV, VT, Expand);
415     setOperationAction(ISD::FEXP2, VT, Expand);
416     setOperationAction(ISD::FLOG2, VT, Expand);
417     setOperationAction(ISD::FREM, VT, Expand);
418     setOperationAction(ISD::FPOW, VT, Expand);
419     setOperationAction(ISD::FFLOOR, VT, Expand);
420     setOperationAction(ISD::FTRUNC, VT, Expand);
421     setOperationAction(ISD::FMUL, VT, Expand);
422     setOperationAction(ISD::FMA, VT, Expand);
423     setOperationAction(ISD::FRINT, VT, Expand);
424     setOperationAction(ISD::FNEARBYINT, VT, Expand);
425     setOperationAction(ISD::FSQRT, VT, Expand);
426     setOperationAction(ISD::FSIN, VT, Expand);
427     setOperationAction(ISD::FSUB, VT, Expand);
428     setOperationAction(ISD::FNEG, VT, Expand);
429     setOperationAction(ISD::VSELECT, VT, Expand);
430     setOperationAction(ISD::SELECT_CC, VT, Expand);
431     setOperationAction(ISD::FCOPYSIGN, VT, Expand);
432     setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
433   }
434 
435   // This causes using an unrolled select operation rather than expansion with
436   // bit operations. This is in general better, but the alternative using BFI
437   // instructions may be better if the select sources are SGPRs.
438   setOperationAction(ISD::SELECT, MVT::v2f32, Promote);
439   AddPromotedToType(ISD::SELECT, MVT::v2f32, MVT::v2i32);
440 
441   setOperationAction(ISD::SELECT, MVT::v4f32, Promote);
442   AddPromotedToType(ISD::SELECT, MVT::v4f32, MVT::v4i32);
443 
444   setBooleanContents(ZeroOrNegativeOneBooleanContent);
445   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
446 
447   setSchedulingPreference(Sched::RegPressure);
448   setJumpIsExpensive(true);
449 
450   // SI at least has hardware support for floating point exceptions, but no way
451   // of using or handling them is implemented. They are also optional in OpenCL
452   // (Section 7.3)
453   setHasFloatingPointExceptions(Subtarget->hasFPExceptions());
454 
455   setSelectIsExpensive(false);
456   PredictableSelectIsExpensive = false;
457 
458   setFsqrtIsCheap(true);
459 
460   // We want to find all load dependencies for long chains of stores to enable
461   // merging into very wide vectors. The problem is with vectors with > 4
462   // elements. MergeConsecutiveStores will attempt to merge these because x8/x16
463   // vectors are a legal type, even though we have to split the loads
464   // usually. When we can more precisely specify load legality per address
465   // space, we should be able to make FindBetterChain/MergeConsecutiveStores
466   // smarter so that they can figure out what to do in 2 iterations without all
467   // N > 4 stores on the same chain.
468   GatherAllAliasesMaxDepth = 16;
469 
470   // FIXME: Need to really handle these.
471   MaxStoresPerMemcpy  = 4096;
472   MaxStoresPerMemmove = 4096;
473   MaxStoresPerMemset  = 4096;
474 
475   setTargetDAGCombine(ISD::BITCAST);
476   setTargetDAGCombine(ISD::AND);
477   setTargetDAGCombine(ISD::SHL);
478   setTargetDAGCombine(ISD::SRA);
479   setTargetDAGCombine(ISD::SRL);
480   setTargetDAGCombine(ISD::MUL);
481   setTargetDAGCombine(ISD::SELECT);
482   setTargetDAGCombine(ISD::SELECT_CC);
483   setTargetDAGCombine(ISD::STORE);
484   setTargetDAGCombine(ISD::FADD);
485   setTargetDAGCombine(ISD::FSUB);
486 }
487 
488 //===----------------------------------------------------------------------===//
489 // Target Information
490 //===----------------------------------------------------------------------===//
491 
492 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {
493   return MVT::i32;
494 }
495 
496 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
497   return true;
498 }
499 
500 // The backend supports 32 and 64 bit floating point immediates.
501 // FIXME: Why are we reporting vectors of FP immediates as legal?
502 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
503   EVT ScalarVT = VT.getScalarType();
504   return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
505 }
506 
507 // We don't want to shrink f64 / f32 constants.
508 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
509   EVT ScalarVT = VT.getScalarType();
510   return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
511 }
512 
513 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
514                                                  ISD::LoadExtType,
515                                                  EVT NewVT) const {
516 
517   unsigned NewSize = NewVT.getStoreSizeInBits();
518 
519   // If we are reducing to a 32-bit load, this is always better.
520   if (NewSize == 32)
521     return true;
522 
523   EVT OldVT = N->getValueType(0);
524   unsigned OldSize = OldVT.getStoreSizeInBits();
525 
526   // Don't produce extloads from sub 32-bit types. SI doesn't have scalar
527   // extloads, so doing one requires using a buffer_load. In cases where we
528   // still couldn't use a scalar load, using the wider load shouldn't really
529   // hurt anything.
530 
531   // If the old size already had to be an extload, there's no harm in continuing
532   // to reduce the width.
533   return (OldSize < 32);
534 }
535 
536 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
537                                                    EVT CastTy) const {
538   if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
539     return true;
540 
541   unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
542   unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
543 
544   return ((LScalarSize <= CastScalarSize) ||
545           (CastScalarSize >= 32) ||
546           (LScalarSize < 32));
547 }
548 
549 // SI+ has instructions for cttz / ctlz for 32-bit values. This is probably also
550 // profitable with the expansion for 64-bit since it's generally good to
551 // speculate things.
552 // FIXME: These should really have the size as a parameter.
553 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {
554   return true;
555 }
556 
557 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {
558   return true;
559 }
560 
561 //===---------------------------------------------------------------------===//
562 // Target Properties
563 //===---------------------------------------------------------------------===//
564 
565 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
566   assert(VT.isFloatingPoint());
567   return VT == MVT::f32 || VT == MVT::f64;
568 }
569 
570 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
571   assert(VT.isFloatingPoint());
572   return VT == MVT::f32 || VT == MVT::f64;
573 }
574 
575 bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(EVT MemVT,
576                                                          unsigned NumElem,
577                                                          unsigned AS) const {
578   return true;
579 }
580 
581 bool AMDGPUTargetLowering::aggressivelyPreferBuildVectorSources(EVT VecVT) const {
582   // There are few operations which truly have vector input operands. Any vector
583   // operation is going to involve operations on each component, and a
584   // build_vector will be a copy per element, so it always makes sense to use a
585   // build_vector input in place of the extracted element to avoid a copy into a
586   // super register.
587   //
588   // We should probably only do this if all users are extracts only, but this
589   // should be the common case.
590   return true;
591 }
592 
593 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
594   // Truncate is just accessing a subregister.
595   return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
596 }
597 
598 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
599   // Truncate is just accessing a subregister.
600   return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
601          (Dest->getPrimitiveSizeInBits() % 32 == 0);
602 }
603 
604 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
605   unsigned SrcSize = Src->getScalarSizeInBits();
606   unsigned DestSize = Dest->getScalarSizeInBits();
607 
608   return SrcSize == 32 && DestSize == 64;
609 }
610 
611 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
612   // Any register load of a 64-bit value really requires 2 32-bit moves. For all
613   // practical purposes, the extra mov 0 to load a 64-bit is free.  As used,
614   // this will enable reducing 64-bit operations the 32-bit, which is always
615   // good.
616   return Src == MVT::i32 && Dest == MVT::i64;
617 }
618 
619 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
620   return isZExtFree(Val.getValueType(), VT2);
621 }
622 
623 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
624   // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
625   // limited number of native 64-bit operations. Shrinking an operation to fit
626   // in a single 32-bit register should always be helpful. As currently used,
627   // this is much less general than the name suggests, and is only used in
628   // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
629   // not profitable, and may actually be harmful.
630   return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
631 }
632 
633 //===---------------------------------------------------------------------===//
634 // TargetLowering Callbacks
635 //===---------------------------------------------------------------------===//
636 
637 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
638                              const SmallVectorImpl<ISD::InputArg> &Ins) const {
639 
640   State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
641 }
642 
643 void AMDGPUTargetLowering::AnalyzeReturn(CCState &State,
644                            const SmallVectorImpl<ISD::OutputArg> &Outs) const {
645 
646   State.AnalyzeReturn(Outs, RetCC_SI);
647 }
648 
649 SDValue
650 AMDGPUTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
651                                   bool isVarArg,
652                                   const SmallVectorImpl<ISD::OutputArg> &Outs,
653                                   const SmallVectorImpl<SDValue> &OutVals,
654                                   const SDLoc &DL, SelectionDAG &DAG) const {
655   return DAG.getNode(AMDGPUISD::ENDPGM, DL, MVT::Other, Chain);
656 }
657 
658 //===---------------------------------------------------------------------===//
659 // Target specific lowering
660 //===---------------------------------------------------------------------===//
661 
662 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
663                                         SmallVectorImpl<SDValue> &InVals) const {
664   SDValue Callee = CLI.Callee;
665   SelectionDAG &DAG = CLI.DAG;
666 
667   const Function &Fn = *DAG.getMachineFunction().getFunction();
668 
669   StringRef FuncName("<unknown>");
670 
671   if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
672     FuncName = G->getSymbol();
673   else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
674     FuncName = G->getGlobal()->getName();
675 
676   DiagnosticInfoUnsupported NoCalls(
677       Fn, "unsupported call to function " + FuncName, CLI.DL.getDebugLoc());
678   DAG.getContext()->diagnose(NoCalls);
679 
680   for (unsigned I = 0, E = CLI.Ins.size(); I != E; ++I)
681     InVals.push_back(DAG.getUNDEF(CLI.Ins[I].VT));
682 
683   return DAG.getEntryNode();
684 }
685 
686 SDValue AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
687                                                       SelectionDAG &DAG) const {
688   const Function &Fn = *DAG.getMachineFunction().getFunction();
689 
690   DiagnosticInfoUnsupported NoDynamicAlloca(Fn, "unsupported dynamic alloca",
691                                             SDLoc(Op).getDebugLoc());
692   DAG.getContext()->diagnose(NoDynamicAlloca);
693   auto Ops = {DAG.getConstant(0, SDLoc(), Op.getValueType()), Op.getOperand(0)};
694   return DAG.getMergeValues(Ops, SDLoc());
695 }
696 
697 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
698                                              SelectionDAG &DAG) const {
699   switch (Op.getOpcode()) {
700   default:
701     Op->dump(&DAG);
702     llvm_unreachable("Custom lowering code for this"
703                      "instruction is not implemented yet!");
704     break;
705   case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
706   case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
707   case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
708   case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
709   case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
710   case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
711   case ISD::FREM: return LowerFREM(Op, DAG);
712   case ISD::FCEIL: return LowerFCEIL(Op, DAG);
713   case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
714   case ISD::FRINT: return LowerFRINT(Op, DAG);
715   case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
716   case ISD::FROUND: return LowerFROUND(Op, DAG);
717   case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
718   case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
719   case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
720   case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
721   case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
722   case ISD::CTLZ:
723   case ISD::CTLZ_ZERO_UNDEF:
724     return LowerCTLZ(Op, DAG);
725   case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
726   }
727   return Op;
728 }
729 
730 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
731                                               SmallVectorImpl<SDValue> &Results,
732                                               SelectionDAG &DAG) const {
733   switch (N->getOpcode()) {
734   case ISD::SIGN_EXTEND_INREG:
735     // Different parts of legalization seem to interpret which type of
736     // sign_extend_inreg is the one to check for custom lowering. The extended
737     // from type is what really matters, but some places check for custom
738     // lowering of the result type. This results in trying to use
739     // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
740     // nothing here and let the illegal result integer be handled normally.
741     return;
742   default:
743     return;
744   }
745 }
746 
747 // FIXME: This implements accesses to initialized globals in the constant
748 // address space by copying them to private and accessing that. It does not
749 // properly handle illegal types or vectors. The private vector loads are not
750 // scalarized, and the illegal scalars hit an assertion. This technique will not
751 // work well with large initializers, and this should eventually be
752 // removed. Initialized globals should be placed into a data section that the
753 // runtime will load into a buffer before the kernel is executed. Uses of the
754 // global need to be replaced with a pointer loaded from an implicit kernel
755 // argument into this buffer holding the copy of the data, which will remove the
756 // need for any of this.
757 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
758                                                        const GlobalValue *GV,
759                                                        const SDValue &InitPtr,
760                                                        SDValue Chain,
761                                                        SelectionDAG &DAG) const {
762   const DataLayout &TD = DAG.getDataLayout();
763   SDLoc DL(InitPtr);
764   Type *InitTy = Init->getType();
765 
766   if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
767     EVT VT = EVT::getEVT(InitTy);
768     PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
769     return DAG.getStore(Chain, DL, DAG.getConstant(*CI, DL, VT), InitPtr,
770                         MachinePointerInfo(UndefValue::get(PtrTy)), false,
771                         false, TD.getPrefTypeAlignment(InitTy));
772   }
773 
774   if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
775     EVT VT = EVT::getEVT(CFP->getType());
776     PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
777     return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, DL, VT), InitPtr,
778                         MachinePointerInfo(UndefValue::get(PtrTy)), false,
779                         false, TD.getPrefTypeAlignment(CFP->getType()));
780   }
781 
782   if (StructType *ST = dyn_cast<StructType>(InitTy)) {
783     const StructLayout *SL = TD.getStructLayout(ST);
784 
785     EVT PtrVT = InitPtr.getValueType();
786     SmallVector<SDValue, 8> Chains;
787 
788     for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
789       SDValue Offset = DAG.getConstant(SL->getElementOffset(I), DL, PtrVT);
790       SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
791 
792       Constant *Elt = Init->getAggregateElement(I);
793       Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
794     }
795 
796     return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
797   }
798 
799   if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
800     EVT PtrVT = InitPtr.getValueType();
801 
802     unsigned NumElements;
803     if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
804       NumElements = AT->getNumElements();
805     else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
806       NumElements = VT->getNumElements();
807     else
808       llvm_unreachable("Unexpected type");
809 
810     unsigned EltSize = TD.getTypeAllocSize(SeqTy->getElementType());
811     SmallVector<SDValue, 8> Chains;
812     for (unsigned i = 0; i < NumElements; ++i) {
813       SDValue Offset = DAG.getConstant(i * EltSize, DL, PtrVT);
814       SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
815 
816       Constant *Elt = Init->getAggregateElement(i);
817       Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
818     }
819 
820     return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
821   }
822 
823   if (isa<UndefValue>(Init)) {
824     EVT VT = EVT::getEVT(InitTy);
825     PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
826     return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
827                         MachinePointerInfo(UndefValue::get(PtrTy)), false,
828                         false, TD.getPrefTypeAlignment(InitTy));
829   }
830 
831   Init->dump();
832   llvm_unreachable("Unhandled constant initializer");
833 }
834 
835 static bool hasDefinedInitializer(const GlobalValue *GV) {
836   const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
837   if (!GVar || !GVar->hasInitializer())
838     return false;
839 
840   return !isa<UndefValue>(GVar->getInitializer());
841 }
842 
843 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
844                                                  SDValue Op,
845                                                  SelectionDAG &DAG) const {
846 
847   const DataLayout &DL = DAG.getDataLayout();
848   GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
849   const GlobalValue *GV = G->getGlobal();
850 
851   switch (G->getAddressSpace()) {
852   case AMDGPUAS::CONSTANT_ADDRESS: {
853     MVT ConstPtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
854     SDValue GA = DAG.getTargetGlobalAddress(GV, SDLoc(G), ConstPtrVT);
855     return DAG.getNode(AMDGPUISD::CONST_DATA_PTR, SDLoc(G), ConstPtrVT, GA);
856   }
857   case AMDGPUAS::LOCAL_ADDRESS: {
858     // XXX: What does the value of G->getOffset() mean?
859     assert(G->getOffset() == 0 &&
860          "Do not know what to do with an non-zero offset");
861 
862     // TODO: We could emit code to handle the initialization somewhere.
863     if (hasDefinedInitializer(GV))
864       break;
865 
866     unsigned Offset;
867     if (MFI->LocalMemoryObjects.count(GV) == 0) {
868       unsigned Align = GV->getAlignment();
869       if (Align == 0)
870         Align = DL.getABITypeAlignment(GV->getValueType());
871 
872       /// TODO: We should sort these to minimize wasted space due to alignment
873       /// padding. Currently the padding is decided by the first encountered use
874       /// during lowering.
875       Offset = MFI->LDSSize = alignTo(MFI->LDSSize, Align);
876       MFI->LocalMemoryObjects[GV] = Offset;
877       MFI->LDSSize += DL.getTypeAllocSize(GV->getValueType());
878     } else {
879       Offset = MFI->LocalMemoryObjects[GV];
880     }
881 
882     return DAG.getConstant(Offset, SDLoc(Op),
883                            getPointerTy(DL, AMDGPUAS::LOCAL_ADDRESS));
884   }
885   }
886 
887   const Function &Fn = *DAG.getMachineFunction().getFunction();
888   DiagnosticInfoUnsupported BadInit(
889       Fn, "unsupported initializer for address space", SDLoc(Op).getDebugLoc());
890   DAG.getContext()->diagnose(BadInit);
891   return SDValue();
892 }
893 
894 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
895                                                   SelectionDAG &DAG) const {
896   SmallVector<SDValue, 8> Args;
897 
898   for (const SDUse &U : Op->ops())
899     DAG.ExtractVectorElements(U.get(), Args);
900 
901   return DAG.getBuildVector(Op.getValueType(), SDLoc(Op), Args);
902 }
903 
904 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
905                                                      SelectionDAG &DAG) const {
906 
907   SmallVector<SDValue, 8> Args;
908   unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
909   EVT VT = Op.getValueType();
910   DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
911                             VT.getVectorNumElements());
912 
913   return DAG.getBuildVector(Op.getValueType(), SDLoc(Op), Args);
914 }
915 
916 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
917     SelectionDAG &DAG) const {
918   unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
919   SDLoc DL(Op);
920   EVT VT = Op.getValueType();
921 
922   switch (IntrinsicID) {
923     default: return Op;
924     case AMDGPUIntrinsic::AMDGPU_clamp:
925     case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
926       return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
927                          Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
928 
929     case Intrinsic::AMDGPU_ldexp: // Legacy name
930       return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1),
931                                                    Op.getOperand(2));
932 
933     case AMDGPUIntrinsic::AMDGPU_bfe_i32:
934       return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
935                          Op.getOperand(1),
936                          Op.getOperand(2),
937                          Op.getOperand(3));
938 
939     case AMDGPUIntrinsic::AMDGPU_bfe_u32:
940       return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
941                          Op.getOperand(1),
942                          Op.getOperand(2),
943                          Op.getOperand(3));
944 
945     case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
946       return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
947 
948     case AMDGPUIntrinsic::AMDGPU_brev: // Legacy name
949       return DAG.getNode(ISD::BITREVERSE, DL, VT, Op.getOperand(1));
950   }
951 }
952 
953 /// \brief Generate Min/Max node
954 SDValue AMDGPUTargetLowering::CombineFMinMaxLegacy(const SDLoc &DL, EVT VT,
955                                                    SDValue LHS, SDValue RHS,
956                                                    SDValue True, SDValue False,
957                                                    SDValue CC,
958                                                    DAGCombinerInfo &DCI) const {
959   if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
960     return SDValue();
961 
962   if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
963     return SDValue();
964 
965   SelectionDAG &DAG = DCI.DAG;
966   ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
967   switch (CCOpcode) {
968   case ISD::SETOEQ:
969   case ISD::SETONE:
970   case ISD::SETUNE:
971   case ISD::SETNE:
972   case ISD::SETUEQ:
973   case ISD::SETEQ:
974   case ISD::SETFALSE:
975   case ISD::SETFALSE2:
976   case ISD::SETTRUE:
977   case ISD::SETTRUE2:
978   case ISD::SETUO:
979   case ISD::SETO:
980     break;
981   case ISD::SETULE:
982   case ISD::SETULT: {
983     if (LHS == True)
984       return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
985     return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
986   }
987   case ISD::SETOLE:
988   case ISD::SETOLT:
989   case ISD::SETLE:
990   case ISD::SETLT: {
991     // Ordered. Assume ordered for undefined.
992 
993     // Only do this after legalization to avoid interfering with other combines
994     // which might occur.
995     if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
996         !DCI.isCalledByLegalizer())
997       return SDValue();
998 
999     // We need to permute the operands to get the correct NaN behavior. The
1000     // selected operand is the second one based on the failing compare with NaN,
1001     // so permute it based on the compare type the hardware uses.
1002     if (LHS == True)
1003       return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1004     return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1005   }
1006   case ISD::SETUGE:
1007   case ISD::SETUGT: {
1008     if (LHS == True)
1009       return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1010     return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1011   }
1012   case ISD::SETGT:
1013   case ISD::SETGE:
1014   case ISD::SETOGE:
1015   case ISD::SETOGT: {
1016     if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1017         !DCI.isCalledByLegalizer())
1018       return SDValue();
1019 
1020     if (LHS == True)
1021       return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1022     return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1023   }
1024   case ISD::SETCC_INVALID:
1025     llvm_unreachable("Invalid setcc condcode!");
1026   }
1027   return SDValue();
1028 }
1029 
1030 std::pair<SDValue, SDValue>
1031 AMDGPUTargetLowering::split64BitValue(SDValue Op, SelectionDAG &DAG) const {
1032   SDLoc SL(Op);
1033 
1034   SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1035 
1036   const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1037   const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1038 
1039   SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
1040   SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
1041 
1042   return std::make_pair(Lo, Hi);
1043 }
1044 
1045 SDValue AMDGPUTargetLowering::getLoHalf64(SDValue Op, SelectionDAG &DAG) const {
1046   SDLoc SL(Op);
1047 
1048   SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1049   const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1050   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
1051 }
1052 
1053 SDValue AMDGPUTargetLowering::getHiHalf64(SDValue Op, SelectionDAG &DAG) const {
1054   SDLoc SL(Op);
1055 
1056   SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1057   const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1058   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
1059 }
1060 
1061 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1062                                               SelectionDAG &DAG) const {
1063   LoadSDNode *Load = cast<LoadSDNode>(Op);
1064   EVT VT = Op.getValueType();
1065 
1066 
1067   // If this is a 2 element vector, we really want to scalarize and not create
1068   // weird 1 element vectors.
1069   if (VT.getVectorNumElements() == 2)
1070     return scalarizeVectorLoad(Load, DAG);
1071 
1072   SDValue BasePtr = Load->getBasePtr();
1073   EVT PtrVT = BasePtr.getValueType();
1074   EVT MemVT = Load->getMemoryVT();
1075   SDLoc SL(Op);
1076 
1077   const MachinePointerInfo &SrcValue = Load->getMemOperand()->getPointerInfo();
1078 
1079   EVT LoVT, HiVT;
1080   EVT LoMemVT, HiMemVT;
1081   SDValue Lo, Hi;
1082 
1083   std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1084   std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1085   std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT);
1086 
1087   unsigned Size = LoMemVT.getStoreSize();
1088   unsigned BaseAlign = Load->getAlignment();
1089   unsigned HiAlign = MinAlign(BaseAlign, Size);
1090 
1091   SDValue LoLoad
1092     = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1093                      Load->getChain(), BasePtr,
1094                      SrcValue,
1095                      LoMemVT, Load->isVolatile(), Load->isNonTemporal(),
1096                      Load->isInvariant(), BaseAlign);
1097 
1098   SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1099                               DAG.getConstant(Size, SL, PtrVT));
1100 
1101   SDValue HiLoad
1102     = DAG.getExtLoad(Load->getExtensionType(), SL, HiVT,
1103                      Load->getChain(), HiPtr,
1104                      SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1105                      HiMemVT, Load->isVolatile(), Load->isNonTemporal(),
1106                      Load->isInvariant(), HiAlign);
1107 
1108   SDValue Ops[] = {
1109     DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),
1110     DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1111                 LoLoad.getValue(1), HiLoad.getValue(1))
1112   };
1113 
1114   return DAG.getMergeValues(Ops, SL);
1115 }
1116 
1117 // FIXME: This isn't doing anything for SI. This should be used in a target
1118 // combine during type legalization.
1119 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1120                                                SelectionDAG &DAG) const {
1121   StoreSDNode *Store = cast<StoreSDNode>(Op);
1122   EVT MemVT = Store->getMemoryVT();
1123   unsigned MemBits = MemVT.getSizeInBits();
1124 
1125   // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1126   // truncating store into an i32 store.
1127   // XXX: We could also handle optimize other vector bitwidths.
1128   if (!MemVT.isVector() || MemBits > 32) {
1129     return SDValue();
1130   }
1131 
1132   SDLoc DL(Op);
1133   SDValue Value = Store->getValue();
1134   EVT VT = Value.getValueType();
1135   EVT ElemVT = VT.getVectorElementType();
1136   SDValue Ptr = Store->getBasePtr();
1137   EVT MemEltVT = MemVT.getVectorElementType();
1138   unsigned MemEltBits = MemEltVT.getSizeInBits();
1139   unsigned MemNumElements = MemVT.getVectorNumElements();
1140   unsigned PackedSize = MemVT.getStoreSizeInBits();
1141   SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, DL, MVT::i32);
1142 
1143   assert(Value.getValueType().getScalarSizeInBits() >= 32);
1144 
1145   SDValue PackedValue;
1146   for (unsigned i = 0; i < MemNumElements; ++i) {
1147     SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1148                               DAG.getConstant(i, DL, MVT::i32));
1149     Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1150     Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1151 
1152     SDValue Shift = DAG.getConstant(MemEltBits * i, DL, MVT::i32);
1153     Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1154 
1155     if (i == 0) {
1156       PackedValue = Elt;
1157     } else {
1158       PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1159     }
1160   }
1161 
1162   if (PackedSize < 32) {
1163     EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1164     return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1165                              Store->getMemOperand()->getPointerInfo(),
1166                              PackedVT,
1167                              Store->isNonTemporal(), Store->isVolatile(),
1168                              Store->getAlignment());
1169   }
1170 
1171   return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1172                       Store->getMemOperand()->getPointerInfo(),
1173                       Store->isVolatile(),  Store->isNonTemporal(),
1174                       Store->getAlignment());
1175 }
1176 
1177 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1178                                                SelectionDAG &DAG) const {
1179   StoreSDNode *Store = cast<StoreSDNode>(Op);
1180   SDValue Val = Store->getValue();
1181   EVT VT = Val.getValueType();
1182 
1183   // If this is a 2 element vector, we really want to scalarize and not create
1184   // weird 1 element vectors.
1185   if (VT.getVectorNumElements() == 2)
1186     return scalarizeVectorStore(Store, DAG);
1187 
1188   EVT MemVT = Store->getMemoryVT();
1189   SDValue Chain = Store->getChain();
1190   SDValue BasePtr = Store->getBasePtr();
1191   SDLoc SL(Op);
1192 
1193   EVT LoVT, HiVT;
1194   EVT LoMemVT, HiMemVT;
1195   SDValue Lo, Hi;
1196 
1197   std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1198   std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1199   std::tie(Lo, Hi) = DAG.SplitVector(Val, SL, LoVT, HiVT);
1200 
1201   EVT PtrVT = BasePtr.getValueType();
1202   SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1203                               DAG.getConstant(LoMemVT.getStoreSize(), SL,
1204                                               PtrVT));
1205 
1206   const MachinePointerInfo &SrcValue = Store->getMemOperand()->getPointerInfo();
1207   unsigned BaseAlign = Store->getAlignment();
1208   unsigned Size = LoMemVT.getStoreSize();
1209   unsigned HiAlign = MinAlign(BaseAlign, Size);
1210 
1211   SDValue LoStore
1212     = DAG.getTruncStore(Chain, SL, Lo,
1213                         BasePtr,
1214                         SrcValue,
1215                         LoMemVT,
1216                         Store->isNonTemporal(),
1217                         Store->isVolatile(),
1218                         BaseAlign);
1219   SDValue HiStore
1220     = DAG.getTruncStore(Chain, SL, Hi,
1221                         HiPtr,
1222                         SrcValue.getWithOffset(Size),
1223                         HiMemVT,
1224                         Store->isNonTemporal(),
1225                         Store->isVolatile(),
1226                         HiAlign);
1227 
1228   return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1229 }
1230 
1231 // This is a shortcut for integer division because we have fast i32<->f32
1232 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1233 // float is enough to accurately represent up to a 24-bit signed integer.
1234 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG,
1235                                             bool Sign) const {
1236   SDLoc DL(Op);
1237   EVT VT = Op.getValueType();
1238   SDValue LHS = Op.getOperand(0);
1239   SDValue RHS = Op.getOperand(1);
1240   MVT IntVT = MVT::i32;
1241   MVT FltVT = MVT::f32;
1242 
1243   unsigned LHSSignBits = DAG.ComputeNumSignBits(LHS);
1244   if (LHSSignBits < 9)
1245     return SDValue();
1246 
1247   unsigned RHSSignBits = DAG.ComputeNumSignBits(RHS);
1248   if (RHSSignBits < 9)
1249     return SDValue();
1250 
1251   unsigned BitSize = VT.getSizeInBits();
1252   unsigned SignBits = std::min(LHSSignBits, RHSSignBits);
1253   unsigned DivBits = BitSize - SignBits;
1254   if (Sign)
1255     ++DivBits;
1256 
1257   ISD::NodeType ToFp = Sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1258   ISD::NodeType ToInt = Sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1259 
1260   SDValue jq = DAG.getConstant(1, DL, IntVT);
1261 
1262   if (Sign) {
1263     // char|short jq = ia ^ ib;
1264     jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1265 
1266     // jq = jq >> (bitsize - 2)
1267     jq = DAG.getNode(ISD::SRA, DL, VT, jq,
1268                      DAG.getConstant(BitSize - 2, DL, VT));
1269 
1270     // jq = jq | 0x1
1271     jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT));
1272   }
1273 
1274   // int ia = (int)LHS;
1275   SDValue ia = LHS;
1276 
1277   // int ib, (int)RHS;
1278   SDValue ib = RHS;
1279 
1280   // float fa = (float)ia;
1281   SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1282 
1283   // float fb = (float)ib;
1284   SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1285 
1286   SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1287                            fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1288 
1289   // fq = trunc(fq);
1290   fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1291 
1292   // float fqneg = -fq;
1293   SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1294 
1295   // float fr = mad(fqneg, fb, fa);
1296   SDValue fr = DAG.getNode(ISD::FMAD, DL, FltVT, fqneg, fb, fa);
1297 
1298   // int iq = (int)fq;
1299   SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1300 
1301   // fr = fabs(fr);
1302   fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1303 
1304   // fb = fabs(fb);
1305   fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1306 
1307   EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
1308 
1309   // int cv = fr >= fb;
1310   SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1311 
1312   // jq = (cv ? jq : 0);
1313   jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, DL, VT));
1314 
1315   // dst = iq + jq;
1316   SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1317 
1318   // Rem needs compensation, it's easier to recompute it
1319   SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1320   Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1321 
1322   // Truncate to number of bits this divide really is.
1323   if (Sign) {
1324     SDValue InRegSize
1325       = DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), DivBits));
1326     Div = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Div, InRegSize);
1327     Rem = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Rem, InRegSize);
1328   } else {
1329     SDValue TruncMask = DAG.getConstant((UINT64_C(1) << DivBits) - 1, DL, VT);
1330     Div = DAG.getNode(ISD::AND, DL, VT, Div, TruncMask);
1331     Rem = DAG.getNode(ISD::AND, DL, VT, Rem, TruncMask);
1332   }
1333 
1334   return DAG.getMergeValues({ Div, Rem }, DL);
1335 }
1336 
1337 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
1338                                       SelectionDAG &DAG,
1339                                       SmallVectorImpl<SDValue> &Results) const {
1340   assert(Op.getValueType() == MVT::i64);
1341 
1342   SDLoc DL(Op);
1343   EVT VT = Op.getValueType();
1344   EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1345 
1346   SDValue one = DAG.getConstant(1, DL, HalfVT);
1347   SDValue zero = DAG.getConstant(0, DL, HalfVT);
1348 
1349   //HiLo split
1350   SDValue LHS = Op.getOperand(0);
1351   SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);
1352   SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);
1353 
1354   SDValue RHS = Op.getOperand(1);
1355   SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);
1356   SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);
1357 
1358   if (VT == MVT::i64 &&
1359     DAG.MaskedValueIsZero(RHS, APInt::getHighBitsSet(64, 32)) &&
1360     DAG.MaskedValueIsZero(LHS, APInt::getHighBitsSet(64, 32))) {
1361 
1362     SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1363                               LHS_Lo, RHS_Lo);
1364 
1365     SDValue DIV = DAG.getBuildVector(MVT::v2i32, DL, {Res.getValue(0), zero});
1366     SDValue REM = DAG.getBuildVector(MVT::v2i32, DL, {Res.getValue(1), zero});
1367 
1368     Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV));
1369     Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM));
1370     return;
1371   }
1372 
1373   // Get Speculative values
1374   SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
1375   SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
1376 
1377   SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);
1378   SDValue REM = DAG.getBuildVector(MVT::v2i32, DL, {REM_Lo, zero});
1379   REM = DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM);
1380 
1381   SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);
1382   SDValue DIV_Lo = zero;
1383 
1384   const unsigned halfBitWidth = HalfVT.getSizeInBits();
1385 
1386   for (unsigned i = 0; i < halfBitWidth; ++i) {
1387     const unsigned bitPos = halfBitWidth - i - 1;
1388     SDValue POS = DAG.getConstant(bitPos, DL, HalfVT);
1389     // Get value of high bit
1390     SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
1391     HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
1392     HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit);
1393 
1394     // Shift
1395     REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT));
1396     // Add LHS high bit
1397     REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit);
1398 
1399     SDValue BIT = DAG.getConstant(1ULL << bitPos, DL, HalfVT);
1400     SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE);
1401 
1402     DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
1403 
1404     // Update REM
1405     SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
1406     REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
1407   }
1408 
1409   SDValue DIV = DAG.getBuildVector(MVT::v2i32, DL, {DIV_Lo, DIV_Hi});
1410   DIV = DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV);
1411   Results.push_back(DIV);
1412   Results.push_back(REM);
1413 }
1414 
1415 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1416                                            SelectionDAG &DAG) const {
1417   SDLoc DL(Op);
1418   EVT VT = Op.getValueType();
1419 
1420   if (VT == MVT::i64) {
1421     SmallVector<SDValue, 2> Results;
1422     LowerUDIVREM64(Op, DAG, Results);
1423     return DAG.getMergeValues(Results, DL);
1424   }
1425 
1426   if (VT == MVT::i32) {
1427     if (SDValue Res = LowerDIVREM24(Op, DAG, false))
1428       return Res;
1429   }
1430 
1431   SDValue Num = Op.getOperand(0);
1432   SDValue Den = Op.getOperand(1);
1433 
1434   // RCP =  URECIP(Den) = 2^32 / Den + e
1435   // e is rounding error.
1436   SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1437 
1438   // RCP_LO = mul(RCP, Den) */
1439   SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1440 
1441   // RCP_HI = mulhu (RCP, Den) */
1442   SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1443 
1444   // NEG_RCP_LO = -RCP_LO
1445   SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1446                                                      RCP_LO);
1447 
1448   // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1449   SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1450                                            NEG_RCP_LO, RCP_LO,
1451                                            ISD::SETEQ);
1452   // Calculate the rounding error from the URECIP instruction
1453   // E = mulhu(ABS_RCP_LO, RCP)
1454   SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1455 
1456   // RCP_A_E = RCP + E
1457   SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1458 
1459   // RCP_S_E = RCP - E
1460   SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1461 
1462   // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1463   SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1464                                      RCP_A_E, RCP_S_E,
1465                                      ISD::SETEQ);
1466   // Quotient = mulhu(Tmp0, Num)
1467   SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1468 
1469   // Num_S_Remainder = Quotient * Den
1470   SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1471 
1472   // Remainder = Num - Num_S_Remainder
1473   SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1474 
1475   // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1476   SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1477                                                  DAG.getConstant(-1, DL, VT),
1478                                                  DAG.getConstant(0, DL, VT),
1479                                                  ISD::SETUGE);
1480   // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1481   SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1482                                                   Num_S_Remainder,
1483                                                   DAG.getConstant(-1, DL, VT),
1484                                                   DAG.getConstant(0, DL, VT),
1485                                                   ISD::SETUGE);
1486   // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1487   SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1488                                                Remainder_GE_Zero);
1489 
1490   // Calculate Division result:
1491 
1492   // Quotient_A_One = Quotient + 1
1493   SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1494                                        DAG.getConstant(1, DL, VT));
1495 
1496   // Quotient_S_One = Quotient - 1
1497   SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1498                                        DAG.getConstant(1, DL, VT));
1499 
1500   // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1501   SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1502                                      Quotient, Quotient_A_One, ISD::SETEQ);
1503 
1504   // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1505   Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1506                             Quotient_S_One, Div, ISD::SETEQ);
1507 
1508   // Calculate Rem result:
1509 
1510   // Remainder_S_Den = Remainder - Den
1511   SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1512 
1513   // Remainder_A_Den = Remainder + Den
1514   SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1515 
1516   // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1517   SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1518                                     Remainder, Remainder_S_Den, ISD::SETEQ);
1519 
1520   // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1521   Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1522                             Remainder_A_Den, Rem, ISD::SETEQ);
1523   SDValue Ops[2] = {
1524     Div,
1525     Rem
1526   };
1527   return DAG.getMergeValues(Ops, DL);
1528 }
1529 
1530 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1531                                            SelectionDAG &DAG) const {
1532   SDLoc DL(Op);
1533   EVT VT = Op.getValueType();
1534 
1535   SDValue LHS = Op.getOperand(0);
1536   SDValue RHS = Op.getOperand(1);
1537 
1538   SDValue Zero = DAG.getConstant(0, DL, VT);
1539   SDValue NegOne = DAG.getConstant(-1, DL, VT);
1540 
1541   if (VT == MVT::i32) {
1542     if (SDValue Res = LowerDIVREM24(Op, DAG, true))
1543       return Res;
1544   }
1545 
1546   if (VT == MVT::i64 &&
1547       DAG.ComputeNumSignBits(LHS) > 32 &&
1548       DAG.ComputeNumSignBits(RHS) > 32) {
1549     EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1550 
1551     //HiLo split
1552     SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1553     SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1554     SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1555                                  LHS_Lo, RHS_Lo);
1556     SDValue Res[2] = {
1557       DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)),
1558       DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1))
1559     };
1560     return DAG.getMergeValues(Res, DL);
1561   }
1562 
1563   SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1564   SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1565   SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1566   SDValue RSign = LHSign; // Remainder sign is the same as LHS
1567 
1568   LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1569   RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1570 
1571   LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1572   RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1573 
1574   SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1575   SDValue Rem = Div.getValue(1);
1576 
1577   Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1578   Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1579 
1580   Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1581   Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1582 
1583   SDValue Res[2] = {
1584     Div,
1585     Rem
1586   };
1587   return DAG.getMergeValues(Res, DL);
1588 }
1589 
1590 // (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
1591 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
1592   SDLoc SL(Op);
1593   EVT VT = Op.getValueType();
1594   SDValue X = Op.getOperand(0);
1595   SDValue Y = Op.getOperand(1);
1596 
1597   // TODO: Should this propagate fast-math-flags?
1598 
1599   SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
1600   SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
1601   SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
1602 
1603   return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
1604 }
1605 
1606 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1607   SDLoc SL(Op);
1608   SDValue Src = Op.getOperand(0);
1609 
1610   // result = trunc(src)
1611   // if (src > 0.0 && src != result)
1612   //   result += 1.0
1613 
1614   SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1615 
1616   const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
1617   const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
1618 
1619   EVT SetCCVT =
1620       getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
1621 
1622   SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1623   SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1624   SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1625 
1626   SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1627   // TODO: Should this propagate fast-math-flags?
1628   return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1629 }
1630 
1631 static SDValue extractF64Exponent(SDValue Hi, const SDLoc &SL,
1632                                   SelectionDAG &DAG) {
1633   const unsigned FractBits = 52;
1634   const unsigned ExpBits = 11;
1635 
1636   SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
1637                                 Hi,
1638                                 DAG.getConstant(FractBits - 32, SL, MVT::i32),
1639                                 DAG.getConstant(ExpBits, SL, MVT::i32));
1640   SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1641                             DAG.getConstant(1023, SL, MVT::i32));
1642 
1643   return Exp;
1644 }
1645 
1646 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1647   SDLoc SL(Op);
1648   SDValue Src = Op.getOperand(0);
1649 
1650   assert(Op.getValueType() == MVT::f64);
1651 
1652   const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1653   const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1654 
1655   SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1656 
1657   // Extract the upper half, since this is where we will find the sign and
1658   // exponent.
1659   SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1660 
1661   SDValue Exp = extractF64Exponent(Hi, SL, DAG);
1662 
1663   const unsigned FractBits = 52;
1664 
1665   // Extract the sign bit.
1666   const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, SL, MVT::i32);
1667   SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
1668 
1669   // Extend back to to 64-bits.
1670   SDValue SignBit64 = DAG.getBuildVector(MVT::v2i32, SL, {Zero, SignBit});
1671   SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
1672 
1673   SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
1674   const SDValue FractMask
1675     = DAG.getConstant((UINT64_C(1) << FractBits) - 1, SL, MVT::i64);
1676 
1677   SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
1678   SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
1679   SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
1680 
1681   EVT SetCCVT =
1682       getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
1683 
1684   const SDValue FiftyOne = DAG.getConstant(FractBits - 1, SL, MVT::i32);
1685 
1686   SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
1687   SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
1688 
1689   SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
1690   SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
1691 
1692   return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
1693 }
1694 
1695 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
1696   SDLoc SL(Op);
1697   SDValue Src = Op.getOperand(0);
1698 
1699   assert(Op.getValueType() == MVT::f64);
1700 
1701   APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
1702   SDValue C1 = DAG.getConstantFP(C1Val, SL, MVT::f64);
1703   SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
1704 
1705   // TODO: Should this propagate fast-math-flags?
1706 
1707   SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
1708   SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
1709 
1710   SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
1711 
1712   APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
1713   SDValue C2 = DAG.getConstantFP(C2Val, SL, MVT::f64);
1714 
1715   EVT SetCCVT =
1716       getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
1717   SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
1718 
1719   return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
1720 }
1721 
1722 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
1723   // FNEARBYINT and FRINT are the same, except in their handling of FP
1724   // exceptions. Those aren't really meaningful for us, and OpenCL only has
1725   // rint, so just treat them as equivalent.
1726   return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
1727 }
1728 
1729 // XXX - May require not supporting f32 denormals?
1730 SDValue AMDGPUTargetLowering::LowerFROUND32(SDValue Op, SelectionDAG &DAG) const {
1731   SDLoc SL(Op);
1732   SDValue X = Op.getOperand(0);
1733 
1734   SDValue T = DAG.getNode(ISD::FTRUNC, SL, MVT::f32, X);
1735 
1736   // TODO: Should this propagate fast-math-flags?
1737 
1738   SDValue Diff = DAG.getNode(ISD::FSUB, SL, MVT::f32, X, T);
1739 
1740   SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, MVT::f32, Diff);
1741 
1742   const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f32);
1743   const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
1744   const SDValue Half = DAG.getConstantFP(0.5, SL, MVT::f32);
1745 
1746   SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f32, One, X);
1747 
1748   EVT SetCCVT =
1749       getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32);
1750 
1751   SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE);
1752 
1753   SDValue Sel = DAG.getNode(ISD::SELECT, SL, MVT::f32, Cmp, SignOne, Zero);
1754 
1755   return DAG.getNode(ISD::FADD, SL, MVT::f32, T, Sel);
1756 }
1757 
1758 SDValue AMDGPUTargetLowering::LowerFROUND64(SDValue Op, SelectionDAG &DAG) const {
1759   SDLoc SL(Op);
1760   SDValue X = Op.getOperand(0);
1761 
1762   SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X);
1763 
1764   const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1765   const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1766   const SDValue NegOne = DAG.getConstant(-1, SL, MVT::i32);
1767   const SDValue FiftyOne = DAG.getConstant(51, SL, MVT::i32);
1768   EVT SetCCVT =
1769       getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
1770 
1771   SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
1772 
1773   SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One);
1774 
1775   SDValue Exp = extractF64Exponent(Hi, SL, DAG);
1776 
1777   const SDValue Mask = DAG.getConstant(INT64_C(0x000fffffffffffff), SL,
1778                                        MVT::i64);
1779 
1780   SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp);
1781   SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64,
1782                           DAG.getConstant(INT64_C(0x0008000000000000), SL,
1783                                           MVT::i64),
1784                           Exp);
1785 
1786   SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M);
1787   SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT,
1788                               DAG.getConstant(0, SL, MVT::i64), Tmp0,
1789                               ISD::SETNE);
1790 
1791   SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1,
1792                              D, DAG.getConstant(0, SL, MVT::i64));
1793   SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2);
1794 
1795   K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64));
1796   K = DAG.getNode(ISD::BITCAST, SL, MVT::f64, K);
1797 
1798   SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
1799   SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
1800   SDValue ExpEqNegOne = DAG.getSetCC(SL, SetCCVT, NegOne, Exp, ISD::SETEQ);
1801 
1802   SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64,
1803                             ExpEqNegOne,
1804                             DAG.getConstantFP(1.0, SL, MVT::f64),
1805                             DAG.getConstantFP(0.0, SL, MVT::f64));
1806 
1807   SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X);
1808 
1809   K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpLt0, S, K);
1810   K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpGt51, X, K);
1811 
1812   return K;
1813 }
1814 
1815 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
1816   EVT VT = Op.getValueType();
1817 
1818   if (VT == MVT::f32)
1819     return LowerFROUND32(Op, DAG);
1820 
1821   if (VT == MVT::f64)
1822     return LowerFROUND64(Op, DAG);
1823 
1824   llvm_unreachable("unhandled type");
1825 }
1826 
1827 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
1828   SDLoc SL(Op);
1829   SDValue Src = Op.getOperand(0);
1830 
1831   // result = trunc(src);
1832   // if (src < 0.0 && src != result)
1833   //   result += -1.0.
1834 
1835   SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1836 
1837   const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
1838   const SDValue NegOne = DAG.getConstantFP(-1.0, SL, MVT::f64);
1839 
1840   EVT SetCCVT =
1841       getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
1842 
1843   SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
1844   SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1845   SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1846 
1847   SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
1848   // TODO: Should this propagate fast-math-flags?
1849   return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1850 }
1851 
1852 SDValue AMDGPUTargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
1853   SDLoc SL(Op);
1854   SDValue Src = Op.getOperand(0);
1855   bool ZeroUndef = Op.getOpcode() == ISD::CTLZ_ZERO_UNDEF;
1856 
1857   if (ZeroUndef && Src.getValueType() == MVT::i32)
1858     return DAG.getNode(AMDGPUISD::FFBH_U32, SL, MVT::i32, Src);
1859 
1860   SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1861 
1862   const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1863   const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1864 
1865   SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
1866   SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
1867 
1868   EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(),
1869                                    *DAG.getContext(), MVT::i32);
1870 
1871   SDValue Hi0 = DAG.getSetCC(SL, SetCCVT, Hi, Zero, ISD::SETEQ);
1872 
1873   SDValue CtlzLo = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i32, Lo);
1874   SDValue CtlzHi = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i32, Hi);
1875 
1876   const SDValue Bits32 = DAG.getConstant(32, SL, MVT::i32);
1877   SDValue Add = DAG.getNode(ISD::ADD, SL, MVT::i32, CtlzLo, Bits32);
1878 
1879   // ctlz(x) = hi_32(x) == 0 ? ctlz(lo_32(x)) + 32 : ctlz(hi_32(x))
1880   SDValue NewCtlz = DAG.getNode(ISD::SELECT, SL, MVT::i32, Hi0, Add, CtlzHi);
1881 
1882   if (!ZeroUndef) {
1883     // Test if the full 64-bit input is zero.
1884 
1885     // FIXME: DAG combines turn what should be an s_and_b64 into a v_or_b32,
1886     // which we probably don't want.
1887     SDValue Lo0 = DAG.getSetCC(SL, SetCCVT, Lo, Zero, ISD::SETEQ);
1888     SDValue SrcIsZero = DAG.getNode(ISD::AND, SL, SetCCVT, Lo0, Hi0);
1889 
1890     // TODO: If i64 setcc is half rate, it can result in 1 fewer instruction
1891     // with the same cycles, otherwise it is slower.
1892     // SDValue SrcIsZero = DAG.getSetCC(SL, SetCCVT, Src,
1893     // DAG.getConstant(0, SL, MVT::i64), ISD::SETEQ);
1894 
1895     const SDValue Bits32 = DAG.getConstant(64, SL, MVT::i32);
1896 
1897     // The instruction returns -1 for 0 input, but the defined intrinsic
1898     // behavior is to return the number of bits.
1899     NewCtlz = DAG.getNode(ISD::SELECT, SL, MVT::i32,
1900                           SrcIsZero, Bits32, NewCtlz);
1901   }
1902 
1903   return DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i64, NewCtlz);
1904 }
1905 
1906 SDValue AMDGPUTargetLowering::LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG,
1907                                                bool Signed) const {
1908   // Unsigned
1909   // cul2f(ulong u)
1910   //{
1911   //  uint lz = clz(u);
1912   //  uint e = (u != 0) ? 127U + 63U - lz : 0;
1913   //  u = (u << lz) & 0x7fffffffffffffffUL;
1914   //  ulong t = u & 0xffffffffffUL;
1915   //  uint v = (e << 23) | (uint)(u >> 40);
1916   //  uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U);
1917   //  return as_float(v + r);
1918   //}
1919   // Signed
1920   // cl2f(long l)
1921   //{
1922   //  long s = l >> 63;
1923   //  float r = cul2f((l + s) ^ s);
1924   //  return s ? -r : r;
1925   //}
1926 
1927   SDLoc SL(Op);
1928   SDValue Src = Op.getOperand(0);
1929   SDValue L = Src;
1930 
1931   SDValue S;
1932   if (Signed) {
1933     const SDValue SignBit = DAG.getConstant(63, SL, MVT::i64);
1934     S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit);
1935 
1936     SDValue LPlusS = DAG.getNode(ISD::ADD, SL, MVT::i64, L, S);
1937     L = DAG.getNode(ISD::XOR, SL, MVT::i64, LPlusS, S);
1938   }
1939 
1940   EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(),
1941                                    *DAG.getContext(), MVT::f32);
1942 
1943 
1944   SDValue ZeroI32 = DAG.getConstant(0, SL, MVT::i32);
1945   SDValue ZeroI64 = DAG.getConstant(0, SL, MVT::i64);
1946   SDValue LZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i64, L);
1947   LZ = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LZ);
1948 
1949   SDValue K = DAG.getConstant(127U + 63U, SL, MVT::i32);
1950   SDValue E = DAG.getSelect(SL, MVT::i32,
1951     DAG.getSetCC(SL, SetCCVT, L, ZeroI64, ISD::SETNE),
1952     DAG.getNode(ISD::SUB, SL, MVT::i32, K, LZ),
1953     ZeroI32);
1954 
1955   SDValue U = DAG.getNode(ISD::AND, SL, MVT::i64,
1956     DAG.getNode(ISD::SHL, SL, MVT::i64, L, LZ),
1957     DAG.getConstant((-1ULL) >> 1, SL, MVT::i64));
1958 
1959   SDValue T = DAG.getNode(ISD::AND, SL, MVT::i64, U,
1960                           DAG.getConstant(0xffffffffffULL, SL, MVT::i64));
1961 
1962   SDValue UShl = DAG.getNode(ISD::SRL, SL, MVT::i64,
1963                              U, DAG.getConstant(40, SL, MVT::i64));
1964 
1965   SDValue V = DAG.getNode(ISD::OR, SL, MVT::i32,
1966     DAG.getNode(ISD::SHL, SL, MVT::i32, E, DAG.getConstant(23, SL, MVT::i32)),
1967     DAG.getNode(ISD::TRUNCATE, SL, MVT::i32,  UShl));
1968 
1969   SDValue C = DAG.getConstant(0x8000000000ULL, SL, MVT::i64);
1970   SDValue RCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETUGT);
1971   SDValue TCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETEQ);
1972 
1973   SDValue One = DAG.getConstant(1, SL, MVT::i32);
1974 
1975   SDValue VTrunc1 = DAG.getNode(ISD::AND, SL, MVT::i32, V, One);
1976 
1977   SDValue R = DAG.getSelect(SL, MVT::i32,
1978     RCmp,
1979     One,
1980     DAG.getSelect(SL, MVT::i32, TCmp, VTrunc1, ZeroI32));
1981   R = DAG.getNode(ISD::ADD, SL, MVT::i32, V, R);
1982   R = DAG.getNode(ISD::BITCAST, SL, MVT::f32, R);
1983 
1984   if (!Signed)
1985     return R;
1986 
1987   SDValue RNeg = DAG.getNode(ISD::FNEG, SL, MVT::f32, R);
1988   return DAG.getSelect(SL, MVT::f32, DAG.getSExtOrTrunc(S, SL, SetCCVT), RNeg, R);
1989 }
1990 
1991 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
1992                                                bool Signed) const {
1993   SDLoc SL(Op);
1994   SDValue Src = Op.getOperand(0);
1995 
1996   SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1997 
1998   SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
1999                            DAG.getConstant(0, SL, MVT::i32));
2000   SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2001                            DAG.getConstant(1, SL, MVT::i32));
2002 
2003   SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
2004                               SL, MVT::f64, Hi);
2005 
2006   SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
2007 
2008   SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
2009                               DAG.getConstant(32, SL, MVT::i32));
2010   // TODO: Should this propagate fast-math-flags?
2011   return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
2012 }
2013 
2014 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
2015                                                SelectionDAG &DAG) const {
2016   assert(Op.getOperand(0).getValueType() == MVT::i64 &&
2017          "operation should be legal");
2018 
2019   EVT DestVT = Op.getValueType();
2020   if (DestVT == MVT::f64)
2021     return LowerINT_TO_FP64(Op, DAG, false);
2022 
2023   if (DestVT == MVT::f32)
2024     return LowerINT_TO_FP32(Op, DAG, false);
2025 
2026   return SDValue();
2027 }
2028 
2029 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
2030                                               SelectionDAG &DAG) const {
2031   assert(Op.getOperand(0).getValueType() == MVT::i64 &&
2032          "operation should be legal");
2033 
2034   EVT DestVT = Op.getValueType();
2035   if (DestVT == MVT::f32)
2036     return LowerINT_TO_FP32(Op, DAG, true);
2037 
2038   if (DestVT == MVT::f64)
2039     return LowerINT_TO_FP64(Op, DAG, true);
2040 
2041   return SDValue();
2042 }
2043 
2044 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
2045                                                bool Signed) const {
2046   SDLoc SL(Op);
2047 
2048   SDValue Src = Op.getOperand(0);
2049 
2050   SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2051 
2052   SDValue K0 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), SL,
2053                                  MVT::f64);
2054   SDValue K1 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), SL,
2055                                  MVT::f64);
2056   // TODO: Should this propagate fast-math-flags?
2057   SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
2058 
2059   SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
2060 
2061 
2062   SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
2063 
2064   SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
2065                            MVT::i32, FloorMul);
2066   SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
2067 
2068   SDValue Result = DAG.getBuildVector(MVT::v2i32, SL, {Lo, Hi});
2069 
2070   return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
2071 }
2072 
2073 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
2074                                               SelectionDAG &DAG) const {
2075   SDValue Src = Op.getOperand(0);
2076 
2077   if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2078     return LowerFP64_TO_INT(Op, DAG, true);
2079 
2080   return SDValue();
2081 }
2082 
2083 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
2084                                               SelectionDAG &DAG) const {
2085   SDValue Src = Op.getOperand(0);
2086 
2087   if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2088     return LowerFP64_TO_INT(Op, DAG, false);
2089 
2090   return SDValue();
2091 }
2092 
2093 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
2094                                                      SelectionDAG &DAG) const {
2095   EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
2096   MVT VT = Op.getSimpleValueType();
2097   MVT ScalarVT = VT.getScalarType();
2098 
2099   if (!VT.isVector())
2100     return SDValue();
2101 
2102   SDValue Src = Op.getOperand(0);
2103   SDLoc DL(Op);
2104 
2105   // TODO: Don't scalarize on Evergreen?
2106   unsigned NElts = VT.getVectorNumElements();
2107   SmallVector<SDValue, 8> Args;
2108   DAG.ExtractVectorElements(Src, Args, 0, NElts);
2109 
2110   SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
2111   for (unsigned I = 0; I < NElts; ++I)
2112     Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
2113 
2114   return DAG.getBuildVector(VT, DL, Args);
2115 }
2116 
2117 //===----------------------------------------------------------------------===//
2118 // Custom DAG optimizations
2119 //===----------------------------------------------------------------------===//
2120 
2121 static bool isU24(SDValue Op, SelectionDAG &DAG) {
2122   APInt KnownZero, KnownOne;
2123   EVT VT = Op.getValueType();
2124   DAG.computeKnownBits(Op, KnownZero, KnownOne);
2125 
2126   return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
2127 }
2128 
2129 static bool isI24(SDValue Op, SelectionDAG &DAG) {
2130   EVT VT = Op.getValueType();
2131 
2132   // In order for this to be a signed 24-bit value, bit 23, must
2133   // be a sign bit.
2134   return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
2135                                      // as unsigned 24-bit values.
2136          (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
2137 }
2138 
2139 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
2140 
2141   SelectionDAG &DAG = DCI.DAG;
2142   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2143   EVT VT = Op.getValueType();
2144 
2145   APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
2146   APInt KnownZero, KnownOne;
2147   TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
2148   if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
2149     DCI.CommitTargetLoweringOpt(TLO);
2150 }
2151 
2152 template <typename IntTy>
2153 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0, uint32_t Offset,
2154                                uint32_t Width, const SDLoc &DL) {
2155   if (Width + Offset < 32) {
2156     uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2157     IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2158     return DAG.getConstant(Result, DL, MVT::i32);
2159   }
2160 
2161   return DAG.getConstant(Src0 >> Offset, DL, MVT::i32);
2162 }
2163 
2164 static bool usesAllNormalStores(SDNode *LoadVal) {
2165   for (SDNode::use_iterator I = LoadVal->use_begin(); !I.atEnd(); ++I) {
2166     if (!ISD::isNormalStore(*I))
2167       return false;
2168   }
2169 
2170   return true;
2171 }
2172 
2173 // If we have a copy of an illegal type, replace it with a load / store of an
2174 // equivalently sized legal type. This avoids intermediate bit pack / unpack
2175 // instructions emitted when handling extloads and truncstores. Ideally we could
2176 // recognize the pack / unpack pattern to eliminate it.
2177 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2178                                                   DAGCombinerInfo &DCI) const {
2179   if (!DCI.isBeforeLegalize())
2180     return SDValue();
2181 
2182   StoreSDNode *SN = cast<StoreSDNode>(N);
2183   SDValue Value = SN->getValue();
2184   EVT VT = Value.getValueType();
2185 
2186   if (isTypeLegal(VT) || SN->isVolatile() ||
2187       !ISD::isNormalLoad(Value.getNode()) || VT.getSizeInBits() < 8)
2188     return SDValue();
2189 
2190   LoadSDNode *LoadVal = cast<LoadSDNode>(Value);
2191   if (LoadVal->isVolatile() || !usesAllNormalStores(LoadVal))
2192     return SDValue();
2193 
2194   EVT MemVT = LoadVal->getMemoryVT();
2195   if (!MemVT.isRound())
2196     return SDValue();
2197 
2198   SDLoc SL(N);
2199   SelectionDAG &DAG = DCI.DAG;
2200   EVT LoadVT = getEquivalentMemType(*DAG.getContext(), MemVT);
2201 
2202   SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
2203                                 LoadVT, SL,
2204                                 LoadVal->getChain(),
2205                                 LoadVal->getBasePtr(),
2206                                 LoadVal->getOffset(),
2207                                 LoadVT,
2208                                 LoadVal->getMemOperand());
2209 
2210   SDValue CastLoad = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad.getValue(0));
2211   DCI.CombineTo(LoadVal, CastLoad, NewLoad.getValue(1), false);
2212 
2213   return DAG.getStore(SN->getChain(), SL, NewLoad,
2214                       SN->getBasePtr(), SN->getMemOperand());
2215 }
2216 
2217 // TODO: Should repeat for other bit ops.
2218 SDValue AMDGPUTargetLowering::performAndCombine(SDNode *N,
2219                                                 DAGCombinerInfo &DCI) const {
2220   if (N->getValueType(0) != MVT::i64)
2221     return SDValue();
2222 
2223   // Break up 64-bit and of a constant into two 32-bit ands. This will typically
2224   // happen anyway for a VALU 64-bit and. This exposes other 32-bit integer
2225   // combine opportunities since most 64-bit operations are decomposed this way.
2226   // TODO: We won't want this for SALU especially if it is an inline immediate.
2227   const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
2228   if (!RHS)
2229     return SDValue();
2230 
2231   uint64_t Val = RHS->getZExtValue();
2232   if (Lo_32(Val) != 0 && Hi_32(Val) != 0 && !RHS->hasOneUse()) {
2233     // If either half of the constant is 0, this is really a 32-bit and, so
2234     // split it. If we can re-use the full materialized constant, keep it.
2235     return SDValue();
2236   }
2237 
2238   SDLoc SL(N);
2239   SelectionDAG &DAG = DCI.DAG;
2240 
2241   SDValue Lo, Hi;
2242   std::tie(Lo, Hi) = split64BitValue(N->getOperand(0), DAG);
2243 
2244   SDValue LoRHS = DAG.getConstant(Lo_32(Val), SL, MVT::i32);
2245   SDValue HiRHS = DAG.getConstant(Hi_32(Val), SL, MVT::i32);
2246 
2247   SDValue LoAnd = DAG.getNode(ISD::AND, SL, MVT::i32, Lo, LoRHS);
2248   SDValue HiAnd = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, HiRHS);
2249 
2250   // Re-visit the ands. It's possible we eliminated one of them and it could
2251   // simplify the vector.
2252   DCI.AddToWorklist(Lo.getNode());
2253   DCI.AddToWorklist(Hi.getNode());
2254 
2255   SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {LoAnd, HiAnd});
2256   return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
2257 }
2258 
2259 SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
2260                                                 DAGCombinerInfo &DCI) const {
2261   if (N->getValueType(0) != MVT::i64)
2262     return SDValue();
2263 
2264   // i64 (shl x, C) -> (build_pair 0, (shl x, C -32))
2265 
2266   // On some subtargets, 64-bit shift is a quarter rate instruction. In the
2267   // common case, splitting this into a move and a 32-bit shift is faster and
2268   // the same code size.
2269   const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
2270   if (!RHS)
2271     return SDValue();
2272 
2273   unsigned RHSVal = RHS->getZExtValue();
2274   if (RHSVal < 32)
2275     return SDValue();
2276 
2277   SDValue LHS = N->getOperand(0);
2278 
2279   SDLoc SL(N);
2280   SelectionDAG &DAG = DCI.DAG;
2281 
2282   SDValue ShiftAmt = DAG.getConstant(RHSVal - 32, SL, MVT::i32);
2283 
2284   SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS);
2285   SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, ShiftAmt);
2286 
2287   const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2288 
2289   SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {Zero, NewShift});
2290   return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
2291 }
2292 
2293 SDValue AMDGPUTargetLowering::performSraCombine(SDNode *N,
2294                                                 DAGCombinerInfo &DCI) const {
2295   if (N->getValueType(0) != MVT::i64)
2296     return SDValue();
2297 
2298   const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
2299   if (!RHS)
2300     return SDValue();
2301 
2302   SelectionDAG &DAG = DCI.DAG;
2303   SDLoc SL(N);
2304   unsigned RHSVal = RHS->getZExtValue();
2305 
2306   // (sra i64:x, 32) -> build_pair x, (sra hi_32(x), 31)
2307   if (RHSVal == 32) {
2308     SDValue Hi = getHiHalf64(N->getOperand(0), DAG);
2309     SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,
2310                                    DAG.getConstant(31, SL, MVT::i32));
2311 
2312     SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {Hi, NewShift});
2313     return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec);
2314   }
2315 
2316   // (sra i64:x, 63) -> build_pair (sra hi_32(x), 31), (sra hi_32(x), 31)
2317   if (RHSVal == 63) {
2318     SDValue Hi = getHiHalf64(N->getOperand(0), DAG);
2319     SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,
2320                                    DAG.getConstant(31, SL, MVT::i32));
2321     SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, NewShift});
2322     return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec);
2323   }
2324 
2325   return SDValue();
2326 }
2327 
2328 SDValue AMDGPUTargetLowering::performSrlCombine(SDNode *N,
2329                                                 DAGCombinerInfo &DCI) const {
2330   if (N->getValueType(0) != MVT::i64)
2331     return SDValue();
2332 
2333   const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
2334   if (!RHS)
2335     return SDValue();
2336 
2337   unsigned ShiftAmt = RHS->getZExtValue();
2338   if (ShiftAmt < 32)
2339     return SDValue();
2340 
2341   // srl i64:x, C for C >= 32
2342   // =>
2343   //   build_pair (srl hi_32(x), C - 32), 0
2344 
2345   SelectionDAG &DAG = DCI.DAG;
2346   SDLoc SL(N);
2347 
2348   SDValue One = DAG.getConstant(1, SL, MVT::i32);
2349   SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2350 
2351   SDValue VecOp = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, N->getOperand(0));
2352   SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32,
2353                            VecOp, One);
2354 
2355   SDValue NewConst = DAG.getConstant(ShiftAmt - 32, SL, MVT::i32);
2356   SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst);
2357 
2358   SDValue BuildPair = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, Zero});
2359 
2360   return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildPair);
2361 }
2362 
2363 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
2364                                                 DAGCombinerInfo &DCI) const {
2365   EVT VT = N->getValueType(0);
2366 
2367   if (VT.isVector() || VT.getSizeInBits() > 32)
2368     return SDValue();
2369 
2370   SelectionDAG &DAG = DCI.DAG;
2371   SDLoc DL(N);
2372 
2373   SDValue N0 = N->getOperand(0);
2374   SDValue N1 = N->getOperand(1);
2375   SDValue Mul;
2376 
2377   if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
2378     N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
2379     N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
2380     Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
2381   } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
2382     N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
2383     N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
2384     Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
2385   } else {
2386     return SDValue();
2387   }
2388 
2389   // We need to use sext even for MUL_U24, because MUL_U24 is used
2390   // for signed multiply of 8 and 16-bit types.
2391   return DAG.getSExtOrTrunc(Mul, DL, VT);
2392 }
2393 
2394 static bool isNegativeOne(SDValue Val) {
2395   if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val))
2396     return C->isAllOnesValue();
2397   return false;
2398 }
2399 
2400 static bool isCtlzOpc(unsigned Opc) {
2401   return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF;
2402 }
2403 
2404 // Get FFBH node if the incoming op may have been type legalized from a smaller
2405 // type VT.
2406 // Need to match pre-legalized type because the generic legalization inserts the
2407 // add/sub between the select and compare.
2408 static SDValue getFFBH_U32(const TargetLowering &TLI, SelectionDAG &DAG,
2409                            const SDLoc &SL, SDValue Op) {
2410   EVT VT = Op.getValueType();
2411   EVT LegalVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2412   if (LegalVT != MVT::i32)
2413     return SDValue();
2414 
2415   if (VT != MVT::i32)
2416     Op = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Op);
2417 
2418   SDValue FFBH = DAG.getNode(AMDGPUISD::FFBH_U32, SL, MVT::i32, Op);
2419   if (VT != MVT::i32)
2420     FFBH = DAG.getNode(ISD::TRUNCATE, SL, VT, FFBH);
2421 
2422   return FFBH;
2423 }
2424 
2425 // The native instructions return -1 on 0 input. Optimize out a select that
2426 // produces -1 on 0.
2427 //
2428 // TODO: If zero is not undef, we could also do this if the output is compared
2429 // against the bitwidth.
2430 //
2431 // TODO: Should probably combine against FFBH_U32 instead of ctlz directly.
2432 SDValue AMDGPUTargetLowering::performCtlzCombine(const SDLoc &SL, SDValue Cond,
2433                                                  SDValue LHS, SDValue RHS,
2434                                                  DAGCombinerInfo &DCI) const {
2435   ConstantSDNode *CmpRhs = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2436   if (!CmpRhs || !CmpRhs->isNullValue())
2437     return SDValue();
2438 
2439   SelectionDAG &DAG = DCI.DAG;
2440   ISD::CondCode CCOpcode = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
2441   SDValue CmpLHS = Cond.getOperand(0);
2442 
2443   // select (setcc x, 0, eq), -1, (ctlz_zero_undef x) -> ffbh_u32 x
2444   if (CCOpcode == ISD::SETEQ &&
2445       isCtlzOpc(RHS.getOpcode()) &&
2446       RHS.getOperand(0) == CmpLHS &&
2447       isNegativeOne(LHS)) {
2448     return getFFBH_U32(*this, DAG, SL, CmpLHS);
2449   }
2450 
2451   // select (setcc x, 0, ne), (ctlz_zero_undef x), -1 -> ffbh_u32 x
2452   if (CCOpcode == ISD::SETNE &&
2453       isCtlzOpc(LHS.getOpcode()) &&
2454       LHS.getOperand(0) == CmpLHS &&
2455       isNegativeOne(RHS)) {
2456     return getFFBH_U32(*this, DAG, SL, CmpLHS);
2457   }
2458 
2459   return SDValue();
2460 }
2461 
2462 SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,
2463                                                    DAGCombinerInfo &DCI) const {
2464   SDValue Cond = N->getOperand(0);
2465   if (Cond.getOpcode() != ISD::SETCC)
2466     return SDValue();
2467 
2468   EVT VT = N->getValueType(0);
2469   SDValue LHS = Cond.getOperand(0);
2470   SDValue RHS = Cond.getOperand(1);
2471   SDValue CC = Cond.getOperand(2);
2472 
2473   SDValue True = N->getOperand(1);
2474   SDValue False = N->getOperand(2);
2475 
2476   if (VT == MVT::f32 && Cond.hasOneUse()) {
2477     SDValue MinMax
2478       = CombineFMinMaxLegacy(SDLoc(N), VT, LHS, RHS, True, False, CC, DCI);
2479     // Revisit this node so we can catch min3/max3/med3 patterns.
2480     //DCI.AddToWorklist(MinMax.getNode());
2481     return MinMax;
2482   }
2483 
2484   // There's no reason to not do this if the condition has other uses.
2485   return performCtlzCombine(SDLoc(N), Cond, True, False, DCI);
2486 }
2487 
2488 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
2489                                                 DAGCombinerInfo &DCI) const {
2490   SelectionDAG &DAG = DCI.DAG;
2491   SDLoc DL(N);
2492 
2493   switch(N->getOpcode()) {
2494   default:
2495     break;
2496   case ISD::BITCAST: {
2497     EVT DestVT = N->getValueType(0);
2498     if (DestVT.getSizeInBits() != 64 && !DestVT.isVector())
2499       break;
2500 
2501     // Fold bitcasts of constants.
2502     //
2503     // v2i32 (bitcast i64:k) -> build_vector lo_32(k), hi_32(k)
2504     // TODO: Generalize and move to DAGCombiner
2505     SDValue Src = N->getOperand(0);
2506     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src)) {
2507       assert(Src.getValueType() == MVT::i64);
2508       SDLoc SL(N);
2509       uint64_t CVal = C->getZExtValue();
2510       return DAG.getNode(ISD::BUILD_VECTOR, SL, DestVT,
2511                          DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
2512                          DAG.getConstant(Hi_32(CVal), SL, MVT::i32));
2513     }
2514 
2515     if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Src)) {
2516       const APInt &Val = C->getValueAPF().bitcastToAPInt();
2517       SDLoc SL(N);
2518       uint64_t CVal = Val.getZExtValue();
2519       SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
2520                                 DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
2521                                 DAG.getConstant(Hi_32(CVal), SL, MVT::i32));
2522 
2523       return DAG.getNode(ISD::BITCAST, SL, DestVT, Vec);
2524     }
2525 
2526     break;
2527   }
2528   case ISD::SHL: {
2529     if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
2530       break;
2531 
2532     return performShlCombine(N, DCI);
2533   }
2534   case ISD::SRL: {
2535     if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
2536       break;
2537 
2538     return performSrlCombine(N, DCI);
2539   }
2540   case ISD::SRA: {
2541     if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
2542       break;
2543 
2544     return performSraCombine(N, DCI);
2545   }
2546   case ISD::AND: {
2547     if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
2548       break;
2549 
2550     return performAndCombine(N, DCI);
2551   }
2552   case ISD::MUL:
2553     return performMulCombine(N, DCI);
2554   case AMDGPUISD::MUL_I24:
2555   case AMDGPUISD::MUL_U24: {
2556     SDValue N0 = N->getOperand(0);
2557     SDValue N1 = N->getOperand(1);
2558     simplifyI24(N0, DCI);
2559     simplifyI24(N1, DCI);
2560     return SDValue();
2561   }
2562   case ISD::SELECT:
2563     return performSelectCombine(N, DCI);
2564   case AMDGPUISD::BFE_I32:
2565   case AMDGPUISD::BFE_U32: {
2566     assert(!N->getValueType(0).isVector() &&
2567            "Vector handling of BFE not implemented");
2568     ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
2569     if (!Width)
2570       break;
2571 
2572     uint32_t WidthVal = Width->getZExtValue() & 0x1f;
2573     if (WidthVal == 0)
2574       return DAG.getConstant(0, DL, MVT::i32);
2575 
2576     ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2577     if (!Offset)
2578       break;
2579 
2580     SDValue BitsFrom = N->getOperand(0);
2581     uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
2582 
2583     bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
2584 
2585     if (OffsetVal == 0) {
2586       // This is already sign / zero extended, so try to fold away extra BFEs.
2587       unsigned SignBits =  Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
2588 
2589       unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
2590       if (OpSignBits >= SignBits)
2591         return BitsFrom;
2592 
2593       EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
2594       if (Signed) {
2595         // This is a sign_extend_inreg. Replace it to take advantage of existing
2596         // DAG Combines. If not eliminated, we will match back to BFE during
2597         // selection.
2598 
2599         // TODO: The sext_inreg of extended types ends, although we can could
2600         // handle them in a single BFE.
2601         return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
2602                            DAG.getValueType(SmallVT));
2603       }
2604 
2605       return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
2606     }
2607 
2608     if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
2609       if (Signed) {
2610         return constantFoldBFE<int32_t>(DAG,
2611                                         CVal->getSExtValue(),
2612                                         OffsetVal,
2613                                         WidthVal,
2614                                         DL);
2615       }
2616 
2617       return constantFoldBFE<uint32_t>(DAG,
2618                                        CVal->getZExtValue(),
2619                                        OffsetVal,
2620                                        WidthVal,
2621                                        DL);
2622     }
2623 
2624     if ((OffsetVal + WidthVal) >= 32) {
2625       SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32);
2626       return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2627                          BitsFrom, ShiftVal);
2628     }
2629 
2630     if (BitsFrom.hasOneUse()) {
2631       APInt Demanded = APInt::getBitsSet(32,
2632                                          OffsetVal,
2633                                          OffsetVal + WidthVal);
2634 
2635       APInt KnownZero, KnownOne;
2636       TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2637                                             !DCI.isBeforeLegalizeOps());
2638       const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2639       if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
2640           TLI.SimplifyDemandedBits(BitsFrom, Demanded,
2641                                    KnownZero, KnownOne, TLO)) {
2642         DCI.CommitTargetLoweringOpt(TLO);
2643       }
2644     }
2645 
2646     break;
2647   }
2648 
2649   case ISD::STORE:
2650     return performStoreCombine(N, DCI);
2651   }
2652   return SDValue();
2653 }
2654 
2655 //===----------------------------------------------------------------------===//
2656 // Helper functions
2657 //===----------------------------------------------------------------------===//
2658 
2659 void AMDGPUTargetLowering::getOriginalFunctionArgs(
2660                                SelectionDAG &DAG,
2661                                const Function *F,
2662                                const SmallVectorImpl<ISD::InputArg> &Ins,
2663                                SmallVectorImpl<ISD::InputArg> &OrigIns) const {
2664 
2665   for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
2666     if (Ins[i].ArgVT == Ins[i].VT) {
2667       OrigIns.push_back(Ins[i]);
2668       continue;
2669     }
2670 
2671     EVT VT;
2672     if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2673       // Vector has been split into scalars.
2674       VT = Ins[i].ArgVT.getVectorElementType();
2675     } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
2676                Ins[i].ArgVT.getVectorElementType() !=
2677                Ins[i].VT.getVectorElementType()) {
2678       // Vector elements have been promoted
2679       VT = Ins[i].ArgVT;
2680     } else {
2681       // Vector has been spilt into smaller vectors.
2682       VT = Ins[i].VT;
2683     }
2684 
2685     ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2686                       Ins[i].OrigArgIndex, Ins[i].PartOffset);
2687     OrigIns.push_back(Arg);
2688   }
2689 }
2690 
2691 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2692                                                   const TargetRegisterClass *RC,
2693                                                    unsigned Reg, EVT VT) const {
2694   MachineFunction &MF = DAG.getMachineFunction();
2695   MachineRegisterInfo &MRI = MF.getRegInfo();
2696   unsigned VirtualRegister;
2697   if (!MRI.isLiveIn(Reg)) {
2698     VirtualRegister = MRI.createVirtualRegister(RC);
2699     MRI.addLiveIn(Reg, VirtualRegister);
2700   } else {
2701     VirtualRegister = MRI.getLiveInVirtReg(Reg);
2702   }
2703   return DAG.getRegister(VirtualRegister, VT);
2704 }
2705 
2706 uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(
2707     const AMDGPUMachineFunction *MFI, const ImplicitParameter Param) const {
2708   uint64_t ArgOffset = MFI->ABIArgOffset;
2709   switch (Param) {
2710   case GRID_DIM:
2711     return ArgOffset;
2712   case GRID_OFFSET:
2713     return ArgOffset + 4;
2714   }
2715   llvm_unreachable("unexpected implicit parameter type");
2716 }
2717 
2718 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2719 
2720 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2721   switch ((AMDGPUISD::NodeType)Opcode) {
2722   case AMDGPUISD::FIRST_NUMBER: break;
2723   // AMDIL DAG nodes
2724   NODE_NAME_CASE(CALL);
2725   NODE_NAME_CASE(UMUL);
2726   NODE_NAME_CASE(BRANCH_COND);
2727 
2728   // AMDGPU DAG nodes
2729   NODE_NAME_CASE(ENDPGM)
2730   NODE_NAME_CASE(RETURN)
2731   NODE_NAME_CASE(DWORDADDR)
2732   NODE_NAME_CASE(FRACT)
2733   NODE_NAME_CASE(CLAMP)
2734   NODE_NAME_CASE(COS_HW)
2735   NODE_NAME_CASE(SIN_HW)
2736   NODE_NAME_CASE(FMAX_LEGACY)
2737   NODE_NAME_CASE(FMIN_LEGACY)
2738   NODE_NAME_CASE(FMAX3)
2739   NODE_NAME_CASE(SMAX3)
2740   NODE_NAME_CASE(UMAX3)
2741   NODE_NAME_CASE(FMIN3)
2742   NODE_NAME_CASE(SMIN3)
2743   NODE_NAME_CASE(UMIN3)
2744   NODE_NAME_CASE(FMED3)
2745   NODE_NAME_CASE(SMED3)
2746   NODE_NAME_CASE(UMED3)
2747   NODE_NAME_CASE(URECIP)
2748   NODE_NAME_CASE(DIV_SCALE)
2749   NODE_NAME_CASE(DIV_FMAS)
2750   NODE_NAME_CASE(DIV_FIXUP)
2751   NODE_NAME_CASE(TRIG_PREOP)
2752   NODE_NAME_CASE(RCP)
2753   NODE_NAME_CASE(RSQ)
2754   NODE_NAME_CASE(RSQ_LEGACY)
2755   NODE_NAME_CASE(RSQ_CLAMP)
2756   NODE_NAME_CASE(LDEXP)
2757   NODE_NAME_CASE(FP_CLASS)
2758   NODE_NAME_CASE(DOT4)
2759   NODE_NAME_CASE(CARRY)
2760   NODE_NAME_CASE(BORROW)
2761   NODE_NAME_CASE(BFE_U32)
2762   NODE_NAME_CASE(BFE_I32)
2763   NODE_NAME_CASE(BFI)
2764   NODE_NAME_CASE(BFM)
2765   NODE_NAME_CASE(FFBH_U32)
2766   NODE_NAME_CASE(MUL_U24)
2767   NODE_NAME_CASE(MUL_I24)
2768   NODE_NAME_CASE(MAD_U24)
2769   NODE_NAME_CASE(MAD_I24)
2770   NODE_NAME_CASE(TEXTURE_FETCH)
2771   NODE_NAME_CASE(EXPORT)
2772   NODE_NAME_CASE(CONST_ADDRESS)
2773   NODE_NAME_CASE(REGISTER_LOAD)
2774   NODE_NAME_CASE(REGISTER_STORE)
2775   NODE_NAME_CASE(LOAD_INPUT)
2776   NODE_NAME_CASE(SAMPLE)
2777   NODE_NAME_CASE(SAMPLEB)
2778   NODE_NAME_CASE(SAMPLED)
2779   NODE_NAME_CASE(SAMPLEL)
2780   NODE_NAME_CASE(CVT_F32_UBYTE0)
2781   NODE_NAME_CASE(CVT_F32_UBYTE1)
2782   NODE_NAME_CASE(CVT_F32_UBYTE2)
2783   NODE_NAME_CASE(CVT_F32_UBYTE3)
2784   NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2785   NODE_NAME_CASE(CONST_DATA_PTR)
2786   NODE_NAME_CASE(PC_ADD_REL_OFFSET)
2787   case AMDGPUISD::FIRST_MEM_OPCODE_NUMBER: break;
2788   NODE_NAME_CASE(SENDMSG)
2789   NODE_NAME_CASE(INTERP_MOV)
2790   NODE_NAME_CASE(INTERP_P1)
2791   NODE_NAME_CASE(INTERP_P2)
2792   NODE_NAME_CASE(STORE_MSKOR)
2793   NODE_NAME_CASE(LOAD_CONSTANT)
2794   NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2795   NODE_NAME_CASE(ATOMIC_CMP_SWAP)
2796   NODE_NAME_CASE(ATOMIC_INC)
2797   NODE_NAME_CASE(ATOMIC_DEC)
2798   case AMDGPUISD::LAST_AMDGPU_ISD_NUMBER: break;
2799   }
2800   return nullptr;
2801 }
2802 
2803 SDValue AMDGPUTargetLowering::getRsqrtEstimate(SDValue Operand,
2804                                                DAGCombinerInfo &DCI,
2805                                                unsigned &RefinementSteps,
2806                                                bool &UseOneConstNR) const {
2807   SelectionDAG &DAG = DCI.DAG;
2808   EVT VT = Operand.getValueType();
2809 
2810   if (VT == MVT::f32) {
2811     RefinementSteps = 0;
2812     return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand);
2813   }
2814 
2815   // TODO: There is also f64 rsq instruction, but the documentation is less
2816   // clear on its precision.
2817 
2818   return SDValue();
2819 }
2820 
2821 SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,
2822                                                DAGCombinerInfo &DCI,
2823                                                unsigned &RefinementSteps) const {
2824   SelectionDAG &DAG = DCI.DAG;
2825   EVT VT = Operand.getValueType();
2826 
2827   if (VT == MVT::f32) {
2828     // Reciprocal, < 1 ulp error.
2829     //
2830     // This reciprocal approximation converges to < 0.5 ulp error with one
2831     // newton rhapson performed with two fused multiple adds (FMAs).
2832 
2833     RefinementSteps = 0;
2834     return DAG.getNode(AMDGPUISD::RCP, SDLoc(Operand), VT, Operand);
2835   }
2836 
2837   // TODO: There is also f64 rcp instruction, but the documentation is less
2838   // clear on its precision.
2839 
2840   return SDValue();
2841 }
2842 
2843 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2844   const SDValue Op,
2845   APInt &KnownZero,
2846   APInt &KnownOne,
2847   const SelectionDAG &DAG,
2848   unsigned Depth) const {
2849 
2850   KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
2851 
2852   APInt KnownZero2;
2853   APInt KnownOne2;
2854   unsigned Opc = Op.getOpcode();
2855 
2856   switch (Opc) {
2857   default:
2858     break;
2859   case AMDGPUISD::CARRY:
2860   case AMDGPUISD::BORROW: {
2861     KnownZero = APInt::getHighBitsSet(32, 31);
2862     break;
2863   }
2864 
2865   case AMDGPUISD::BFE_I32:
2866   case AMDGPUISD::BFE_U32: {
2867     ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2868     if (!CWidth)
2869       return;
2870 
2871     unsigned BitWidth = 32;
2872     uint32_t Width = CWidth->getZExtValue() & 0x1f;
2873 
2874     if (Opc == AMDGPUISD::BFE_U32)
2875       KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2876 
2877     break;
2878   }
2879   }
2880 }
2881 
2882 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2883   SDValue Op,
2884   const SelectionDAG &DAG,
2885   unsigned Depth) const {
2886   switch (Op.getOpcode()) {
2887   case AMDGPUISD::BFE_I32: {
2888     ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2889     if (!Width)
2890       return 1;
2891 
2892     unsigned SignBits = 32 - Width->getZExtValue() + 1;
2893     if (!isNullConstant(Op.getOperand(1)))
2894       return SignBits;
2895 
2896     // TODO: Could probably figure something out with non-0 offsets.
2897     unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2898     return std::max(SignBits, Op0SignBits);
2899   }
2900 
2901   case AMDGPUISD::BFE_U32: {
2902     ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2903     return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;
2904   }
2905 
2906   case AMDGPUISD::CARRY:
2907   case AMDGPUISD::BORROW:
2908     return 31;
2909 
2910   default:
2911     return 1;
2912   }
2913 }
2914