1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief This is the parent TargetLowering class for hardware code gen
12 /// targets.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPUISelLowering.h"
17 #include "AMDGPU.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUIntrinsicInfo.h"
20 #include "AMDGPURegisterInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DiagnosticInfo.h"
31 #include "llvm/IR/DiagnosticPrinter.h"
32 
33 using namespace llvm;
34 
35 namespace {
36 
37 /// Diagnostic information for unimplemented or unsupported feature reporting.
38 class DiagnosticInfoUnsupported : public DiagnosticInfo {
39 private:
40   const Twine &Description;
41   const Function &Fn;
42 
43   static int KindID;
44 
45   static int getKindID() {
46     if (KindID == 0)
47       KindID = llvm::getNextAvailablePluginDiagnosticKind();
48     return KindID;
49   }
50 
51 public:
52   DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
53                           DiagnosticSeverity Severity = DS_Error)
54     : DiagnosticInfo(getKindID(), Severity),
55       Description(Desc),
56       Fn(Fn) { }
57 
58   const Function &getFunction() const { return Fn; }
59   const Twine &getDescription() const { return Description; }
60 
61   void print(DiagnosticPrinter &DP) const override {
62     DP << "unsupported " << getDescription() << " in " << Fn.getName();
63   }
64 
65   static bool classof(const DiagnosticInfo *DI) {
66     return DI->getKind() == getKindID();
67   }
68 };
69 
70 int DiagnosticInfoUnsupported::KindID = 0;
71 }
72 
73 
74 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
75                       CCValAssign::LocInfo LocInfo,
76                       ISD::ArgFlagsTy ArgFlags, CCState &State) {
77   unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
78                                         ArgFlags.getOrigAlign());
79   State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
80 
81   return true;
82 }
83 
84 #include "AMDGPUGenCallingConv.inc"
85 
86 // Find a larger type to do a load / store of a vector with.
87 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
88   unsigned StoreSize = VT.getStoreSizeInBits();
89   if (StoreSize <= 32)
90     return EVT::getIntegerVT(Ctx, StoreSize);
91 
92   assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
93   return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
94 }
95 
96 // Type for a vector that will be loaded to.
97 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
98   unsigned StoreSize = VT.getStoreSizeInBits();
99   if (StoreSize <= 32)
100     return EVT::getIntegerVT(Ctx, 32);
101 
102   return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
103 }
104 
105 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM,
106                                            const AMDGPUSubtarget &STI)
107     : TargetLowering(TM), Subtarget(&STI) {
108   setOperationAction(ISD::Constant, MVT::i32, Legal);
109   setOperationAction(ISD::Constant, MVT::i64, Legal);
110   setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
111   setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
112 
113   setOperationAction(ISD::BR_JT, MVT::Other, Expand);
114   setOperationAction(ISD::BRIND, MVT::Other, Expand);
115 
116   // This is totally unsupported, just custom lower to produce an error.
117   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
118 
119   // We need to custom lower some of the intrinsics
120   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
121 
122   // Library functions.  These default to Expand, but we have instructions
123   // for them.
124   setOperationAction(ISD::FCEIL,  MVT::f32, Legal);
125   setOperationAction(ISD::FEXP2,  MVT::f32, Legal);
126   setOperationAction(ISD::FPOW,   MVT::f32, Legal);
127   setOperationAction(ISD::FLOG2,  MVT::f32, Legal);
128   setOperationAction(ISD::FABS,   MVT::f32, Legal);
129   setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
130   setOperationAction(ISD::FRINT,  MVT::f32, Legal);
131   setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
132   setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
133   setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
134 
135   setOperationAction(ISD::FROUND, MVT::f32, Custom);
136   setOperationAction(ISD::FROUND, MVT::f64, Custom);
137 
138   setOperationAction(ISD::FREM, MVT::f32, Custom);
139   setOperationAction(ISD::FREM, MVT::f64, Custom);
140 
141   // v_mad_f32 does not support denormals according to some sources.
142   if (!Subtarget->hasFP32Denormals())
143     setOperationAction(ISD::FMAD, MVT::f32, Legal);
144 
145   // Expand to fneg + fadd.
146   setOperationAction(ISD::FSUB, MVT::f64, Expand);
147 
148   // Lower floating point store/load to integer store/load to reduce the number
149   // of patterns in tablegen.
150   setOperationAction(ISD::STORE, MVT::f32, Promote);
151   AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
152 
153   setOperationAction(ISD::STORE, MVT::v2f32, Promote);
154   AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
155 
156   setOperationAction(ISD::STORE, MVT::v4f32, Promote);
157   AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
158 
159   setOperationAction(ISD::STORE, MVT::v8f32, Promote);
160   AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
161 
162   setOperationAction(ISD::STORE, MVT::v16f32, Promote);
163   AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
164 
165   setOperationAction(ISD::STORE, MVT::f64, Promote);
166   AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
167 
168   setOperationAction(ISD::STORE, MVT::v2f64, Promote);
169   AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
170 
171   // Custom lowering of vector stores is required for local address space
172   // stores.
173   setOperationAction(ISD::STORE, MVT::v4i32, Custom);
174 
175   setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
176   setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
177   setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
178 
179   // XXX: This can be change to Custom, once ExpandVectorStores can
180   // handle 64-bit stores.
181   setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
182 
183   setTruncStoreAction(MVT::i64, MVT::i16, Expand);
184   setTruncStoreAction(MVT::i64, MVT::i8, Expand);
185   setTruncStoreAction(MVT::i64, MVT::i1, Expand);
186   setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
187   setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
188 
189 
190   setOperationAction(ISD::LOAD, MVT::f32, Promote);
191   AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
192 
193   setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
194   AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
195 
196   setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
197   AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
198 
199   setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
200   AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
201 
202   setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
203   AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
204 
205   setOperationAction(ISD::LOAD, MVT::f64, Promote);
206   AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
207 
208   setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
209   AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
210 
211   setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
212   setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
213   setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
214   setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
215   setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
216   setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
217   setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
218   setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
219   setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
220   setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
221 
222   // There are no 64-bit extloads. These should be done as a 32-bit extload and
223   // an extension to 64-bit.
224   for (MVT VT : MVT::integer_valuetypes()) {
225     setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand);
226     setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand);
227     setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand);
228   }
229 
230   for (MVT VT : MVT::integer_vector_valuetypes()) {
231     setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand);
232     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand);
233     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand);
234     setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand);
235     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand);
236     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand);
237     setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand);
238     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand);
239     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand);
240     setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand);
241     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand);
242     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand);
243   }
244 
245   setOperationAction(ISD::BR_CC, MVT::i1, Expand);
246 
247   if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
248     setOperationAction(ISD::FCEIL, MVT::f64, Custom);
249     setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
250     setOperationAction(ISD::FRINT, MVT::f64, Custom);
251     setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
252   }
253 
254   if (!Subtarget->hasBFI()) {
255     // fcopysign can be done in a single instruction with BFI.
256     setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
257     setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
258   }
259 
260   setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
261 
262   setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
263   setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
264   setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
265   setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, MVT::v8f16, Expand);
266 
267   setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
268   setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
269   setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
270   setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f16, Expand);
271 
272   setTruncStoreAction(MVT::f32, MVT::f16, Expand);
273   setTruncStoreAction(MVT::v2f32, MVT::v2f16, Expand);
274   setTruncStoreAction(MVT::v4f32, MVT::v4f16, Expand);
275   setTruncStoreAction(MVT::v8f32, MVT::v8f16, Expand);
276 
277   setTruncStoreAction(MVT::f64, MVT::f16, Expand);
278   setTruncStoreAction(MVT::f64, MVT::f32, Expand);
279 
280   const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
281   for (MVT VT : ScalarIntVTs) {
282     setOperationAction(ISD::SREM, VT, Expand);
283     setOperationAction(ISD::SDIV, VT, Expand);
284 
285     // GPU does not have divrem function for signed or unsigned.
286     setOperationAction(ISD::SDIVREM, VT, Custom);
287     setOperationAction(ISD::UDIVREM, VT, Custom);
288 
289     // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
290     setOperationAction(ISD::SMUL_LOHI, VT, Expand);
291     setOperationAction(ISD::UMUL_LOHI, VT, Expand);
292 
293     setOperationAction(ISD::BSWAP, VT, Expand);
294     setOperationAction(ISD::CTTZ, VT, Expand);
295     setOperationAction(ISD::CTLZ, VT, Expand);
296   }
297 
298   if (!Subtarget->hasBCNT(32))
299     setOperationAction(ISD::CTPOP, MVT::i32, Expand);
300 
301   if (!Subtarget->hasBCNT(64))
302     setOperationAction(ISD::CTPOP, MVT::i64, Expand);
303 
304   // The hardware supports 32-bit ROTR, but not ROTL.
305   setOperationAction(ISD::ROTL, MVT::i32, Expand);
306   setOperationAction(ISD::ROTL, MVT::i64, Expand);
307   setOperationAction(ISD::ROTR, MVT::i64, Expand);
308 
309   setOperationAction(ISD::MUL, MVT::i64, Expand);
310   setOperationAction(ISD::MULHU, MVT::i64, Expand);
311   setOperationAction(ISD::MULHS, MVT::i64, Expand);
312   setOperationAction(ISD::UDIV, MVT::i32, Expand);
313   setOperationAction(ISD::UREM, MVT::i32, Expand);
314   setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
315   setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
316   setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
317   setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
318   setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
319 
320   setOperationAction(ISD::SMIN, MVT::i32, Legal);
321   setOperationAction(ISD::UMIN, MVT::i32, Legal);
322   setOperationAction(ISD::SMAX, MVT::i32, Legal);
323   setOperationAction(ISD::UMAX, MVT::i32, Legal);
324 
325   if (!Subtarget->hasFFBH())
326     setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
327 
328   if (!Subtarget->hasFFBL())
329     setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
330 
331   static const MVT::SimpleValueType VectorIntTypes[] = {
332     MVT::v2i32, MVT::v4i32
333   };
334 
335   for (MVT VT : VectorIntTypes) {
336     // Expand the following operations for the current type by default.
337     setOperationAction(ISD::ADD,  VT, Expand);
338     setOperationAction(ISD::AND,  VT, Expand);
339     setOperationAction(ISD::FP_TO_SINT, VT, Expand);
340     setOperationAction(ISD::FP_TO_UINT, VT, Expand);
341     setOperationAction(ISD::MUL,  VT, Expand);
342     setOperationAction(ISD::OR,   VT, Expand);
343     setOperationAction(ISD::SHL,  VT, Expand);
344     setOperationAction(ISD::SRA,  VT, Expand);
345     setOperationAction(ISD::SRL,  VT, Expand);
346     setOperationAction(ISD::ROTL, VT, Expand);
347     setOperationAction(ISD::ROTR, VT, Expand);
348     setOperationAction(ISD::SUB,  VT, Expand);
349     setOperationAction(ISD::SINT_TO_FP, VT, Expand);
350     setOperationAction(ISD::UINT_TO_FP, VT, Expand);
351     setOperationAction(ISD::SDIV, VT, Expand);
352     setOperationAction(ISD::UDIV, VT, Expand);
353     setOperationAction(ISD::SREM, VT, Expand);
354     setOperationAction(ISD::UREM, VT, Expand);
355     setOperationAction(ISD::SMUL_LOHI, VT, Expand);
356     setOperationAction(ISD::UMUL_LOHI, VT, Expand);
357     setOperationAction(ISD::SDIVREM, VT, Custom);
358     setOperationAction(ISD::UDIVREM, VT, Custom);
359     setOperationAction(ISD::ADDC, VT, Expand);
360     setOperationAction(ISD::SUBC, VT, Expand);
361     setOperationAction(ISD::ADDE, VT, Expand);
362     setOperationAction(ISD::SUBE, VT, Expand);
363     setOperationAction(ISD::SELECT, VT, Expand);
364     setOperationAction(ISD::VSELECT, VT, Expand);
365     setOperationAction(ISD::SELECT_CC, VT, Expand);
366     setOperationAction(ISD::XOR,  VT, Expand);
367     setOperationAction(ISD::BSWAP, VT, Expand);
368     setOperationAction(ISD::CTPOP, VT, Expand);
369     setOperationAction(ISD::CTTZ, VT, Expand);
370     setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
371     setOperationAction(ISD::CTLZ, VT, Expand);
372     setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
373     setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
374   }
375 
376   static const MVT::SimpleValueType FloatVectorTypes[] = {
377     MVT::v2f32, MVT::v4f32
378   };
379 
380   for (MVT VT : FloatVectorTypes) {
381     setOperationAction(ISD::FABS, VT, Expand);
382     setOperationAction(ISD::FMINNUM, VT, Expand);
383     setOperationAction(ISD::FMAXNUM, VT, Expand);
384     setOperationAction(ISD::FADD, VT, Expand);
385     setOperationAction(ISD::FCEIL, VT, Expand);
386     setOperationAction(ISD::FCOS, VT, Expand);
387     setOperationAction(ISD::FDIV, VT, Expand);
388     setOperationAction(ISD::FEXP2, VT, Expand);
389     setOperationAction(ISD::FLOG2, VT, Expand);
390     setOperationAction(ISD::FREM, VT, Expand);
391     setOperationAction(ISD::FPOW, VT, Expand);
392     setOperationAction(ISD::FFLOOR, VT, Expand);
393     setOperationAction(ISD::FTRUNC, VT, Expand);
394     setOperationAction(ISD::FMUL, VT, Expand);
395     setOperationAction(ISD::FMA, VT, Expand);
396     setOperationAction(ISD::FRINT, VT, Expand);
397     setOperationAction(ISD::FNEARBYINT, VT, Expand);
398     setOperationAction(ISD::FSQRT, VT, Expand);
399     setOperationAction(ISD::FSIN, VT, Expand);
400     setOperationAction(ISD::FSUB, VT, Expand);
401     setOperationAction(ISD::FNEG, VT, Expand);
402     setOperationAction(ISD::SELECT, VT, Expand);
403     setOperationAction(ISD::VSELECT, VT, Expand);
404     setOperationAction(ISD::SELECT_CC, VT, Expand);
405     setOperationAction(ISD::FCOPYSIGN, VT, Expand);
406     setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
407   }
408 
409   setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
410   setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
411 
412   setTargetDAGCombine(ISD::SHL);
413   setTargetDAGCombine(ISD::MUL);
414   setTargetDAGCombine(ISD::SELECT);
415   setTargetDAGCombine(ISD::SELECT_CC);
416   setTargetDAGCombine(ISD::STORE);
417 
418   setTargetDAGCombine(ISD::FADD);
419   setTargetDAGCombine(ISD::FSUB);
420 
421   setBooleanContents(ZeroOrNegativeOneBooleanContent);
422   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
423 
424   setSchedulingPreference(Sched::RegPressure);
425   setJumpIsExpensive(true);
426 
427   // SI at least has hardware support for floating point exceptions, but no way
428   // of using or handling them is implemented. They are also optional in OpenCL
429   // (Section 7.3)
430   setHasFloatingPointExceptions(false);
431 
432   setSelectIsExpensive(false);
433   PredictableSelectIsExpensive = false;
434 
435   setFsqrtIsCheap(true);
436 
437   // FIXME: Need to really handle these.
438   MaxStoresPerMemcpy  = 4096;
439   MaxStoresPerMemmove = 4096;
440   MaxStoresPerMemset  = 4096;
441 }
442 
443 //===----------------------------------------------------------------------===//
444 // Target Information
445 //===----------------------------------------------------------------------===//
446 
447 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {
448   return MVT::i32;
449 }
450 
451 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
452   return true;
453 }
454 
455 // The backend supports 32 and 64 bit floating point immediates.
456 // FIXME: Why are we reporting vectors of FP immediates as legal?
457 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
458   EVT ScalarVT = VT.getScalarType();
459   return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
460 }
461 
462 // We don't want to shrink f64 / f32 constants.
463 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
464   EVT ScalarVT = VT.getScalarType();
465   return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
466 }
467 
468 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
469                                                  ISD::LoadExtType,
470                                                  EVT NewVT) const {
471 
472   unsigned NewSize = NewVT.getStoreSizeInBits();
473 
474   // If we are reducing to a 32-bit load, this is always better.
475   if (NewSize == 32)
476     return true;
477 
478   EVT OldVT = N->getValueType(0);
479   unsigned OldSize = OldVT.getStoreSizeInBits();
480 
481   // Don't produce extloads from sub 32-bit types. SI doesn't have scalar
482   // extloads, so doing one requires using a buffer_load. In cases where we
483   // still couldn't use a scalar load, using the wider load shouldn't really
484   // hurt anything.
485 
486   // If the old size already had to be an extload, there's no harm in continuing
487   // to reduce the width.
488   return (OldSize < 32);
489 }
490 
491 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
492                                                    EVT CastTy) const {
493   if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
494     return true;
495 
496   unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
497   unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
498 
499   return ((LScalarSize <= CastScalarSize) ||
500           (CastScalarSize >= 32) ||
501           (LScalarSize < 32));
502 }
503 
504 // SI+ has instructions for cttz / ctlz for 32-bit values. This is probably also
505 // profitable with the expansion for 64-bit since it's generally good to
506 // speculate things.
507 // FIXME: These should really have the size as a parameter.
508 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {
509   return true;
510 }
511 
512 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {
513   return true;
514 }
515 
516 //===---------------------------------------------------------------------===//
517 // Target Properties
518 //===---------------------------------------------------------------------===//
519 
520 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
521   assert(VT.isFloatingPoint());
522   return VT == MVT::f32 || VT == MVT::f64;
523 }
524 
525 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
526   assert(VT.isFloatingPoint());
527   return VT == MVT::f32 || VT == MVT::f64;
528 }
529 
530 bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(EVT MemVT,
531                                                          unsigned NumElem,
532                                                          unsigned AS) const {
533   return true;
534 }
535 
536 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
537   // Truncate is just accessing a subregister.
538   return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
539 }
540 
541 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
542   // Truncate is just accessing a subregister.
543   return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
544          (Dest->getPrimitiveSizeInBits() % 32 == 0);
545 }
546 
547 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
548   unsigned SrcSize = Src->getScalarSizeInBits();
549   unsigned DestSize = Dest->getScalarSizeInBits();
550 
551   return SrcSize == 32 && DestSize == 64;
552 }
553 
554 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
555   // Any register load of a 64-bit value really requires 2 32-bit moves. For all
556   // practical purposes, the extra mov 0 to load a 64-bit is free.  As used,
557   // this will enable reducing 64-bit operations the 32-bit, which is always
558   // good.
559   return Src == MVT::i32 && Dest == MVT::i64;
560 }
561 
562 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
563   return isZExtFree(Val.getValueType(), VT2);
564 }
565 
566 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
567   // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
568   // limited number of native 64-bit operations. Shrinking an operation to fit
569   // in a single 32-bit register should always be helpful. As currently used,
570   // this is much less general than the name suggests, and is only used in
571   // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
572   // not profitable, and may actually be harmful.
573   return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
574 }
575 
576 //===---------------------------------------------------------------------===//
577 // TargetLowering Callbacks
578 //===---------------------------------------------------------------------===//
579 
580 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
581                              const SmallVectorImpl<ISD::InputArg> &Ins) const {
582 
583   State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
584 }
585 
586 SDValue AMDGPUTargetLowering::LowerReturn(
587                                      SDValue Chain,
588                                      CallingConv::ID CallConv,
589                                      bool isVarArg,
590                                      const SmallVectorImpl<ISD::OutputArg> &Outs,
591                                      const SmallVectorImpl<SDValue> &OutVals,
592                                      SDLoc DL, SelectionDAG &DAG) const {
593   return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
594 }
595 
596 //===---------------------------------------------------------------------===//
597 // Target specific lowering
598 //===---------------------------------------------------------------------===//
599 
600 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
601                                         SmallVectorImpl<SDValue> &InVals) const {
602   SDValue Callee = CLI.Callee;
603   SelectionDAG &DAG = CLI.DAG;
604 
605   const Function &Fn = *DAG.getMachineFunction().getFunction();
606 
607   StringRef FuncName("<unknown>");
608 
609   if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
610     FuncName = G->getSymbol();
611   else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
612     FuncName = G->getGlobal()->getName();
613 
614   DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
615   DAG.getContext()->diagnose(NoCalls);
616   return SDValue();
617 }
618 
619 SDValue AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
620                                                       SelectionDAG &DAG) const {
621   const Function &Fn = *DAG.getMachineFunction().getFunction();
622 
623   DiagnosticInfoUnsupported NoDynamicAlloca(Fn, "dynamic alloca");
624   DAG.getContext()->diagnose(NoDynamicAlloca);
625   return SDValue();
626 }
627 
628 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
629                                              SelectionDAG &DAG) const {
630   switch (Op.getOpcode()) {
631   default:
632     Op.getNode()->dump();
633     llvm_unreachable("Custom lowering code for this"
634                      "instruction is not implemented yet!");
635     break;
636   case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
637   case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
638   case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
639   case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
640   case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
641   case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
642   case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
643   case ISD::FREM: return LowerFREM(Op, DAG);
644   case ISD::FCEIL: return LowerFCEIL(Op, DAG);
645   case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
646   case ISD::FRINT: return LowerFRINT(Op, DAG);
647   case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
648   case ISD::FROUND: return LowerFROUND(Op, DAG);
649   case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
650   case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
651   case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
652   case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
653   case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
654   case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
655   }
656   return Op;
657 }
658 
659 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
660                                               SmallVectorImpl<SDValue> &Results,
661                                               SelectionDAG &DAG) const {
662   switch (N->getOpcode()) {
663   case ISD::SIGN_EXTEND_INREG:
664     // Different parts of legalization seem to interpret which type of
665     // sign_extend_inreg is the one to check for custom lowering. The extended
666     // from type is what really matters, but some places check for custom
667     // lowering of the result type. This results in trying to use
668     // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
669     // nothing here and let the illegal result integer be handled normally.
670     return;
671   case ISD::LOAD: {
672     SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
673     if (!Node)
674       return;
675 
676     Results.push_back(SDValue(Node, 0));
677     Results.push_back(SDValue(Node, 1));
678     // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
679     // function
680     DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
681     return;
682   }
683   case ISD::STORE: {
684     SDValue Lowered = LowerSTORE(SDValue(N, 0), DAG);
685     if (Lowered.getNode())
686       Results.push_back(Lowered);
687     return;
688   }
689   default:
690     return;
691   }
692 }
693 
694 // FIXME: This implements accesses to initialized globals in the constant
695 // address space by copying them to private and accessing that. It does not
696 // properly handle illegal types or vectors. The private vector loads are not
697 // scalarized, and the illegal scalars hit an assertion. This technique will not
698 // work well with large initializers, and this should eventually be
699 // removed. Initialized globals should be placed into a data section that the
700 // runtime will load into a buffer before the kernel is executed. Uses of the
701 // global need to be replaced with a pointer loaded from an implicit kernel
702 // argument into this buffer holding the copy of the data, which will remove the
703 // need for any of this.
704 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
705                                                        const GlobalValue *GV,
706                                                        const SDValue &InitPtr,
707                                                        SDValue Chain,
708                                                        SelectionDAG &DAG) const {
709   const DataLayout &TD = DAG.getDataLayout();
710   SDLoc DL(InitPtr);
711   Type *InitTy = Init->getType();
712 
713   if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
714     EVT VT = EVT::getEVT(InitTy);
715     PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
716     return DAG.getStore(Chain, DL, DAG.getConstant(*CI, DL, VT), InitPtr,
717                         MachinePointerInfo(UndefValue::get(PtrTy)), false,
718                         false, TD.getPrefTypeAlignment(InitTy));
719   }
720 
721   if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
722     EVT VT = EVT::getEVT(CFP->getType());
723     PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
724     return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, DL, VT), InitPtr,
725                         MachinePointerInfo(UndefValue::get(PtrTy)), false,
726                         false, TD.getPrefTypeAlignment(CFP->getType()));
727   }
728 
729   if (StructType *ST = dyn_cast<StructType>(InitTy)) {
730     const StructLayout *SL = TD.getStructLayout(ST);
731 
732     EVT PtrVT = InitPtr.getValueType();
733     SmallVector<SDValue, 8> Chains;
734 
735     for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
736       SDValue Offset = DAG.getConstant(SL->getElementOffset(I), DL, PtrVT);
737       SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
738 
739       Constant *Elt = Init->getAggregateElement(I);
740       Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
741     }
742 
743     return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
744   }
745 
746   if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
747     EVT PtrVT = InitPtr.getValueType();
748 
749     unsigned NumElements;
750     if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
751       NumElements = AT->getNumElements();
752     else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
753       NumElements = VT->getNumElements();
754     else
755       llvm_unreachable("Unexpected type");
756 
757     unsigned EltSize = TD.getTypeAllocSize(SeqTy->getElementType());
758     SmallVector<SDValue, 8> Chains;
759     for (unsigned i = 0; i < NumElements; ++i) {
760       SDValue Offset = DAG.getConstant(i * EltSize, DL, PtrVT);
761       SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
762 
763       Constant *Elt = Init->getAggregateElement(i);
764       Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
765     }
766 
767     return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
768   }
769 
770   if (isa<UndefValue>(Init)) {
771     EVT VT = EVT::getEVT(InitTy);
772     PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
773     return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
774                         MachinePointerInfo(UndefValue::get(PtrTy)), false,
775                         false, TD.getPrefTypeAlignment(InitTy));
776   }
777 
778   Init->dump();
779   llvm_unreachable("Unhandled constant initializer");
780 }
781 
782 static bool hasDefinedInitializer(const GlobalValue *GV) {
783   const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
784   if (!GVar || !GVar->hasInitializer())
785     return false;
786 
787   if (isa<UndefValue>(GVar->getInitializer()))
788     return false;
789 
790   return true;
791 }
792 
793 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
794                                                  SDValue Op,
795                                                  SelectionDAG &DAG) const {
796 
797   const DataLayout &DL = DAG.getDataLayout();
798   GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
799   const GlobalValue *GV = G->getGlobal();
800 
801   switch (G->getAddressSpace()) {
802   case AMDGPUAS::LOCAL_ADDRESS: {
803     // XXX: What does the value of G->getOffset() mean?
804     assert(G->getOffset() == 0 &&
805          "Do not know what to do with an non-zero offset");
806 
807     // TODO: We could emit code to handle the initialization somewhere.
808     if (hasDefinedInitializer(GV))
809       break;
810 
811     unsigned Offset;
812     if (MFI->LocalMemoryObjects.count(GV) == 0) {
813       uint64_t Size = DL.getTypeAllocSize(GV->getType()->getElementType());
814       Offset = MFI->LDSSize;
815       MFI->LocalMemoryObjects[GV] = Offset;
816       // XXX: Account for alignment?
817       MFI->LDSSize += Size;
818     } else {
819       Offset = MFI->LocalMemoryObjects[GV];
820     }
821 
822     return DAG.getConstant(Offset, SDLoc(Op),
823                            getPointerTy(DL, AMDGPUAS::LOCAL_ADDRESS));
824   }
825   case AMDGPUAS::CONSTANT_ADDRESS: {
826     MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
827     Type *EltType = GV->getType()->getElementType();
828     unsigned Size = DL.getTypeAllocSize(EltType);
829     unsigned Alignment = DL.getPrefTypeAlignment(EltType);
830 
831     MVT PrivPtrVT = getPointerTy(DL, AMDGPUAS::PRIVATE_ADDRESS);
832     MVT ConstPtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
833 
834     int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
835     SDValue InitPtr = DAG.getFrameIndex(FI, PrivPtrVT);
836 
837     const GlobalVariable *Var = cast<GlobalVariable>(GV);
838     if (!Var->hasInitializer()) {
839       // This has no use, but bugpoint will hit it.
840       return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
841     }
842 
843     const Constant *Init = Var->getInitializer();
844     SmallVector<SDNode*, 8> WorkList;
845 
846     for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
847                               E = DAG.getEntryNode()->use_end(); I != E; ++I) {
848       if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
849         continue;
850       WorkList.push_back(*I);
851     }
852     SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
853     for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
854                                            E = WorkList.end(); I != E; ++I) {
855       SmallVector<SDValue, 8> Ops;
856       Ops.push_back(Chain);
857       for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
858         Ops.push_back((*I)->getOperand(i));
859       }
860       DAG.UpdateNodeOperands(*I, Ops);
861     }
862     return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
863   }
864   }
865 
866   const Function &Fn = *DAG.getMachineFunction().getFunction();
867   DiagnosticInfoUnsupported BadInit(Fn,
868                                     "initializer for address space");
869   DAG.getContext()->diagnose(BadInit);
870   return SDValue();
871 }
872 
873 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
874                                                   SelectionDAG &DAG) const {
875   SmallVector<SDValue, 8> Args;
876 
877   for (const SDUse &U : Op->ops())
878     DAG.ExtractVectorElements(U.get(), Args);
879 
880   return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
881 }
882 
883 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
884                                                      SelectionDAG &DAG) const {
885 
886   SmallVector<SDValue, 8> Args;
887   unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
888   EVT VT = Op.getValueType();
889   DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
890                             VT.getVectorNumElements());
891 
892   return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
893 }
894 
895 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
896                                               SelectionDAG &DAG) const {
897 
898   MachineFunction &MF = DAG.getMachineFunction();
899   const AMDGPUFrameLowering *TFL = Subtarget->getFrameLowering();
900 
901   FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
902 
903   unsigned FrameIndex = FIN->getIndex();
904   unsigned IgnoredFrameReg;
905   unsigned Offset =
906       TFL->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
907   return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), SDLoc(Op),
908                          Op.getValueType());
909 }
910 
911 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
912     SelectionDAG &DAG) const {
913   unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
914   SDLoc DL(Op);
915   EVT VT = Op.getValueType();
916 
917   switch (IntrinsicID) {
918     default: return Op;
919     case AMDGPUIntrinsic::AMDGPU_abs:
920     case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
921       return LowerIntrinsicIABS(Op, DAG);
922     case AMDGPUIntrinsic::AMDGPU_lrp:
923       return LowerIntrinsicLRP(Op, DAG);
924 
925     case AMDGPUIntrinsic::AMDGPU_clamp:
926     case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
927       return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
928                          Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
929 
930     case Intrinsic::AMDGPU_div_scale: {
931       // 3rd parameter required to be a constant.
932       const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
933       if (!Param)
934         return DAG.getUNDEF(VT);
935 
936       // Translate to the operands expected by the machine instruction. The
937       // first parameter must be the same as the first instruction.
938       SDValue Numerator = Op.getOperand(1);
939       SDValue Denominator = Op.getOperand(2);
940 
941       // Note this order is opposite of the machine instruction's operations,
942       // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The
943       // intrinsic has the numerator as the first operand to match a normal
944       // division operation.
945 
946       SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
947 
948       return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
949                          Denominator, Numerator);
950     }
951 
952     case Intrinsic::AMDGPU_div_fmas:
953       return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
954                          Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
955                          Op.getOperand(4));
956 
957     case Intrinsic::AMDGPU_div_fixup:
958       return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
959                          Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
960 
961     case Intrinsic::AMDGPU_trig_preop:
962       return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
963                          Op.getOperand(1), Op.getOperand(2));
964 
965     case Intrinsic::AMDGPU_rcp:
966       return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
967 
968     case Intrinsic::AMDGPU_rsq:
969       return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
970 
971     case AMDGPUIntrinsic::AMDGPU_legacy_rsq:
972       return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
973 
974     case Intrinsic::AMDGPU_rsq_clamped:
975       if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
976         Type *Type = VT.getTypeForEVT(*DAG.getContext());
977         APFloat Max = APFloat::getLargest(Type->getFltSemantics());
978         APFloat Min = APFloat::getLargest(Type->getFltSemantics(), true);
979 
980         SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
981         SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq,
982                                   DAG.getConstantFP(Max, DL, VT));
983         return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp,
984                            DAG.getConstantFP(Min, DL, VT));
985       } else {
986         return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1));
987       }
988 
989     case Intrinsic::AMDGPU_ldexp:
990       return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1),
991                                                    Op.getOperand(2));
992 
993     case AMDGPUIntrinsic::AMDGPU_imax:
994       return DAG.getNode(ISD::SMAX, DL, VT, Op.getOperand(1),
995                                             Op.getOperand(2));
996     case AMDGPUIntrinsic::AMDGPU_umax:
997       return DAG.getNode(ISD::UMAX, DL, VT, Op.getOperand(1),
998                                             Op.getOperand(2));
999     case AMDGPUIntrinsic::AMDGPU_imin:
1000       return DAG.getNode(ISD::SMIN, DL, VT, Op.getOperand(1),
1001                                             Op.getOperand(2));
1002     case AMDGPUIntrinsic::AMDGPU_umin:
1003       return DAG.getNode(ISD::UMIN, DL, VT, Op.getOperand(1),
1004                                             Op.getOperand(2));
1005 
1006     case AMDGPUIntrinsic::AMDGPU_umul24:
1007       return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
1008                          Op.getOperand(1), Op.getOperand(2));
1009 
1010     case AMDGPUIntrinsic::AMDGPU_imul24:
1011       return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
1012                          Op.getOperand(1), Op.getOperand(2));
1013 
1014     case AMDGPUIntrinsic::AMDGPU_umad24:
1015       return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
1016                          Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
1017 
1018     case AMDGPUIntrinsic::AMDGPU_imad24:
1019       return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
1020                          Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
1021 
1022     case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
1023       return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
1024 
1025     case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
1026       return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
1027 
1028     case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
1029       return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
1030 
1031     case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
1032       return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
1033 
1034     case AMDGPUIntrinsic::AMDGPU_bfe_i32:
1035       return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
1036                          Op.getOperand(1),
1037                          Op.getOperand(2),
1038                          Op.getOperand(3));
1039 
1040     case AMDGPUIntrinsic::AMDGPU_bfe_u32:
1041       return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
1042                          Op.getOperand(1),
1043                          Op.getOperand(2),
1044                          Op.getOperand(3));
1045 
1046     case AMDGPUIntrinsic::AMDGPU_bfi:
1047       return DAG.getNode(AMDGPUISD::BFI, DL, VT,
1048                          Op.getOperand(1),
1049                          Op.getOperand(2),
1050                          Op.getOperand(3));
1051 
1052     case AMDGPUIntrinsic::AMDGPU_bfm:
1053       return DAG.getNode(AMDGPUISD::BFM, DL, VT,
1054                          Op.getOperand(1),
1055                          Op.getOperand(2));
1056 
1057     case AMDGPUIntrinsic::AMDGPU_brev:
1058       return DAG.getNode(AMDGPUISD::BREV, DL, VT, Op.getOperand(1));
1059 
1060   case Intrinsic::AMDGPU_class:
1061     return DAG.getNode(AMDGPUISD::FP_CLASS, DL, VT,
1062                        Op.getOperand(1), Op.getOperand(2));
1063 
1064     case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
1065       return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
1066 
1067     case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
1068       return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
1069     case AMDGPUIntrinsic::AMDGPU_trunc: // Legacy name.
1070       return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1));
1071   }
1072 }
1073 
1074 ///IABS(a) = SMAX(sub(0, a), a)
1075 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
1076                                                  SelectionDAG &DAG) const {
1077   SDLoc DL(Op);
1078   EVT VT = Op.getValueType();
1079   SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1080                             Op.getOperand(1));
1081 
1082   return DAG.getNode(ISD::SMAX, DL, VT, Neg, Op.getOperand(1));
1083 }
1084 
1085 /// Linear Interpolation
1086 /// LRP(a, b, c) = muladd(a,  b, (1 - a) * c)
1087 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
1088                                                 SelectionDAG &DAG) const {
1089   SDLoc DL(Op);
1090   EVT VT = Op.getValueType();
1091   SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
1092                                 DAG.getConstantFP(1.0f, DL, MVT::f32),
1093                                 Op.getOperand(1));
1094   SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
1095                                                     Op.getOperand(3));
1096   return DAG.getNode(ISD::FADD, DL, VT,
1097       DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
1098       OneSubAC);
1099 }
1100 
1101 /// \brief Generate Min/Max node
1102 SDValue AMDGPUTargetLowering::CombineFMinMaxLegacy(SDLoc DL,
1103                                                    EVT VT,
1104                                                    SDValue LHS,
1105                                                    SDValue RHS,
1106                                                    SDValue True,
1107                                                    SDValue False,
1108                                                    SDValue CC,
1109                                                    DAGCombinerInfo &DCI) const {
1110   if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1111     return SDValue();
1112 
1113   if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1114     return SDValue();
1115 
1116   SelectionDAG &DAG = DCI.DAG;
1117   ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1118   switch (CCOpcode) {
1119   case ISD::SETOEQ:
1120   case ISD::SETONE:
1121   case ISD::SETUNE:
1122   case ISD::SETNE:
1123   case ISD::SETUEQ:
1124   case ISD::SETEQ:
1125   case ISD::SETFALSE:
1126   case ISD::SETFALSE2:
1127   case ISD::SETTRUE:
1128   case ISD::SETTRUE2:
1129   case ISD::SETUO:
1130   case ISD::SETO:
1131     break;
1132   case ISD::SETULE:
1133   case ISD::SETULT: {
1134     if (LHS == True)
1135       return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1136     return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1137   }
1138   case ISD::SETOLE:
1139   case ISD::SETOLT:
1140   case ISD::SETLE:
1141   case ISD::SETLT: {
1142     // Ordered. Assume ordered for undefined.
1143 
1144     // Only do this after legalization to avoid interfering with other combines
1145     // which might occur.
1146     if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1147         !DCI.isCalledByLegalizer())
1148       return SDValue();
1149 
1150     // We need to permute the operands to get the correct NaN behavior. The
1151     // selected operand is the second one based on the failing compare with NaN,
1152     // so permute it based on the compare type the hardware uses.
1153     if (LHS == True)
1154       return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1155     return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1156   }
1157   case ISD::SETUGE:
1158   case ISD::SETUGT: {
1159     if (LHS == True)
1160       return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1161     return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1162   }
1163   case ISD::SETGT:
1164   case ISD::SETGE:
1165   case ISD::SETOGE:
1166   case ISD::SETOGT: {
1167     if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1168         !DCI.isCalledByLegalizer())
1169       return SDValue();
1170 
1171     if (LHS == True)
1172       return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1173     return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1174   }
1175   case ISD::SETCC_INVALID:
1176     llvm_unreachable("Invalid setcc condcode!");
1177   }
1178   return SDValue();
1179 }
1180 
1181 SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
1182                                                   SelectionDAG &DAG) const {
1183   LoadSDNode *Load = cast<LoadSDNode>(Op);
1184   EVT MemVT = Load->getMemoryVT();
1185   EVT MemEltVT = MemVT.getVectorElementType();
1186 
1187   EVT LoadVT = Op.getValueType();
1188   EVT EltVT = LoadVT.getVectorElementType();
1189   EVT PtrVT = Load->getBasePtr().getValueType();
1190 
1191   unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
1192   SmallVector<SDValue, 8> Loads;
1193   SmallVector<SDValue, 8> Chains;
1194 
1195   SDLoc SL(Op);
1196   unsigned MemEltSize = MemEltVT.getStoreSize();
1197   MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1198 
1199   for (unsigned i = 0; i < NumElts; ++i) {
1200     SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
1201                               DAG.getConstant(i * MemEltSize, SL, PtrVT));
1202 
1203     SDValue NewLoad
1204       = DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
1205                        Load->getChain(), Ptr,
1206                        SrcValue.getWithOffset(i * MemEltSize),
1207                        MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
1208                        Load->isInvariant(), Load->getAlignment());
1209     Loads.push_back(NewLoad.getValue(0));
1210     Chains.push_back(NewLoad.getValue(1));
1211   }
1212 
1213   SDValue Ops[] = {
1214     DAG.getNode(ISD::BUILD_VECTOR, SL, LoadVT, Loads),
1215     DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains)
1216   };
1217 
1218   return DAG.getMergeValues(Ops, SL);
1219 }
1220 
1221 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1222                                               SelectionDAG &DAG) const {
1223   EVT VT = Op.getValueType();
1224 
1225   // If this is a 2 element vector, we really want to scalarize and not create
1226   // weird 1 element vectors.
1227   if (VT.getVectorNumElements() == 2)
1228     return ScalarizeVectorLoad(Op, DAG);
1229 
1230   LoadSDNode *Load = cast<LoadSDNode>(Op);
1231   SDValue BasePtr = Load->getBasePtr();
1232   EVT PtrVT = BasePtr.getValueType();
1233   EVT MemVT = Load->getMemoryVT();
1234   SDLoc SL(Op);
1235   MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1236 
1237   EVT LoVT, HiVT;
1238   EVT LoMemVT, HiMemVT;
1239   SDValue Lo, Hi;
1240 
1241   std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1242   std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1243   std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT);
1244   SDValue LoLoad
1245     = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1246                      Load->getChain(), BasePtr,
1247                      SrcValue,
1248                      LoMemVT, Load->isVolatile(), Load->isNonTemporal(),
1249                      Load->isInvariant(), Load->getAlignment());
1250 
1251   SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1252                               DAG.getConstant(LoMemVT.getStoreSize(), SL,
1253                                               PtrVT));
1254 
1255   SDValue HiLoad
1256     = DAG.getExtLoad(Load->getExtensionType(), SL, HiVT,
1257                      Load->getChain(), HiPtr,
1258                      SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1259                      HiMemVT, Load->isVolatile(), Load->isNonTemporal(),
1260                      Load->isInvariant(), Load->getAlignment());
1261 
1262   SDValue Ops[] = {
1263     DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),
1264     DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1265                 LoLoad.getValue(1), HiLoad.getValue(1))
1266   };
1267 
1268   return DAG.getMergeValues(Ops, SL);
1269 }
1270 
1271 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1272                                                SelectionDAG &DAG) const {
1273   StoreSDNode *Store = cast<StoreSDNode>(Op);
1274   EVT MemVT = Store->getMemoryVT();
1275   unsigned MemBits = MemVT.getSizeInBits();
1276 
1277   // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1278   // truncating store into an i32 store.
1279   // XXX: We could also handle optimize other vector bitwidths.
1280   if (!MemVT.isVector() || MemBits > 32) {
1281     return SDValue();
1282   }
1283 
1284   SDLoc DL(Op);
1285   SDValue Value = Store->getValue();
1286   EVT VT = Value.getValueType();
1287   EVT ElemVT = VT.getVectorElementType();
1288   SDValue Ptr = Store->getBasePtr();
1289   EVT MemEltVT = MemVT.getVectorElementType();
1290   unsigned MemEltBits = MemEltVT.getSizeInBits();
1291   unsigned MemNumElements = MemVT.getVectorNumElements();
1292   unsigned PackedSize = MemVT.getStoreSizeInBits();
1293   SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, DL, MVT::i32);
1294 
1295   assert(Value.getValueType().getScalarSizeInBits() >= 32);
1296 
1297   SDValue PackedValue;
1298   for (unsigned i = 0; i < MemNumElements; ++i) {
1299     SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1300                               DAG.getConstant(i, DL, MVT::i32));
1301     Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1302     Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1303 
1304     SDValue Shift = DAG.getConstant(MemEltBits * i, DL, MVT::i32);
1305     Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1306 
1307     if (i == 0) {
1308       PackedValue = Elt;
1309     } else {
1310       PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1311     }
1312   }
1313 
1314   if (PackedSize < 32) {
1315     EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1316     return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1317                              Store->getMemOperand()->getPointerInfo(),
1318                              PackedVT,
1319                              Store->isNonTemporal(), Store->isVolatile(),
1320                              Store->getAlignment());
1321   }
1322 
1323   return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1324                       Store->getMemOperand()->getPointerInfo(),
1325                       Store->isVolatile(),  Store->isNonTemporal(),
1326                       Store->getAlignment());
1327 }
1328 
1329 SDValue AMDGPUTargetLowering::ScalarizeVectorStore(SDValue Op,
1330                                                    SelectionDAG &DAG) const {
1331   StoreSDNode *Store = cast<StoreSDNode>(Op);
1332   EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1333   EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1334   EVT PtrVT = Store->getBasePtr().getValueType();
1335   unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1336   SDLoc SL(Op);
1337 
1338   SmallVector<SDValue, 8> Chains;
1339 
1340   unsigned EltSize = MemEltVT.getStoreSize();
1341   MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1342 
1343   for (unsigned i = 0, e = NumElts; i != e; ++i) {
1344     SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1345                               Store->getValue(),
1346                               DAG.getConstant(i, SL, MVT::i32));
1347 
1348     SDValue Offset = DAG.getConstant(i * MemEltVT.getStoreSize(), SL, PtrVT);
1349     SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Store->getBasePtr(), Offset);
1350     SDValue NewStore =
1351       DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1352                         SrcValue.getWithOffset(i * EltSize),
1353                         MemEltVT, Store->isNonTemporal(), Store->isVolatile(),
1354                         Store->getAlignment());
1355     Chains.push_back(NewStore);
1356   }
1357 
1358   return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1359 }
1360 
1361 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1362                                                SelectionDAG &DAG) const {
1363   StoreSDNode *Store = cast<StoreSDNode>(Op);
1364   SDValue Val = Store->getValue();
1365   EVT VT = Val.getValueType();
1366 
1367   // If this is a 2 element vector, we really want to scalarize and not create
1368   // weird 1 element vectors.
1369   if (VT.getVectorNumElements() == 2)
1370     return ScalarizeVectorStore(Op, DAG);
1371 
1372   EVT MemVT = Store->getMemoryVT();
1373   SDValue Chain = Store->getChain();
1374   SDValue BasePtr = Store->getBasePtr();
1375   SDLoc SL(Op);
1376 
1377   EVT LoVT, HiVT;
1378   EVT LoMemVT, HiMemVT;
1379   SDValue Lo, Hi;
1380 
1381   std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1382   std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1383   std::tie(Lo, Hi) = DAG.SplitVector(Val, SL, LoVT, HiVT);
1384 
1385   EVT PtrVT = BasePtr.getValueType();
1386   SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1387                               DAG.getConstant(LoMemVT.getStoreSize(), SL,
1388                                               PtrVT));
1389 
1390   MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1391   SDValue LoStore
1392     = DAG.getTruncStore(Chain, SL, Lo,
1393                         BasePtr,
1394                         SrcValue,
1395                         LoMemVT,
1396                         Store->isNonTemporal(),
1397                         Store->isVolatile(),
1398                         Store->getAlignment());
1399   SDValue HiStore
1400     = DAG.getTruncStore(Chain, SL, Hi,
1401                         HiPtr,
1402                         SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1403                         HiMemVT,
1404                         Store->isNonTemporal(),
1405                         Store->isVolatile(),
1406                         Store->getAlignment());
1407 
1408   return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1409 }
1410 
1411 
1412 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1413   SDLoc DL(Op);
1414   LoadSDNode *Load = cast<LoadSDNode>(Op);
1415   ISD::LoadExtType ExtType = Load->getExtensionType();
1416   EVT VT = Op.getValueType();
1417   EVT MemVT = Load->getMemoryVT();
1418 
1419   if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1420     assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1421     // FIXME: Copied from PPC
1422     // First, load into 32 bits, then truncate to 1 bit.
1423 
1424     SDValue Chain = Load->getChain();
1425     SDValue BasePtr = Load->getBasePtr();
1426     MachineMemOperand *MMO = Load->getMemOperand();
1427 
1428     SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1429                                    BasePtr, MVT::i8, MMO);
1430 
1431     SDValue Ops[] = {
1432       DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD),
1433       NewLD.getValue(1)
1434     };
1435 
1436     return DAG.getMergeValues(Ops, DL);
1437   }
1438 
1439   if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS ||
1440       Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1441       ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1442     return SDValue();
1443 
1444   // <SI && AS=PRIVATE && EXTLOAD && size < 32bit,
1445   // register (2-)byte extract.
1446 
1447   // Get Register holding the target.
1448   SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1449                             DAG.getConstant(2, DL, MVT::i32));
1450   // Load the Register.
1451   SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1452                             Load->getChain(), Ptr,
1453                             DAG.getTargetConstant(0, DL, MVT::i32),
1454                             Op.getOperand(2));
1455 
1456   // Get offset within the register.
1457   SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1458                                 Load->getBasePtr(),
1459                                 DAG.getConstant(0x3, DL, MVT::i32));
1460 
1461   // Bit offset of target byte (byteIdx * 8).
1462   SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1463                                  DAG.getConstant(3, DL, MVT::i32));
1464 
1465   // Shift to the right.
1466   Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1467 
1468   // Eliminate the upper bits by setting them to ...
1469   EVT MemEltVT = MemVT.getScalarType();
1470 
1471   // ... ones.
1472   if (ExtType == ISD::SEXTLOAD) {
1473     SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1474 
1475     SDValue Ops[] = {
1476       DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode),
1477       Load->getChain()
1478     };
1479 
1480     return DAG.getMergeValues(Ops, DL);
1481   }
1482 
1483   // ... or zeros.
1484   SDValue Ops[] = {
1485     DAG.getZeroExtendInReg(Ret, DL, MemEltVT),
1486     Load->getChain()
1487   };
1488 
1489   return DAG.getMergeValues(Ops, DL);
1490 }
1491 
1492 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1493   SDLoc DL(Op);
1494   SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1495   if (Result.getNode()) {
1496     return Result;
1497   }
1498 
1499   StoreSDNode *Store = cast<StoreSDNode>(Op);
1500   SDValue Chain = Store->getChain();
1501   if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1502        Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1503       Store->getValue().getValueType().isVector()) {
1504     return ScalarizeVectorStore(Op, DAG);
1505   }
1506 
1507   EVT MemVT = Store->getMemoryVT();
1508   if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1509       MemVT.bitsLT(MVT::i32)) {
1510     unsigned Mask = 0;
1511     if (Store->getMemoryVT() == MVT::i8) {
1512       Mask = 0xff;
1513     } else if (Store->getMemoryVT() == MVT::i16) {
1514       Mask = 0xffff;
1515     }
1516     SDValue BasePtr = Store->getBasePtr();
1517     SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1518                               DAG.getConstant(2, DL, MVT::i32));
1519     SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1520                               Chain, Ptr,
1521                               DAG.getTargetConstant(0, DL, MVT::i32));
1522 
1523     SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1524                                   DAG.getConstant(0x3, DL, MVT::i32));
1525 
1526     SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1527                                    DAG.getConstant(3, DL, MVT::i32));
1528 
1529     SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1530                                     Store->getValue());
1531 
1532     SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1533 
1534     SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1535                                        MaskedValue, ShiftAmt);
1536 
1537     SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32,
1538                                   DAG.getConstant(Mask, DL, MVT::i32),
1539                                   ShiftAmt);
1540     DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1541                           DAG.getConstant(0xffffffff, DL, MVT::i32));
1542     Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1543 
1544     SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1545     return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1546                        Chain, Value, Ptr,
1547                        DAG.getTargetConstant(0, DL, MVT::i32));
1548   }
1549   return SDValue();
1550 }
1551 
1552 // This is a shortcut for integer division because we have fast i32<->f32
1553 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1554 // float is enough to accurately represent up to a 24-bit integer.
1555 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const {
1556   SDLoc DL(Op);
1557   EVT VT = Op.getValueType();
1558   SDValue LHS = Op.getOperand(0);
1559   SDValue RHS = Op.getOperand(1);
1560   MVT IntVT = MVT::i32;
1561   MVT FltVT = MVT::f32;
1562 
1563   ISD::NodeType ToFp  = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1564   ISD::NodeType ToInt = sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1565 
1566   if (VT.isVector()) {
1567     unsigned NElts = VT.getVectorNumElements();
1568     IntVT = MVT::getVectorVT(MVT::i32, NElts);
1569     FltVT = MVT::getVectorVT(MVT::f32, NElts);
1570   }
1571 
1572   unsigned BitSize = VT.getScalarType().getSizeInBits();
1573 
1574   SDValue jq = DAG.getConstant(1, DL, IntVT);
1575 
1576   if (sign) {
1577     // char|short jq = ia ^ ib;
1578     jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1579 
1580     // jq = jq >> (bitsize - 2)
1581     jq = DAG.getNode(ISD::SRA, DL, VT, jq,
1582                      DAG.getConstant(BitSize - 2, DL, VT));
1583 
1584     // jq = jq | 0x1
1585     jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT));
1586 
1587     // jq = (int)jq
1588     jq = DAG.getSExtOrTrunc(jq, DL, IntVT);
1589   }
1590 
1591   // int ia = (int)LHS;
1592   SDValue ia = sign ?
1593     DAG.getSExtOrTrunc(LHS, DL, IntVT) : DAG.getZExtOrTrunc(LHS, DL, IntVT);
1594 
1595   // int ib, (int)RHS;
1596   SDValue ib = sign ?
1597     DAG.getSExtOrTrunc(RHS, DL, IntVT) : DAG.getZExtOrTrunc(RHS, DL, IntVT);
1598 
1599   // float fa = (float)ia;
1600   SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1601 
1602   // float fb = (float)ib;
1603   SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1604 
1605   // float fq = native_divide(fa, fb);
1606   SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1607                            fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1608 
1609   // fq = trunc(fq);
1610   fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1611 
1612   // float fqneg = -fq;
1613   SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1614 
1615   // float fr = mad(fqneg, fb, fa);
1616   SDValue fr = DAG.getNode(ISD::FADD, DL, FltVT,
1617                            DAG.getNode(ISD::FMUL, DL, FltVT, fqneg, fb), fa);
1618 
1619   // int iq = (int)fq;
1620   SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1621 
1622   // fr = fabs(fr);
1623   fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1624 
1625   // fb = fabs(fb);
1626   fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1627 
1628   EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
1629 
1630   // int cv = fr >= fb;
1631   SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1632 
1633   // jq = (cv ? jq : 0);
1634   jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, DL, VT));
1635 
1636   // dst = trunc/extend to legal type
1637   iq = sign ? DAG.getSExtOrTrunc(iq, DL, VT) : DAG.getZExtOrTrunc(iq, DL, VT);
1638 
1639   // dst = iq + jq;
1640   SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1641 
1642   // Rem needs compensation, it's easier to recompute it
1643   SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1644   Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1645 
1646   SDValue Res[2] = {
1647     Div,
1648     Rem
1649   };
1650   return DAG.getMergeValues(Res, DL);
1651 }
1652 
1653 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
1654                                       SelectionDAG &DAG,
1655                                       SmallVectorImpl<SDValue> &Results) const {
1656   assert(Op.getValueType() == MVT::i64);
1657 
1658   SDLoc DL(Op);
1659   EVT VT = Op.getValueType();
1660   EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1661 
1662   SDValue one = DAG.getConstant(1, DL, HalfVT);
1663   SDValue zero = DAG.getConstant(0, DL, HalfVT);
1664 
1665   //HiLo split
1666   SDValue LHS = Op.getOperand(0);
1667   SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);
1668   SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);
1669 
1670   SDValue RHS = Op.getOperand(1);
1671   SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);
1672   SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);
1673 
1674   if (VT == MVT::i64 &&
1675     DAG.MaskedValueIsZero(RHS, APInt::getHighBitsSet(64, 32)) &&
1676     DAG.MaskedValueIsZero(LHS, APInt::getHighBitsSet(64, 32))) {
1677 
1678     SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1679                               LHS_Lo, RHS_Lo);
1680 
1681     SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(0), zero);
1682     SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(1), zero);
1683     Results.push_back(DIV);
1684     Results.push_back(REM);
1685     return;
1686   }
1687 
1688   // Get Speculative values
1689   SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
1690   SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
1691 
1692   SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);
1693   SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, zero);
1694 
1695   SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);
1696   SDValue DIV_Lo = zero;
1697 
1698   const unsigned halfBitWidth = HalfVT.getSizeInBits();
1699 
1700   for (unsigned i = 0; i < halfBitWidth; ++i) {
1701     const unsigned bitPos = halfBitWidth - i - 1;
1702     SDValue POS = DAG.getConstant(bitPos, DL, HalfVT);
1703     // Get value of high bit
1704     SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
1705     HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
1706     HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit);
1707 
1708     // Shift
1709     REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT));
1710     // Add LHS high bit
1711     REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit);
1712 
1713     SDValue BIT = DAG.getConstant(1 << bitPos, DL, HalfVT);
1714     SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE);
1715 
1716     DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
1717 
1718     // Update REM
1719     SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
1720     REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
1721   }
1722 
1723   SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi);
1724   Results.push_back(DIV);
1725   Results.push_back(REM);
1726 }
1727 
1728 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1729                                            SelectionDAG &DAG) const {
1730   SDLoc DL(Op);
1731   EVT VT = Op.getValueType();
1732 
1733   if (VT == MVT::i64) {
1734     SmallVector<SDValue, 2> Results;
1735     LowerUDIVREM64(Op, DAG, Results);
1736     return DAG.getMergeValues(Results, DL);
1737   }
1738 
1739   SDValue Num = Op.getOperand(0);
1740   SDValue Den = Op.getOperand(1);
1741 
1742   if (VT == MVT::i32) {
1743     if (DAG.MaskedValueIsZero(Num, APInt::getHighBitsSet(32, 8)) &&
1744         DAG.MaskedValueIsZero(Den, APInt::getHighBitsSet(32, 8))) {
1745       // TODO: We technically could do this for i64, but shouldn't that just be
1746       // handled by something generally reducing 64-bit division on 32-bit
1747       // values to 32-bit?
1748       return LowerDIVREM24(Op, DAG, false);
1749     }
1750   }
1751 
1752   // RCP =  URECIP(Den) = 2^32 / Den + e
1753   // e is rounding error.
1754   SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1755 
1756   // RCP_LO = mul(RCP, Den) */
1757   SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1758 
1759   // RCP_HI = mulhu (RCP, Den) */
1760   SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1761 
1762   // NEG_RCP_LO = -RCP_LO
1763   SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1764                                                      RCP_LO);
1765 
1766   // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1767   SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1768                                            NEG_RCP_LO, RCP_LO,
1769                                            ISD::SETEQ);
1770   // Calculate the rounding error from the URECIP instruction
1771   // E = mulhu(ABS_RCP_LO, RCP)
1772   SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1773 
1774   // RCP_A_E = RCP + E
1775   SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1776 
1777   // RCP_S_E = RCP - E
1778   SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1779 
1780   // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1781   SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1782                                      RCP_A_E, RCP_S_E,
1783                                      ISD::SETEQ);
1784   // Quotient = mulhu(Tmp0, Num)
1785   SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1786 
1787   // Num_S_Remainder = Quotient * Den
1788   SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1789 
1790   // Remainder = Num - Num_S_Remainder
1791   SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1792 
1793   // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1794   SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1795                                                  DAG.getConstant(-1, DL, VT),
1796                                                  DAG.getConstant(0, DL, VT),
1797                                                  ISD::SETUGE);
1798   // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1799   SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1800                                                   Num_S_Remainder,
1801                                                   DAG.getConstant(-1, DL, VT),
1802                                                   DAG.getConstant(0, DL, VT),
1803                                                   ISD::SETUGE);
1804   // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1805   SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1806                                                Remainder_GE_Zero);
1807 
1808   // Calculate Division result:
1809 
1810   // Quotient_A_One = Quotient + 1
1811   SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1812                                        DAG.getConstant(1, DL, VT));
1813 
1814   // Quotient_S_One = Quotient - 1
1815   SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1816                                        DAG.getConstant(1, DL, VT));
1817 
1818   // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1819   SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1820                                      Quotient, Quotient_A_One, ISD::SETEQ);
1821 
1822   // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1823   Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1824                             Quotient_S_One, Div, ISD::SETEQ);
1825 
1826   // Calculate Rem result:
1827 
1828   // Remainder_S_Den = Remainder - Den
1829   SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1830 
1831   // Remainder_A_Den = Remainder + Den
1832   SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1833 
1834   // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1835   SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1836                                     Remainder, Remainder_S_Den, ISD::SETEQ);
1837 
1838   // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1839   Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1840                             Remainder_A_Den, Rem, ISD::SETEQ);
1841   SDValue Ops[2] = {
1842     Div,
1843     Rem
1844   };
1845   return DAG.getMergeValues(Ops, DL);
1846 }
1847 
1848 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1849                                            SelectionDAG &DAG) const {
1850   SDLoc DL(Op);
1851   EVT VT = Op.getValueType();
1852 
1853   SDValue LHS = Op.getOperand(0);
1854   SDValue RHS = Op.getOperand(1);
1855 
1856   SDValue Zero = DAG.getConstant(0, DL, VT);
1857   SDValue NegOne = DAG.getConstant(-1, DL, VT);
1858 
1859   if (VT == MVT::i32 &&
1860       DAG.ComputeNumSignBits(LHS) > 8 &&
1861       DAG.ComputeNumSignBits(RHS) > 8) {
1862     return LowerDIVREM24(Op, DAG, true);
1863   }
1864   if (VT == MVT::i64 &&
1865       DAG.ComputeNumSignBits(LHS) > 32 &&
1866       DAG.ComputeNumSignBits(RHS) > 32) {
1867     EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1868 
1869     //HiLo split
1870     SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1871     SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1872     SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1873                                  LHS_Lo, RHS_Lo);
1874     SDValue Res[2] = {
1875       DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)),
1876       DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1))
1877     };
1878     return DAG.getMergeValues(Res, DL);
1879   }
1880 
1881   SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1882   SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1883   SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1884   SDValue RSign = LHSign; // Remainder sign is the same as LHS
1885 
1886   LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1887   RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1888 
1889   LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1890   RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1891 
1892   SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1893   SDValue Rem = Div.getValue(1);
1894 
1895   Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1896   Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1897 
1898   Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1899   Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1900 
1901   SDValue Res[2] = {
1902     Div,
1903     Rem
1904   };
1905   return DAG.getMergeValues(Res, DL);
1906 }
1907 
1908 // (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
1909 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
1910   SDLoc SL(Op);
1911   EVT VT = Op.getValueType();
1912   SDValue X = Op.getOperand(0);
1913   SDValue Y = Op.getOperand(1);
1914 
1915   SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
1916   SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
1917   SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
1918 
1919   return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
1920 }
1921 
1922 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1923   SDLoc SL(Op);
1924   SDValue Src = Op.getOperand(0);
1925 
1926   // result = trunc(src)
1927   // if (src > 0.0 && src != result)
1928   //   result += 1.0
1929 
1930   SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1931 
1932   const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
1933   const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
1934 
1935   EVT SetCCVT =
1936       getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
1937 
1938   SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1939   SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1940   SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1941 
1942   SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1943   return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1944 }
1945 
1946 static SDValue extractF64Exponent(SDValue Hi, SDLoc SL, SelectionDAG &DAG) {
1947   const unsigned FractBits = 52;
1948   const unsigned ExpBits = 11;
1949 
1950   SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
1951                                 Hi,
1952                                 DAG.getConstant(FractBits - 32, SL, MVT::i32),
1953                                 DAG.getConstant(ExpBits, SL, MVT::i32));
1954   SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1955                             DAG.getConstant(1023, SL, MVT::i32));
1956 
1957   return Exp;
1958 }
1959 
1960 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1961   SDLoc SL(Op);
1962   SDValue Src = Op.getOperand(0);
1963 
1964   assert(Op.getValueType() == MVT::f64);
1965 
1966   const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1967   const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1968 
1969   SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1970 
1971   // Extract the upper half, since this is where we will find the sign and
1972   // exponent.
1973   SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1974 
1975   SDValue Exp = extractF64Exponent(Hi, SL, DAG);
1976 
1977   const unsigned FractBits = 52;
1978 
1979   // Extract the sign bit.
1980   const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, SL, MVT::i32);
1981   SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
1982 
1983   // Extend back to to 64-bits.
1984   SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
1985                                   Zero, SignBit);
1986   SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
1987 
1988   SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
1989   const SDValue FractMask
1990     = DAG.getConstant((UINT64_C(1) << FractBits) - 1, SL, MVT::i64);
1991 
1992   SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
1993   SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
1994   SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
1995 
1996   EVT SetCCVT =
1997       getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
1998 
1999   const SDValue FiftyOne = DAG.getConstant(FractBits - 1, SL, MVT::i32);
2000 
2001   SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2002   SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2003 
2004   SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
2005   SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
2006 
2007   return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
2008 }
2009 
2010 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
2011   SDLoc SL(Op);
2012   SDValue Src = Op.getOperand(0);
2013 
2014   assert(Op.getValueType() == MVT::f64);
2015 
2016   APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
2017   SDValue C1 = DAG.getConstantFP(C1Val, SL, MVT::f64);
2018   SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
2019 
2020   SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
2021   SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
2022 
2023   SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
2024 
2025   APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
2026   SDValue C2 = DAG.getConstantFP(C2Val, SL, MVT::f64);
2027 
2028   EVT SetCCVT =
2029       getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2030   SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
2031 
2032   return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
2033 }
2034 
2035 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
2036   // FNEARBYINT and FRINT are the same, except in their handling of FP
2037   // exceptions. Those aren't really meaningful for us, and OpenCL only has
2038   // rint, so just treat them as equivalent.
2039   return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
2040 }
2041 
2042 // XXX - May require not supporting f32 denormals?
2043 SDValue AMDGPUTargetLowering::LowerFROUND32(SDValue Op, SelectionDAG &DAG) const {
2044   SDLoc SL(Op);
2045   SDValue X = Op.getOperand(0);
2046 
2047   SDValue T = DAG.getNode(ISD::FTRUNC, SL, MVT::f32, X);
2048 
2049   SDValue Diff = DAG.getNode(ISD::FSUB, SL, MVT::f32, X, T);
2050 
2051   SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, MVT::f32, Diff);
2052 
2053   const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f32);
2054   const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
2055   const SDValue Half = DAG.getConstantFP(0.5, SL, MVT::f32);
2056 
2057   SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f32, One, X);
2058 
2059   EVT SetCCVT =
2060       getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32);
2061 
2062   SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE);
2063 
2064   SDValue Sel = DAG.getNode(ISD::SELECT, SL, MVT::f32, Cmp, SignOne, Zero);
2065 
2066   return DAG.getNode(ISD::FADD, SL, MVT::f32, T, Sel);
2067 }
2068 
2069 SDValue AMDGPUTargetLowering::LowerFROUND64(SDValue Op, SelectionDAG &DAG) const {
2070   SDLoc SL(Op);
2071   SDValue X = Op.getOperand(0);
2072 
2073   SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X);
2074 
2075   const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2076   const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2077   const SDValue NegOne = DAG.getConstant(-1, SL, MVT::i32);
2078   const SDValue FiftyOne = DAG.getConstant(51, SL, MVT::i32);
2079   EVT SetCCVT =
2080       getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
2081 
2082   SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
2083 
2084   SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One);
2085 
2086   SDValue Exp = extractF64Exponent(Hi, SL, DAG);
2087 
2088   const SDValue Mask = DAG.getConstant(INT64_C(0x000fffffffffffff), SL,
2089                                        MVT::i64);
2090 
2091   SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp);
2092   SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64,
2093                           DAG.getConstant(INT64_C(0x0008000000000000), SL,
2094                                           MVT::i64),
2095                           Exp);
2096 
2097   SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M);
2098   SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT,
2099                               DAG.getConstant(0, SL, MVT::i64), Tmp0,
2100                               ISD::SETNE);
2101 
2102   SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1,
2103                              D, DAG.getConstant(0, SL, MVT::i64));
2104   SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2);
2105 
2106   K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64));
2107   K = DAG.getNode(ISD::BITCAST, SL, MVT::f64, K);
2108 
2109   SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2110   SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2111   SDValue ExpEqNegOne = DAG.getSetCC(SL, SetCCVT, NegOne, Exp, ISD::SETEQ);
2112 
2113   SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64,
2114                             ExpEqNegOne,
2115                             DAG.getConstantFP(1.0, SL, MVT::f64),
2116                             DAG.getConstantFP(0.0, SL, MVT::f64));
2117 
2118   SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X);
2119 
2120   K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpLt0, S, K);
2121   K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpGt51, X, K);
2122 
2123   return K;
2124 }
2125 
2126 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
2127   EVT VT = Op.getValueType();
2128 
2129   if (VT == MVT::f32)
2130     return LowerFROUND32(Op, DAG);
2131 
2132   if (VT == MVT::f64)
2133     return LowerFROUND64(Op, DAG);
2134 
2135   llvm_unreachable("unhandled type");
2136 }
2137 
2138 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
2139   SDLoc SL(Op);
2140   SDValue Src = Op.getOperand(0);
2141 
2142   // result = trunc(src);
2143   // if (src < 0.0 && src != result)
2144   //   result += -1.0.
2145 
2146   SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2147 
2148   const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
2149   const SDValue NegOne = DAG.getConstantFP(-1.0, SL, MVT::f64);
2150 
2151   EVT SetCCVT =
2152       getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2153 
2154   SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
2155   SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
2156   SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2157 
2158   SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
2159   return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2160 }
2161 
2162 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
2163                                                bool Signed) const {
2164   SDLoc SL(Op);
2165   SDValue Src = Op.getOperand(0);
2166 
2167   SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2168 
2169   SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2170                            DAG.getConstant(0, SL, MVT::i32));
2171   SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2172                            DAG.getConstant(1, SL, MVT::i32));
2173 
2174   SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
2175                               SL, MVT::f64, Hi);
2176 
2177   SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
2178 
2179   SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
2180                               DAG.getConstant(32, SL, MVT::i32));
2181 
2182   return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
2183 }
2184 
2185 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
2186                                                SelectionDAG &DAG) const {
2187   SDValue S0 = Op.getOperand(0);
2188   if (S0.getValueType() != MVT::i64)
2189     return SDValue();
2190 
2191   EVT DestVT = Op.getValueType();
2192   if (DestVT == MVT::f64)
2193     return LowerINT_TO_FP64(Op, DAG, false);
2194 
2195   assert(DestVT == MVT::f32);
2196 
2197   SDLoc DL(Op);
2198 
2199   // f32 uint_to_fp i64
2200   SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2201                            DAG.getConstant(0, DL, MVT::i32));
2202   SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
2203   SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2204                            DAG.getConstant(1, DL, MVT::i32));
2205   SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
2206   FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
2207                         DAG.getConstantFP(4294967296.0f, DL, MVT::f32)); // 2^32
2208   return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
2209 }
2210 
2211 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
2212                                               SelectionDAG &DAG) const {
2213   SDValue Src = Op.getOperand(0);
2214   if (Src.getValueType() == MVT::i64 && Op.getValueType() == MVT::f64)
2215     return LowerINT_TO_FP64(Op, DAG, true);
2216 
2217   return SDValue();
2218 }
2219 
2220 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
2221                                                bool Signed) const {
2222   SDLoc SL(Op);
2223 
2224   SDValue Src = Op.getOperand(0);
2225 
2226   SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2227 
2228   SDValue K0 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), SL,
2229                                  MVT::f64);
2230   SDValue K1 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), SL,
2231                                  MVT::f64);
2232 
2233   SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
2234 
2235   SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
2236 
2237 
2238   SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
2239 
2240   SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
2241                            MVT::i32, FloorMul);
2242   SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
2243 
2244   SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Lo, Hi);
2245 
2246   return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
2247 }
2248 
2249 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
2250                                               SelectionDAG &DAG) const {
2251   SDValue Src = Op.getOperand(0);
2252 
2253   if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2254     return LowerFP64_TO_INT(Op, DAG, true);
2255 
2256   return SDValue();
2257 }
2258 
2259 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
2260                                               SelectionDAG &DAG) const {
2261   SDValue Src = Op.getOperand(0);
2262 
2263   if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2264     return LowerFP64_TO_INT(Op, DAG, false);
2265 
2266   return SDValue();
2267 }
2268 
2269 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
2270                                                      SelectionDAG &DAG) const {
2271   EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
2272   MVT VT = Op.getSimpleValueType();
2273   MVT ScalarVT = VT.getScalarType();
2274 
2275   if (!VT.isVector())
2276     return SDValue();
2277 
2278   SDValue Src = Op.getOperand(0);
2279   SDLoc DL(Op);
2280 
2281   // TODO: Don't scalarize on Evergreen?
2282   unsigned NElts = VT.getVectorNumElements();
2283   SmallVector<SDValue, 8> Args;
2284   DAG.ExtractVectorElements(Src, Args, 0, NElts);
2285 
2286   SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
2287   for (unsigned I = 0; I < NElts; ++I)
2288     Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
2289 
2290   return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
2291 }
2292 
2293 //===----------------------------------------------------------------------===//
2294 // Custom DAG optimizations
2295 //===----------------------------------------------------------------------===//
2296 
2297 static bool isU24(SDValue Op, SelectionDAG &DAG) {
2298   APInt KnownZero, KnownOne;
2299   EVT VT = Op.getValueType();
2300   DAG.computeKnownBits(Op, KnownZero, KnownOne);
2301 
2302   return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
2303 }
2304 
2305 static bool isI24(SDValue Op, SelectionDAG &DAG) {
2306   EVT VT = Op.getValueType();
2307 
2308   // In order for this to be a signed 24-bit value, bit 23, must
2309   // be a sign bit.
2310   return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
2311                                      // as unsigned 24-bit values.
2312          (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
2313 }
2314 
2315 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
2316 
2317   SelectionDAG &DAG = DCI.DAG;
2318   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2319   EVT VT = Op.getValueType();
2320 
2321   APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
2322   APInt KnownZero, KnownOne;
2323   TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
2324   if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
2325     DCI.CommitTargetLoweringOpt(TLO);
2326 }
2327 
2328 template <typename IntTy>
2329 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
2330                                uint32_t Offset, uint32_t Width, SDLoc DL) {
2331   if (Width + Offset < 32) {
2332     uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2333     IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2334     return DAG.getConstant(Result, DL, MVT::i32);
2335   }
2336 
2337   return DAG.getConstant(Src0 >> Offset, DL, MVT::i32);
2338 }
2339 
2340 static bool usesAllNormalStores(SDNode *LoadVal) {
2341   for (SDNode::use_iterator I = LoadVal->use_begin(); !I.atEnd(); ++I) {
2342     if (!ISD::isNormalStore(*I))
2343       return false;
2344   }
2345 
2346   return true;
2347 }
2348 
2349 // If we have a copy of an illegal type, replace it with a load / store of an
2350 // equivalently sized legal type. This avoids intermediate bit pack / unpack
2351 // instructions emitted when handling extloads and truncstores. Ideally we could
2352 // recognize the pack / unpack pattern to eliminate it.
2353 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2354                                                   DAGCombinerInfo &DCI) const {
2355   if (!DCI.isBeforeLegalize())
2356     return SDValue();
2357 
2358   StoreSDNode *SN = cast<StoreSDNode>(N);
2359   SDValue Value = SN->getValue();
2360   EVT VT = Value.getValueType();
2361 
2362   if (isTypeLegal(VT) || SN->isVolatile() ||
2363       !ISD::isNormalLoad(Value.getNode()) || VT.getSizeInBits() < 8)
2364     return SDValue();
2365 
2366   LoadSDNode *LoadVal = cast<LoadSDNode>(Value);
2367   if (LoadVal->isVolatile() || !usesAllNormalStores(LoadVal))
2368     return SDValue();
2369 
2370   EVT MemVT = LoadVal->getMemoryVT();
2371 
2372   SDLoc SL(N);
2373   SelectionDAG &DAG = DCI.DAG;
2374   EVT LoadVT = getEquivalentMemType(*DAG.getContext(), MemVT);
2375 
2376   SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
2377                                 LoadVT, SL,
2378                                 LoadVal->getChain(),
2379                                 LoadVal->getBasePtr(),
2380                                 LoadVal->getOffset(),
2381                                 LoadVT,
2382                                 LoadVal->getMemOperand());
2383 
2384   SDValue CastLoad = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad.getValue(0));
2385   DCI.CombineTo(LoadVal, CastLoad, NewLoad.getValue(1), false);
2386 
2387   return DAG.getStore(SN->getChain(), SL, NewLoad,
2388                       SN->getBasePtr(), SN->getMemOperand());
2389 }
2390 
2391 SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
2392                                                 DAGCombinerInfo &DCI) const {
2393   if (N->getValueType(0) != MVT::i64)
2394     return SDValue();
2395 
2396   // i64 (shl x, 32) -> (build_pair 0, x)
2397 
2398   // Doing this with moves theoretically helps MI optimizations that understand
2399   // copies. 2 v_mov_b32_e32 will have the same code size / cycle count as
2400   // v_lshl_b64. In the SALU case, I think this is slightly worse since it
2401   // doubles the code size and I'm unsure about cycle count.
2402   const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
2403   if (!RHS || RHS->getZExtValue() != 32)
2404     return SDValue();
2405 
2406   SDValue LHS = N->getOperand(0);
2407 
2408   SDLoc SL(N);
2409   SelectionDAG &DAG = DCI.DAG;
2410 
2411   // Extract low 32-bits.
2412   SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS);
2413 
2414   const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2415   return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64, Zero, Lo);
2416 }
2417 
2418 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
2419                                                 DAGCombinerInfo &DCI) const {
2420   EVT VT = N->getValueType(0);
2421 
2422   if (VT.isVector() || VT.getSizeInBits() > 32)
2423     return SDValue();
2424 
2425   SelectionDAG &DAG = DCI.DAG;
2426   SDLoc DL(N);
2427 
2428   SDValue N0 = N->getOperand(0);
2429   SDValue N1 = N->getOperand(1);
2430   SDValue Mul;
2431 
2432   if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
2433     N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
2434     N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
2435     Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
2436   } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
2437     N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
2438     N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
2439     Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
2440   } else {
2441     return SDValue();
2442   }
2443 
2444   // We need to use sext even for MUL_U24, because MUL_U24 is used
2445   // for signed multiply of 8 and 16-bit types.
2446   return DAG.getSExtOrTrunc(Mul, DL, VT);
2447 }
2448 
2449 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
2450                                                 DAGCombinerInfo &DCI) const {
2451   SelectionDAG &DAG = DCI.DAG;
2452   SDLoc DL(N);
2453 
2454   switch(N->getOpcode()) {
2455   default:
2456     break;
2457   case ISD::SHL: {
2458     if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
2459       break;
2460 
2461     return performShlCombine(N, DCI);
2462   }
2463   case ISD::MUL:
2464     return performMulCombine(N, DCI);
2465   case AMDGPUISD::MUL_I24:
2466   case AMDGPUISD::MUL_U24: {
2467     SDValue N0 = N->getOperand(0);
2468     SDValue N1 = N->getOperand(1);
2469     simplifyI24(N0, DCI);
2470     simplifyI24(N1, DCI);
2471     return SDValue();
2472   }
2473   case ISD::SELECT: {
2474     SDValue Cond = N->getOperand(0);
2475     if (Cond.getOpcode() == ISD::SETCC && Cond.hasOneUse()) {
2476       EVT VT = N->getValueType(0);
2477       SDValue LHS = Cond.getOperand(0);
2478       SDValue RHS = Cond.getOperand(1);
2479       SDValue CC = Cond.getOperand(2);
2480 
2481       SDValue True = N->getOperand(1);
2482       SDValue False = N->getOperand(2);
2483 
2484       if (VT == MVT::f32)
2485         return CombineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI);
2486     }
2487 
2488     break;
2489   }
2490   case AMDGPUISD::BFE_I32:
2491   case AMDGPUISD::BFE_U32: {
2492     assert(!N->getValueType(0).isVector() &&
2493            "Vector handling of BFE not implemented");
2494     ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
2495     if (!Width)
2496       break;
2497 
2498     uint32_t WidthVal = Width->getZExtValue() & 0x1f;
2499     if (WidthVal == 0)
2500       return DAG.getConstant(0, DL, MVT::i32);
2501 
2502     ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2503     if (!Offset)
2504       break;
2505 
2506     SDValue BitsFrom = N->getOperand(0);
2507     uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
2508 
2509     bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
2510 
2511     if (OffsetVal == 0) {
2512       // This is already sign / zero extended, so try to fold away extra BFEs.
2513       unsigned SignBits =  Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
2514 
2515       unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
2516       if (OpSignBits >= SignBits)
2517         return BitsFrom;
2518 
2519       EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
2520       if (Signed) {
2521         // This is a sign_extend_inreg. Replace it to take advantage of existing
2522         // DAG Combines. If not eliminated, we will match back to BFE during
2523         // selection.
2524 
2525         // TODO: The sext_inreg of extended types ends, although we can could
2526         // handle them in a single BFE.
2527         return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
2528                            DAG.getValueType(SmallVT));
2529       }
2530 
2531       return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
2532     }
2533 
2534     if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
2535       if (Signed) {
2536         return constantFoldBFE<int32_t>(DAG,
2537                                         CVal->getSExtValue(),
2538                                         OffsetVal,
2539                                         WidthVal,
2540                                         DL);
2541       }
2542 
2543       return constantFoldBFE<uint32_t>(DAG,
2544                                        CVal->getZExtValue(),
2545                                        OffsetVal,
2546                                        WidthVal,
2547                                        DL);
2548     }
2549 
2550     if ((OffsetVal + WidthVal) >= 32) {
2551       SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32);
2552       return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2553                          BitsFrom, ShiftVal);
2554     }
2555 
2556     if (BitsFrom.hasOneUse()) {
2557       APInt Demanded = APInt::getBitsSet(32,
2558                                          OffsetVal,
2559                                          OffsetVal + WidthVal);
2560 
2561       APInt KnownZero, KnownOne;
2562       TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2563                                             !DCI.isBeforeLegalizeOps());
2564       const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2565       if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
2566           TLI.SimplifyDemandedBits(BitsFrom, Demanded,
2567                                    KnownZero, KnownOne, TLO)) {
2568         DCI.CommitTargetLoweringOpt(TLO);
2569       }
2570     }
2571 
2572     break;
2573   }
2574 
2575   case ISD::STORE:
2576     return performStoreCombine(N, DCI);
2577   }
2578   return SDValue();
2579 }
2580 
2581 //===----------------------------------------------------------------------===//
2582 // Helper functions
2583 //===----------------------------------------------------------------------===//
2584 
2585 void AMDGPUTargetLowering::getOriginalFunctionArgs(
2586                                SelectionDAG &DAG,
2587                                const Function *F,
2588                                const SmallVectorImpl<ISD::InputArg> &Ins,
2589                                SmallVectorImpl<ISD::InputArg> &OrigIns) const {
2590 
2591   for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
2592     if (Ins[i].ArgVT == Ins[i].VT) {
2593       OrigIns.push_back(Ins[i]);
2594       continue;
2595     }
2596 
2597     EVT VT;
2598     if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2599       // Vector has been split into scalars.
2600       VT = Ins[i].ArgVT.getVectorElementType();
2601     } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
2602                Ins[i].ArgVT.getVectorElementType() !=
2603                Ins[i].VT.getVectorElementType()) {
2604       // Vector elements have been promoted
2605       VT = Ins[i].ArgVT;
2606     } else {
2607       // Vector has been spilt into smaller vectors.
2608       VT = Ins[i].VT;
2609     }
2610 
2611     ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2612                       Ins[i].OrigArgIndex, Ins[i].PartOffset);
2613     OrigIns.push_back(Arg);
2614   }
2615 }
2616 
2617 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
2618   if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2619     return CFP->isExactlyValue(1.0);
2620   }
2621   if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2622     return C->isAllOnesValue();
2623   }
2624   return false;
2625 }
2626 
2627 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2628   if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2629     return CFP->getValueAPF().isZero();
2630   }
2631   if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2632     return C->isNullValue();
2633   }
2634   return false;
2635 }
2636 
2637 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2638                                                   const TargetRegisterClass *RC,
2639                                                    unsigned Reg, EVT VT) const {
2640   MachineFunction &MF = DAG.getMachineFunction();
2641   MachineRegisterInfo &MRI = MF.getRegInfo();
2642   unsigned VirtualRegister;
2643   if (!MRI.isLiveIn(Reg)) {
2644     VirtualRegister = MRI.createVirtualRegister(RC);
2645     MRI.addLiveIn(Reg, VirtualRegister);
2646   } else {
2647     VirtualRegister = MRI.getLiveInVirtReg(Reg);
2648   }
2649   return DAG.getRegister(VirtualRegister, VT);
2650 }
2651 
2652 uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(
2653     const AMDGPUMachineFunction *MFI, const ImplicitParameter Param) const {
2654   uint64_t ArgOffset = MFI->ABIArgOffset;
2655   switch (Param) {
2656   case GRID_DIM:
2657     return ArgOffset;
2658   case GRID_OFFSET:
2659     return ArgOffset + 4;
2660   }
2661   llvm_unreachable("unexpected implicit parameter type");
2662 }
2663 
2664 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2665 
2666 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2667   switch ((AMDGPUISD::NodeType)Opcode) {
2668   case AMDGPUISD::FIRST_NUMBER: break;
2669   // AMDIL DAG nodes
2670   NODE_NAME_CASE(CALL);
2671   NODE_NAME_CASE(UMUL);
2672   NODE_NAME_CASE(RET_FLAG);
2673   NODE_NAME_CASE(BRANCH_COND);
2674 
2675   // AMDGPU DAG nodes
2676   NODE_NAME_CASE(DWORDADDR)
2677   NODE_NAME_CASE(FRACT)
2678   NODE_NAME_CASE(CLAMP)
2679   NODE_NAME_CASE(COS_HW)
2680   NODE_NAME_CASE(SIN_HW)
2681   NODE_NAME_CASE(FMAX_LEGACY)
2682   NODE_NAME_CASE(FMIN_LEGACY)
2683   NODE_NAME_CASE(FMAX3)
2684   NODE_NAME_CASE(SMAX3)
2685   NODE_NAME_CASE(UMAX3)
2686   NODE_NAME_CASE(FMIN3)
2687   NODE_NAME_CASE(SMIN3)
2688   NODE_NAME_CASE(UMIN3)
2689   NODE_NAME_CASE(URECIP)
2690   NODE_NAME_CASE(DIV_SCALE)
2691   NODE_NAME_CASE(DIV_FMAS)
2692   NODE_NAME_CASE(DIV_FIXUP)
2693   NODE_NAME_CASE(TRIG_PREOP)
2694   NODE_NAME_CASE(RCP)
2695   NODE_NAME_CASE(RSQ)
2696   NODE_NAME_CASE(RSQ_LEGACY)
2697   NODE_NAME_CASE(RSQ_CLAMPED)
2698   NODE_NAME_CASE(LDEXP)
2699   NODE_NAME_CASE(FP_CLASS)
2700   NODE_NAME_CASE(DOT4)
2701   NODE_NAME_CASE(CARRY)
2702   NODE_NAME_CASE(BORROW)
2703   NODE_NAME_CASE(BFE_U32)
2704   NODE_NAME_CASE(BFE_I32)
2705   NODE_NAME_CASE(BFI)
2706   NODE_NAME_CASE(BFM)
2707   NODE_NAME_CASE(BREV)
2708   NODE_NAME_CASE(MUL_U24)
2709   NODE_NAME_CASE(MUL_I24)
2710   NODE_NAME_CASE(MAD_U24)
2711   NODE_NAME_CASE(MAD_I24)
2712   NODE_NAME_CASE(TEXTURE_FETCH)
2713   NODE_NAME_CASE(EXPORT)
2714   NODE_NAME_CASE(CONST_ADDRESS)
2715   NODE_NAME_CASE(REGISTER_LOAD)
2716   NODE_NAME_CASE(REGISTER_STORE)
2717   NODE_NAME_CASE(LOAD_CONSTANT)
2718   NODE_NAME_CASE(LOAD_INPUT)
2719   NODE_NAME_CASE(SAMPLE)
2720   NODE_NAME_CASE(SAMPLEB)
2721   NODE_NAME_CASE(SAMPLED)
2722   NODE_NAME_CASE(SAMPLEL)
2723   NODE_NAME_CASE(CVT_F32_UBYTE0)
2724   NODE_NAME_CASE(CVT_F32_UBYTE1)
2725   NODE_NAME_CASE(CVT_F32_UBYTE2)
2726   NODE_NAME_CASE(CVT_F32_UBYTE3)
2727   NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2728   NODE_NAME_CASE(CONST_DATA_PTR)
2729   case AMDGPUISD::FIRST_MEM_OPCODE_NUMBER: break;
2730   NODE_NAME_CASE(SENDMSG)
2731   NODE_NAME_CASE(INTERP_MOV)
2732   NODE_NAME_CASE(INTERP_P1)
2733   NODE_NAME_CASE(INTERP_P2)
2734   NODE_NAME_CASE(STORE_MSKOR)
2735   NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2736   case AMDGPUISD::LAST_AMDGPU_ISD_NUMBER: break;
2737   }
2738   return nullptr;
2739 }
2740 
2741 SDValue AMDGPUTargetLowering::getRsqrtEstimate(SDValue Operand,
2742                                                DAGCombinerInfo &DCI,
2743                                                unsigned &RefinementSteps,
2744                                                bool &UseOneConstNR) const {
2745   SelectionDAG &DAG = DCI.DAG;
2746   EVT VT = Operand.getValueType();
2747 
2748   if (VT == MVT::f32) {
2749     RefinementSteps = 0;
2750     return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand);
2751   }
2752 
2753   // TODO: There is also f64 rsq instruction, but the documentation is less
2754   // clear on its precision.
2755 
2756   return SDValue();
2757 }
2758 
2759 SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,
2760                                                DAGCombinerInfo &DCI,
2761                                                unsigned &RefinementSteps) const {
2762   SelectionDAG &DAG = DCI.DAG;
2763   EVT VT = Operand.getValueType();
2764 
2765   if (VT == MVT::f32) {
2766     // Reciprocal, < 1 ulp error.
2767     //
2768     // This reciprocal approximation converges to < 0.5 ulp error with one
2769     // newton rhapson performed with two fused multiple adds (FMAs).
2770 
2771     RefinementSteps = 0;
2772     return DAG.getNode(AMDGPUISD::RCP, SDLoc(Operand), VT, Operand);
2773   }
2774 
2775   // TODO: There is also f64 rcp instruction, but the documentation is less
2776   // clear on its precision.
2777 
2778   return SDValue();
2779 }
2780 
2781 static void computeKnownBitsForMinMax(const SDValue Op0,
2782                                       const SDValue Op1,
2783                                       APInt &KnownZero,
2784                                       APInt &KnownOne,
2785                                       const SelectionDAG &DAG,
2786                                       unsigned Depth) {
2787   APInt Op0Zero, Op0One;
2788   APInt Op1Zero, Op1One;
2789   DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
2790   DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
2791 
2792   KnownZero = Op0Zero & Op1Zero;
2793   KnownOne = Op0One & Op1One;
2794 }
2795 
2796 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2797   const SDValue Op,
2798   APInt &KnownZero,
2799   APInt &KnownOne,
2800   const SelectionDAG &DAG,
2801   unsigned Depth) const {
2802 
2803   KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
2804 
2805   APInt KnownZero2;
2806   APInt KnownOne2;
2807   unsigned Opc = Op.getOpcode();
2808 
2809   switch (Opc) {
2810   default:
2811     break;
2812   case ISD::INTRINSIC_WO_CHAIN: {
2813     // FIXME: The intrinsic should just use the node.
2814     switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
2815     case AMDGPUIntrinsic::AMDGPU_imax:
2816     case AMDGPUIntrinsic::AMDGPU_umax:
2817     case AMDGPUIntrinsic::AMDGPU_imin:
2818     case AMDGPUIntrinsic::AMDGPU_umin:
2819       computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
2820                                 KnownZero, KnownOne, DAG, Depth);
2821       break;
2822     default:
2823       break;
2824     }
2825 
2826     break;
2827   }
2828   case AMDGPUISD::CARRY:
2829   case AMDGPUISD::BORROW: {
2830     KnownZero = APInt::getHighBitsSet(32, 31);
2831     break;
2832   }
2833 
2834   case AMDGPUISD::BFE_I32:
2835   case AMDGPUISD::BFE_U32: {
2836     ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2837     if (!CWidth)
2838       return;
2839 
2840     unsigned BitWidth = 32;
2841     uint32_t Width = CWidth->getZExtValue() & 0x1f;
2842 
2843     if (Opc == AMDGPUISD::BFE_U32)
2844       KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2845 
2846     break;
2847   }
2848   }
2849 }
2850 
2851 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2852   SDValue Op,
2853   const SelectionDAG &DAG,
2854   unsigned Depth) const {
2855   switch (Op.getOpcode()) {
2856   case AMDGPUISD::BFE_I32: {
2857     ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2858     if (!Width)
2859       return 1;
2860 
2861     unsigned SignBits = 32 - Width->getZExtValue() + 1;
2862     ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2863     if (!Offset || !Offset->isNullValue())
2864       return SignBits;
2865 
2866     // TODO: Could probably figure something out with non-0 offsets.
2867     unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2868     return std::max(SignBits, Op0SignBits);
2869   }
2870 
2871   case AMDGPUISD::BFE_U32: {
2872     ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2873     return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;
2874   }
2875 
2876   case AMDGPUISD::CARRY:
2877   case AMDGPUISD::BORROW:
2878     return 31;
2879 
2880   default:
2881     return 1;
2882   }
2883 }
2884