1//===-- AMDGPUGIsel.td - AMDGPU GlobalISel Patterns---------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8// This files contains patterns that should only be used by GlobalISel.  For
9// example patterns for V_* instructions that have S_* equivalents.
10// SelectionDAG does not support selecting V_* instructions.
11//===----------------------------------------------------------------------===//
12
13include "AMDGPU.td"
14include "AMDGPUCombine.td"
15
16def sd_vsrc0 : ComplexPattern<i32, 1, "">;
17def gi_vsrc0 :
18    GIComplexOperandMatcher<s32, "selectVSRC0">,
19    GIComplexPatternEquiv<sd_vsrc0>;
20
21def sd_vcsrc : ComplexPattern<i32, 1, "">;
22def gi_vcsrc :
23    GIComplexOperandMatcher<s32, "selectVCSRC">,
24    GIComplexPatternEquiv<sd_vcsrc>;
25
26def gi_vop3mods0 :
27    GIComplexOperandMatcher<s32, "selectVOP3Mods0">,
28    GIComplexPatternEquiv<VOP3Mods0>;
29
30def gi_vop3mods :
31    GIComplexOperandMatcher<s32, "selectVOP3Mods">,
32    GIComplexPatternEquiv<VOP3Mods>;
33
34def gi_vop3_no_mods :
35    GIComplexOperandMatcher<s32, "selectVOP3NoMods">,
36    GIComplexPatternEquiv<VOP3NoMods>;
37
38def gi_vop3mods_nnan :
39    GIComplexOperandMatcher<s32, "selectVOP3Mods_nnan">,
40    GIComplexPatternEquiv<VOP3Mods_nnan>;
41
42def gi_vop3omods :
43    GIComplexOperandMatcher<s32, "selectVOP3OMods">,
44    GIComplexPatternEquiv<VOP3OMods>;
45
46def gi_vop3pmods :
47    GIComplexOperandMatcher<s32, "selectVOP3PMods">,
48    GIComplexPatternEquiv<VOP3PMods>;
49
50def gi_vop3pmodsdot :
51    GIComplexOperandMatcher<s32, "selectVOP3PModsDOT">,
52    GIComplexPatternEquiv<VOP3PModsDOT>;
53
54def gi_dotiuvop3pmods :
55    GIComplexOperandMatcher<s32, "selectDotIUVOP3PMods">,
56    GIComplexPatternEquiv<DotIUVOP3PMods>;
57
58def gi_vop3opselmods :
59    GIComplexOperandMatcher<s32, "selectVOP3OpSelMods">,
60    GIComplexPatternEquiv<VOP3OpSelMods>;
61
62def gi_vinterpmods :
63    GIComplexOperandMatcher<s32, "selectVINTERPMods">,
64    GIComplexPatternEquiv<VINTERPMods>;
65
66def gi_vinterpmods_hi :
67    GIComplexOperandMatcher<s32, "selectVINTERPModsHi">,
68    GIComplexPatternEquiv<VINTERPModsHi>;
69
70// FIXME: Why do we have both VOP3OpSel and VOP3OpSelMods?
71def gi_vop3opsel :
72    GIComplexOperandMatcher<s32, "selectVOP3OpSelMods">,
73    GIComplexPatternEquiv<VOP3OpSel>;
74
75def gi_smrd_imm :
76    GIComplexOperandMatcher<s64, "selectSmrdImm">,
77    GIComplexPatternEquiv<SMRDImm>;
78
79def gi_smrd_imm32 :
80    GIComplexOperandMatcher<s64, "selectSmrdImm32">,
81    GIComplexPatternEquiv<SMRDImm32>;
82
83def gi_smrd_sgpr :
84    GIComplexOperandMatcher<s64, "selectSmrdSgpr">,
85    GIComplexPatternEquiv<SMRDSgpr>;
86
87def gi_flat_offset :
88    GIComplexOperandMatcher<s64, "selectFlatOffset">,
89    GIComplexPatternEquiv<FlatOffset>;
90def gi_global_offset :
91    GIComplexOperandMatcher<s64, "selectGlobalOffset">,
92    GIComplexPatternEquiv<GlobalOffset>;
93def gi_global_saddr :
94    GIComplexOperandMatcher<s64, "selectGlobalSAddr">,
95    GIComplexPatternEquiv<GlobalSAddr>;
96
97def gi_mubuf_scratch_offset :
98    GIComplexOperandMatcher<s32, "selectMUBUFScratchOffset">,
99    GIComplexPatternEquiv<MUBUFScratchOffset>;
100def gi_mubuf_scratch_offen :
101    GIComplexOperandMatcher<s32, "selectMUBUFScratchOffen">,
102    GIComplexPatternEquiv<MUBUFScratchOffen>;
103
104def gi_flat_scratch_offset :
105    GIComplexOperandMatcher<s32, "selectScratchOffset">,
106    GIComplexPatternEquiv<ScratchOffset>;
107
108def gi_flat_scratch_saddr :
109    GIComplexOperandMatcher<s32, "selectScratchSAddr">,
110    GIComplexPatternEquiv<ScratchSAddr>;
111
112def gi_flat_scratch_svaddr :
113    GIComplexOperandMatcher<s32, "selectScratchSVAddr">,
114    GIComplexPatternEquiv<ScratchSVAddr>;
115
116def gi_ds_1addr_1offset :
117    GIComplexOperandMatcher<s32, "selectDS1Addr1Offset">,
118    GIComplexPatternEquiv<DS1Addr1Offset>;
119
120def gi_ds_64bit_4byte_aligned :
121    GIComplexOperandMatcher<s64, "selectDS64Bit4ByteAligned">,
122    GIComplexPatternEquiv<DS64Bit4ByteAligned>;
123
124def gi_ds_128bit_8byte_aligned :
125    GIComplexOperandMatcher<s64, "selectDS128Bit8ByteAligned">,
126    GIComplexPatternEquiv<DS128Bit8ByteAligned>;
127
128def gi_mubuf_addr64 :
129    GIComplexOperandMatcher<s64, "selectMUBUFAddr64">,
130    GIComplexPatternEquiv<MUBUFAddr64>;
131
132def gi_mubuf_offset :
133    GIComplexOperandMatcher<s64, "selectMUBUFOffset">,
134    GIComplexPatternEquiv<MUBUFOffset>;
135
136def gi_smrd_buffer_imm :
137    GIComplexOperandMatcher<s64, "selectSMRDBufferImm">,
138    GIComplexPatternEquiv<SMRDBufferImm>;
139
140def gi_smrd_buffer_imm32 :
141    GIComplexOperandMatcher<s64, "selectSMRDBufferImm32">,
142    GIComplexPatternEquiv<SMRDBufferImm32>;
143
144// Separate load nodes are defined to glue m0 initialization in
145// SelectionDAG. The GISel selector can just insert m0 initialization
146// directly before selecting a glue-less load, so hide this
147// distinction.
148
149def : GINodeEquiv<G_LOAD, AMDGPUld_glue> {
150  let CheckMMOIsNonAtomic = 1;
151  let IfSignExtend = G_SEXTLOAD;
152  let IfZeroExtend = G_ZEXTLOAD;
153}
154
155def : GINodeEquiv<G_STORE, AMDGPUst_glue> {
156  let CheckMMOIsNonAtomic = 1;
157}
158
159def : GINodeEquiv<G_LOAD, AMDGPUatomic_ld_glue> {
160  bit CheckMMOIsAtomic = 1;
161}
162
163def : GINodeEquiv<G_STORE, AMDGPUatomic_st_glue> {
164  bit CheckMMOIsAtomic = 1;
165}
166
167
168def : GINodeEquiv<G_ATOMIC_CMPXCHG, atomic_cmp_swap_glue>;
169def : GINodeEquiv<G_ATOMICRMW_XCHG, atomic_swap_glue>;
170def : GINodeEquiv<G_ATOMICRMW_ADD, atomic_load_add_glue>;
171def : GINodeEquiv<G_ATOMICRMW_SUB, atomic_load_sub_glue>;
172def : GINodeEquiv<G_ATOMICRMW_AND, atomic_load_and_glue>;
173def : GINodeEquiv<G_ATOMICRMW_OR, atomic_load_or_glue>;
174def : GINodeEquiv<G_ATOMICRMW_XOR, atomic_load_xor_glue>;
175def : GINodeEquiv<G_ATOMICRMW_MIN, atomic_load_min_glue>;
176def : GINodeEquiv<G_ATOMICRMW_MAX, atomic_load_max_glue>;
177def : GINodeEquiv<G_ATOMICRMW_UMIN, atomic_load_umin_glue>;
178def : GINodeEquiv<G_ATOMICRMW_UMAX, atomic_load_umax_glue>;
179def : GINodeEquiv<G_ATOMICRMW_FADD, atomic_load_fadd_glue>;
180
181def : GINodeEquiv<G_AMDGPU_FFBH_U32, AMDGPUffbh_u32_impl>;
182def : GINodeEquiv<G_AMDGPU_FFBL_B32, AMDGPUffbl_b32_impl>;
183def : GINodeEquiv<G_AMDGPU_FMIN_LEGACY, AMDGPUfmin_legacy>;
184def : GINodeEquiv<G_AMDGPU_FMAX_LEGACY, AMDGPUfmax_legacy>;
185def : GINodeEquiv<G_AMDGPU_RCP_IFLAG, AMDGPUrcp_iflag>;
186
187def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE0, AMDGPUcvt_f32_ubyte0>;
188def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE1, AMDGPUcvt_f32_ubyte1>;
189def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE2, AMDGPUcvt_f32_ubyte2>;
190def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE3, AMDGPUcvt_f32_ubyte3>;
191
192def : GINodeEquiv<G_AMDGPU_CVT_PK_I16_I32, AMDGPUpk_i16_i32_impl>;
193def : GINodeEquiv<G_AMDGPU_SMED3, AMDGPUsmed3>;
194def : GINodeEquiv<G_AMDGPU_UMED3, AMDGPUumed3>;
195def : GINodeEquiv<G_AMDGPU_FMED3, AMDGPUfmed3_impl>;
196def : GINodeEquiv<G_AMDGPU_CLAMP, AMDGPUclamp>;
197
198def : GINodeEquiv<G_AMDGPU_ATOMIC_CMPXCHG, AMDGPUatomic_cmp_swap>;
199def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD, SIbuffer_load>;
200def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_USHORT, SIbuffer_load_ushort>;
201def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_UBYTE, SIbuffer_load_ubyte>;
202def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_SSHORT, SIbuffer_load_short>;
203def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_SBYTE, SIbuffer_load_byte>;
204def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_FORMAT, SIbuffer_load_format>;
205def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_FORMAT_D16, SIbuffer_load_format_d16>;
206def : GINodeEquiv<G_AMDGPU_TBUFFER_LOAD_FORMAT, SItbuffer_load>;
207def : GINodeEquiv<G_AMDGPU_TBUFFER_LOAD_FORMAT_D16, SItbuffer_load_d16>;
208def : GINodeEquiv<G_AMDGPU_BUFFER_STORE, SIbuffer_store>;
209def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_SHORT, SIbuffer_store_short>;
210def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_BYTE, SIbuffer_store_byte>;
211def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_FORMAT, SIbuffer_store_format>;
212def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_FORMAT_D16, SIbuffer_store_format_d16>;
213def : GINodeEquiv<G_AMDGPU_TBUFFER_STORE_FORMAT, SItbuffer_store>;
214def : GINodeEquiv<G_AMDGPU_TBUFFER_STORE_FORMAT_D16, SItbuffer_store_d16>;
215
216// FIXME: Check MMO is atomic
217def : GINodeEquiv<G_AMDGPU_ATOMIC_INC, SIatomic_inc>;
218def : GINodeEquiv<G_AMDGPU_ATOMIC_DEC, SIatomic_dec>;
219def : GINodeEquiv<G_AMDGPU_ATOMIC_INC, atomic_inc_glue>;
220def : GINodeEquiv<G_AMDGPU_ATOMIC_DEC, atomic_dec_glue>;
221def : GINodeEquiv<G_AMDGPU_ATOMIC_FMIN, SIatomic_fmin>;
222def : GINodeEquiv<G_AMDGPU_ATOMIC_FMAX, SIatomic_fmax>;
223def : GINodeEquiv<G_AMDGPU_ATOMIC_FMIN, atomic_load_fmin_glue>;
224def : GINodeEquiv<G_AMDGPU_ATOMIC_FMAX, atomic_load_fmax_glue>;
225
226
227def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SWAP, SIbuffer_atomic_swap>;
228def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_ADD, SIbuffer_atomic_add>;
229def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SUB, SIbuffer_atomic_sub>;
230def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SMIN, SIbuffer_atomic_smin>;
231def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_UMIN, SIbuffer_atomic_umin>;
232def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SMAX, SIbuffer_atomic_smax>;
233def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_UMAX, SIbuffer_atomic_umax>;
234def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_AND, SIbuffer_atomic_and>;
235def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_OR, SIbuffer_atomic_or>;
236def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_XOR, SIbuffer_atomic_xor>;
237def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_INC, SIbuffer_atomic_inc>;
238def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_DEC, SIbuffer_atomic_dec>;
239def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_FADD, SIbuffer_atomic_fadd>;
240def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_FMIN, SIbuffer_atomic_fmin>;
241def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_FMAX, SIbuffer_atomic_fmax>;
242def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_CMPSWAP, SIbuffer_atomic_cmpswap>;
243def : GINodeEquiv<G_AMDGPU_S_BUFFER_LOAD, SIsbuffer_load>;
244
245def : GINodeEquiv<G_FPTRUNC_ROUND_UPWARD, SIfptrunc_round_upward>;
246def : GINodeEquiv<G_FPTRUNC_ROUND_DOWNWARD, SIfptrunc_round_downward>;
247
248class GISelSop2Pat <
249  SDPatternOperator node,
250  Instruction inst,
251  ValueType dst_vt,
252  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
253
254  (dst_vt (node (src0_vt SReg_32:$src0), (src1_vt SReg_32:$src1))),
255  (inst src0_vt:$src0, src1_vt:$src1)
256>;
257
258class GISelVop2Pat <
259  SDPatternOperator node,
260  Instruction inst,
261  ValueType dst_vt,
262  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
263
264  (dst_vt (node (src0_vt (sd_vsrc0 src0_vt:$src0)), (src1_vt VGPR_32:$src1))),
265  (inst src0_vt:$src0, src1_vt:$src1)
266>;
267
268class GISelVop2CommutePat <
269  SDPatternOperator node,
270  Instruction inst,
271  ValueType dst_vt,
272  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
273
274  (dst_vt (node (src1_vt VGPR_32:$src1), (src0_vt (sd_vsrc0 src0_vt:$src0)))),
275  (inst src0_vt:$src0, src1_vt:$src1)
276>;
277
278class GISelVop3Pat2 <
279  SDPatternOperator node,
280  Instruction inst,
281  ValueType dst_vt,
282  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
283
284  (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))),
285  (inst src0_vt:$src0, src1_vt:$src1)
286>;
287
288class GISelVop3Pat2CommutePat <
289  SDPatternOperator node,
290  Instruction inst,
291  ValueType dst_vt,
292  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
293
294  (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))),
295  (inst src0_vt:$src1, src1_vt:$src0)
296>;
297
298class GISelVop3Pat2ModsPat <
299  SDPatternOperator node,
300  Instruction inst,
301  ValueType dst_vt,
302  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat <
303
304  (dst_vt (node (src0_vt (VOP3Mods0 src0_vt:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omods)),
305                (src1_vt (VOP3Mods src1_vt:$src1, i32:$src1_modifiers)))),
306  (inst i32:$src0_modifiers, src0_vt:$src0,
307        i32:$src1_modifiers, src1_vt:$src1, $clamp, $omods)
308>;
309
310multiclass GISelVop2IntrPat <
311  SDPatternOperator node, Instruction inst,
312  ValueType dst_vt, ValueType src_vt = dst_vt> {
313
314  def : GISelVop2Pat <node, inst, dst_vt, src_vt>;
315
316  // FIXME: Intrinsics aren't marked as commutable, so we need to add an explicit
317  // pattern to handle commuting.  This is another reason why legalizing to a
318  // generic machine instruction may be better that matching the intrinsic
319  // directly.
320  def : GISelVop2CommutePat <node, inst, dst_vt, src_vt>;
321}
322
323// Since GlobalISel is more flexible then SelectionDAG, I think we can get
324// away with adding patterns for integer types and not legalizing all
325// loads and stores to vector types.  This should help simplify the load/store
326// legalization.
327foreach Ty = [i64, p0, p1, p4] in {
328  defm : SMRD_Pattern <"S_LOAD_DWORDX2",  Ty>;
329}
330
331def gi_as_i32timm : GICustomOperandRenderer<"renderTruncTImm">,
332  GISDNodeXFormEquiv<as_i32timm>;
333
334def gi_as_i16timm : GICustomOperandRenderer<"renderTruncTImm">,
335  GISDNodeXFormEquiv<as_i16timm>;
336
337def gi_as_i8timm : GICustomOperandRenderer<"renderTruncTImm">,
338  GISDNodeXFormEquiv<as_i8timm>;
339
340def gi_as_i1timm : GICustomOperandRenderer<"renderTruncTImm">,
341  GISDNodeXFormEquiv<as_i1timm>;
342
343def gi_NegateImm : GICustomOperandRenderer<"renderNegateImm">,
344  GISDNodeXFormEquiv<NegateImm>;
345
346def gi_bitcast_fpimm_to_i32 : GICustomOperandRenderer<"renderBitcastImm">,
347  GISDNodeXFormEquiv<bitcast_fpimm_to_i32>;
348
349def gi_IMMPopCount : GICustomOperandRenderer<"renderPopcntImm">,
350  GISDNodeXFormEquiv<IMMPopCount>;
351
352def gi_extract_cpol : GICustomOperandRenderer<"renderExtractCPol">,
353  GISDNodeXFormEquiv<extract_cpol>;
354
355def gi_extract_swz : GICustomOperandRenderer<"renderExtractSWZ">,
356  GISDNodeXFormEquiv<extract_swz>;
357
358def gi_set_glc : GICustomOperandRenderer<"renderSetGLC">,
359  GISDNodeXFormEquiv<set_glc>;
360
361def gi_frameindex_to_targetframeindex : GICustomOperandRenderer<"renderFrameIndex">,
362  GISDNodeXFormEquiv<frameindex_to_targetframeindex>;
363