1//===-- AMDGPUGIsel.td - AMDGPU GlobalISel Patterns---------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8// This files contains patterns that should only be used by GlobalISel.  For
9// example patterns for V_* instructions that have S_* equivalents.
10// SelectionDAG does not support selecting V_* instructions.
11//===----------------------------------------------------------------------===//
12
13include "AMDGPU.td"
14include "AMDGPUCombine.td"
15
16def sd_vsrc0 : ComplexPattern<i32, 1, "">;
17def gi_vsrc0 :
18    GIComplexOperandMatcher<s32, "selectVSRC0">,
19    GIComplexPatternEquiv<sd_vsrc0>;
20
21def sd_vcsrc : ComplexPattern<i32, 1, "">;
22def gi_vcsrc :
23    GIComplexOperandMatcher<s32, "selectVCSRC">,
24    GIComplexPatternEquiv<sd_vcsrc>;
25
26def gi_vop3mods0 :
27    GIComplexOperandMatcher<s32, "selectVOP3Mods0">,
28    GIComplexPatternEquiv<VOP3Mods0>;
29
30def gi_vop3mods :
31    GIComplexOperandMatcher<s32, "selectVOP3Mods">,
32    GIComplexPatternEquiv<VOP3Mods>;
33
34def gi_vop3_no_mods :
35    GIComplexOperandMatcher<s32, "selectVOP3NoMods">,
36    GIComplexPatternEquiv<VOP3NoMods>;
37
38def gi_vop3mods_nnan :
39    GIComplexOperandMatcher<s32, "selectVOP3Mods_nnan">,
40    GIComplexPatternEquiv<VOP3Mods_nnan>;
41
42def gi_vop3omods :
43    GIComplexOperandMatcher<s32, "selectVOP3OMods">,
44    GIComplexPatternEquiv<VOP3OMods>;
45
46def gi_vop3pmods :
47    GIComplexOperandMatcher<s32, "selectVOP3PMods">,
48    GIComplexPatternEquiv<VOP3PMods>;
49
50def gi_vop3opselmods :
51    GIComplexOperandMatcher<s32, "selectVOP3OpSelMods">,
52    GIComplexPatternEquiv<VOP3OpSelMods>;
53
54// FIXME: Why do we have both VOP3OpSel and VOP3OpSelMods?
55def gi_vop3opsel :
56    GIComplexOperandMatcher<s32, "selectVOP3OpSelMods">,
57    GIComplexPatternEquiv<VOP3OpSel>;
58
59def gi_smrd_imm :
60    GIComplexOperandMatcher<s64, "selectSmrdImm">,
61    GIComplexPatternEquiv<SMRDImm>;
62
63def gi_smrd_imm32 :
64    GIComplexOperandMatcher<s64, "selectSmrdImm32">,
65    GIComplexPatternEquiv<SMRDImm32>;
66
67def gi_smrd_sgpr :
68    GIComplexOperandMatcher<s64, "selectSmrdSgpr">,
69    GIComplexPatternEquiv<SMRDSgpr>;
70
71def gi_flat_offset :
72    GIComplexOperandMatcher<s64, "selectFlatOffset">,
73    GIComplexPatternEquiv<FLATOffset>;
74def gi_flat_offset_signed :
75    GIComplexOperandMatcher<s64, "selectFlatOffsetSigned">,
76    GIComplexPatternEquiv<FLATOffsetSigned>;
77def gi_global_saddr :
78    GIComplexOperandMatcher<s64, "selectGlobalSAddr">,
79    GIComplexPatternEquiv<GlobalSAddr>;
80
81def gi_mubuf_scratch_offset :
82    GIComplexOperandMatcher<s32, "selectMUBUFScratchOffset">,
83    GIComplexPatternEquiv<MUBUFScratchOffset>;
84def gi_mubuf_scratch_offen :
85    GIComplexOperandMatcher<s32, "selectMUBUFScratchOffen">,
86    GIComplexPatternEquiv<MUBUFScratchOffen>;
87
88def gi_ds_1addr_1offset :
89    GIComplexOperandMatcher<s32, "selectDS1Addr1Offset">,
90    GIComplexPatternEquiv<DS1Addr1Offset>;
91
92def gi_ds_64bit_4byte_aligned :
93    GIComplexOperandMatcher<s64, "selectDS64Bit4ByteAligned">,
94    GIComplexPatternEquiv<DS64Bit4ByteAligned>;
95
96def gi_ds_128bit_8byte_aligned :
97    GIComplexOperandMatcher<s64, "selectDS128Bit8ByteAligned">,
98    GIComplexPatternEquiv<DS128Bit8ByteAligned>;
99
100def gi_mubuf_addr64 :
101    GIComplexOperandMatcher<s64, "selectMUBUFAddr64">,
102    GIComplexPatternEquiv<MUBUFAddr64>;
103
104def gi_mubuf_offset :
105    GIComplexOperandMatcher<s64, "selectMUBUFOffset">,
106    GIComplexPatternEquiv<MUBUFOffset>;
107
108def gi_mubuf_addr64_atomic :
109    GIComplexOperandMatcher<s64, "selectMUBUFAddr64Atomic">,
110    GIComplexPatternEquiv<MUBUFAddr64Atomic>;
111
112def gi_mubuf_offset_atomic :
113    GIComplexOperandMatcher<s64, "selectMUBUFOffsetAtomic">,
114    GIComplexPatternEquiv<MUBUFOffsetAtomic>;
115
116def gi_smrd_buffer_imm :
117    GIComplexOperandMatcher<s64, "selectSMRDBufferImm">,
118    GIComplexPatternEquiv<SMRDBufferImm>;
119
120def gi_smrd_buffer_imm32 :
121    GIComplexOperandMatcher<s64, "selectSMRDBufferImm32">,
122    GIComplexPatternEquiv<SMRDBufferImm32>;
123
124// Separate load nodes are defined to glue m0 initialization in
125// SelectionDAG. The GISel selector can just insert m0 initialization
126// directly before before selecting a glue-less load, so hide this
127// distinction.
128
129def : GINodeEquiv<G_LOAD, AMDGPUld_glue> {
130  let CheckMMOIsNonAtomic = 1;
131}
132
133def : GINodeEquiv<G_STORE, AMDGPUst_glue> {
134  let CheckMMOIsNonAtomic = 1;
135}
136
137def : GINodeEquiv<G_LOAD, AMDGPUatomic_ld_glue> {
138  bit CheckMMOIsAtomic = 1;
139}
140
141def : GINodeEquiv<G_STORE, AMDGPUatomic_st_glue> {
142  bit CheckMMOIsAtomic = 1;
143}
144
145
146def : GINodeEquiv<G_ATOMIC_CMPXCHG, atomic_cmp_swap_glue>;
147def : GINodeEquiv<G_ATOMICRMW_XCHG, atomic_swap_glue>;
148def : GINodeEquiv<G_ATOMICRMW_ADD, atomic_load_add_glue>;
149def : GINodeEquiv<G_ATOMICRMW_SUB, atomic_load_sub_glue>;
150def : GINodeEquiv<G_ATOMICRMW_AND, atomic_load_and_glue>;
151def : GINodeEquiv<G_ATOMICRMW_OR, atomic_load_or_glue>;
152def : GINodeEquiv<G_ATOMICRMW_XOR, atomic_load_xor_glue>;
153def : GINodeEquiv<G_ATOMICRMW_MIN, atomic_load_min_glue>;
154def : GINodeEquiv<G_ATOMICRMW_MAX, atomic_load_max_glue>;
155def : GINodeEquiv<G_ATOMICRMW_UMIN, atomic_load_umin_glue>;
156def : GINodeEquiv<G_ATOMICRMW_UMAX, atomic_load_umax_glue>;
157def : GINodeEquiv<G_ATOMICRMW_FADD, atomic_load_fadd_glue>;
158
159def : GINodeEquiv<G_AMDGPU_FFBH_U32, AMDGPUffbh_u32_impl>;
160def : GINodeEquiv<G_AMDGPU_FMIN_LEGACY, AMDGPUfmin_legacy>;
161def : GINodeEquiv<G_AMDGPU_FMAX_LEGACY, AMDGPUfmax_legacy>;
162def : GINodeEquiv<G_AMDGPU_RCP_IFLAG, AMDGPUrcp_iflag>;
163
164def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE0, AMDGPUcvt_f32_ubyte0>;
165def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE1, AMDGPUcvt_f32_ubyte1>;
166def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE2, AMDGPUcvt_f32_ubyte2>;
167def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE3, AMDGPUcvt_f32_ubyte3>;
168
169def : GINodeEquiv<G_AMDGPU_ATOMIC_CMPXCHG, AMDGPUatomic_cmp_swap>;
170def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD, SIbuffer_load>;
171def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_USHORT, SIbuffer_load_ushort>;
172def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_UBYTE, SIbuffer_load_ubyte>;
173def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_SSHORT, SIbuffer_load_short>;
174def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_SBYTE, SIbuffer_load_byte>;
175def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_FORMAT, SIbuffer_load_format>;
176def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_FORMAT_D16, SIbuffer_load_format_d16>;
177def : GINodeEquiv<G_AMDGPU_TBUFFER_LOAD_FORMAT, SItbuffer_load>;
178def : GINodeEquiv<G_AMDGPU_TBUFFER_LOAD_FORMAT_D16, SItbuffer_load_d16>;
179def : GINodeEquiv<G_AMDGPU_BUFFER_STORE, SIbuffer_store>;
180def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_SHORT, SIbuffer_store_short>;
181def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_BYTE, SIbuffer_store_byte>;
182def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_FORMAT, SIbuffer_store_format>;
183def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_FORMAT_D16, SIbuffer_store_format_d16>;
184def : GINodeEquiv<G_AMDGPU_TBUFFER_STORE_FORMAT, SItbuffer_store>;
185def : GINodeEquiv<G_AMDGPU_TBUFFER_STORE_FORMAT_D16, SItbuffer_store_d16>;
186
187// FIXME: Check MMO is atomic
188def : GINodeEquiv<G_AMDGPU_ATOMIC_INC, SIatomic_inc>;
189def : GINodeEquiv<G_AMDGPU_ATOMIC_DEC, SIatomic_dec>;
190def : GINodeEquiv<G_AMDGPU_ATOMIC_INC, atomic_inc_glue>;
191def : GINodeEquiv<G_AMDGPU_ATOMIC_DEC, atomic_dec_glue>;
192def : GINodeEquiv<G_AMDGPU_ATOMIC_FMIN, SIatomic_fmin>;
193def : GINodeEquiv<G_AMDGPU_ATOMIC_FMAX, SIatomic_fmax>;
194def : GINodeEquiv<G_AMDGPU_ATOMIC_FMIN, atomic_load_fmin_glue>;
195def : GINodeEquiv<G_AMDGPU_ATOMIC_FMAX, atomic_load_fmax_glue>;
196
197
198def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SWAP, SIbuffer_atomic_swap>;
199def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_ADD, SIbuffer_atomic_add>;
200def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SUB, SIbuffer_atomic_sub>;
201def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SMIN, SIbuffer_atomic_smin>;
202def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_UMIN, SIbuffer_atomic_umin>;
203def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SMAX, SIbuffer_atomic_smax>;
204def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_UMAX, SIbuffer_atomic_umax>;
205def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_AND, SIbuffer_atomic_and>;
206def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_OR, SIbuffer_atomic_or>;
207def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_XOR, SIbuffer_atomic_xor>;
208def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_INC, SIbuffer_atomic_inc>;
209def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_DEC, SIbuffer_atomic_dec>;
210def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_FADD, SIbuffer_atomic_fadd>;
211def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_CMPSWAP, SIbuffer_atomic_cmpswap>;
212def : GINodeEquiv<G_AMDGPU_S_BUFFER_LOAD, SIsbuffer_load>;
213
214class GISelSop2Pat <
215  SDPatternOperator node,
216  Instruction inst,
217  ValueType dst_vt,
218  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
219
220  (dst_vt (node (src0_vt SReg_32:$src0), (src1_vt SReg_32:$src1))),
221  (inst src0_vt:$src0, src1_vt:$src1)
222>;
223
224class GISelVop2Pat <
225  SDPatternOperator node,
226  Instruction inst,
227  ValueType dst_vt,
228  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
229
230  (dst_vt (node (src0_vt (sd_vsrc0 src0_vt:$src0)), (src1_vt VGPR_32:$src1))),
231  (inst src0_vt:$src0, src1_vt:$src1)
232>;
233
234class GISelVop2CommutePat <
235  SDPatternOperator node,
236  Instruction inst,
237  ValueType dst_vt,
238  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
239
240  (dst_vt (node (src1_vt VGPR_32:$src1), (src0_vt (sd_vsrc0 src0_vt:$src0)))),
241  (inst src0_vt:$src0, src1_vt:$src1)
242>;
243
244class GISelVop3Pat2 <
245  SDPatternOperator node,
246  Instruction inst,
247  ValueType dst_vt,
248  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
249
250  (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))),
251  (inst src0_vt:$src0, src1_vt:$src1)
252>;
253
254class GISelVop3Pat2CommutePat <
255  SDPatternOperator node,
256  Instruction inst,
257  ValueType dst_vt,
258  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
259
260  (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))),
261  (inst src0_vt:$src1, src1_vt:$src0)
262>;
263
264class GISelVop3Pat2ModsPat <
265  SDPatternOperator node,
266  Instruction inst,
267  ValueType dst_vt,
268  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat <
269
270  (dst_vt (node (src0_vt (VOP3Mods0 src0_vt:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omods)),
271                (src1_vt (VOP3Mods src1_vt:$src1, i32:$src1_modifiers)))),
272  (inst i32:$src0_modifiers, src0_vt:$src0,
273        i32:$src1_modifiers, src1_vt:$src1, $clamp, $omods)
274>;
275
276multiclass GISelVop2IntrPat <
277  SDPatternOperator node, Instruction inst,
278  ValueType dst_vt, ValueType src_vt = dst_vt> {
279
280  def : GISelVop2Pat <node, inst, dst_vt, src_vt>;
281
282  // FIXME: Intrinsics aren't marked as commutable, so we need to add an explicit
283  // pattern to handle commuting.  This is another reason why legalizing to a
284  // generic machine instruction may be better that matching the intrinsic
285  // directly.
286  def : GISelVop2CommutePat <node, inst, dst_vt, src_vt>;
287}
288
289// Since GlobalISel is more flexible then SelectionDAG, I think we can get
290// away with adding patterns for integer types and not legalizing all
291// loads and stores to vector types.  This should help simplify the load/store
292// legalization.
293foreach Ty = [i64, p0, p1, p4] in {
294  defm : SMRD_Pattern <"S_LOAD_DWORDX2",  Ty>;
295}
296
297def gi_as_i32timm : GICustomOperandRenderer<"renderTruncTImm32">,
298  GISDNodeXFormEquiv<as_i32timm>;
299
300def gi_as_i16timm : GICustomOperandRenderer<"renderTruncTImm16">,
301  GISDNodeXFormEquiv<as_i16timm>;
302
303def gi_as_i8timm : GICustomOperandRenderer<"renderTruncTImm8">,
304  GISDNodeXFormEquiv<as_i8timm>;
305
306def gi_as_i1timm : GICustomOperandRenderer<"renderTruncTImm1">,
307  GISDNodeXFormEquiv<as_i1timm>;
308
309def gi_NegateImm : GICustomOperandRenderer<"renderNegateImm">,
310  GISDNodeXFormEquiv<NegateImm>;
311
312def gi_bitcast_fpimm_to_i32 : GICustomOperandRenderer<"renderBitcastImm">,
313  GISDNodeXFormEquiv<bitcast_fpimm_to_i32>;
314
315def gi_IMMPopCount : GICustomOperandRenderer<"renderPopcntImm">,
316  GISDNodeXFormEquiv<IMMPopCount>;
317
318def gi_extract_glc : GICustomOperandRenderer<"renderExtractGLC">,
319  GISDNodeXFormEquiv<extract_glc>;
320
321def gi_extract_slc : GICustomOperandRenderer<"renderExtractSLC">,
322  GISDNodeXFormEquiv<extract_slc>;
323
324def gi_extract_dlc : GICustomOperandRenderer<"renderExtractDLC">,
325  GISDNodeXFormEquiv<extract_dlc>;
326
327def gi_extract_swz : GICustomOperandRenderer<"renderExtractSWZ">,
328  GISDNodeXFormEquiv<extract_swz>;
329
330def gi_frameindex_to_targetframeindex : GICustomOperandRenderer<"renderFrameIndex">,
331  GISDNodeXFormEquiv<frameindex_to_targetframeindex>;
332