1//===-- AMDGPUGIsel.td - AMDGPU GlobalISel Patterns---------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8// This files contains patterns that should only be used by GlobalISel.  For
9// example patterns for V_* instructions that have S_* equivalents.
10// SelectionDAG does not support selecting V_* instructions.
11//===----------------------------------------------------------------------===//
12
13include "AMDGPU.td"
14include "AMDGPUCombine.td"
15
16def sd_vsrc0 : ComplexPattern<i32, 1, "">;
17def gi_vsrc0 :
18    GIComplexOperandMatcher<s32, "selectVSRC0">,
19    GIComplexPatternEquiv<sd_vsrc0>;
20
21def sd_vcsrc : ComplexPattern<i32, 1, "">;
22def gi_vcsrc :
23    GIComplexOperandMatcher<s32, "selectVCSRC">,
24    GIComplexPatternEquiv<sd_vcsrc>;
25
26def gi_vop3mods0 :
27    GIComplexOperandMatcher<s32, "selectVOP3Mods0">,
28    GIComplexPatternEquiv<VOP3Mods0>;
29
30def gi_vop3mods :
31    GIComplexOperandMatcher<s32, "selectVOP3Mods">,
32    GIComplexPatternEquiv<VOP3Mods>;
33
34def gi_vop3_no_mods :
35    GIComplexOperandMatcher<s32, "selectVOP3NoMods">,
36    GIComplexPatternEquiv<VOP3NoMods>;
37
38def gi_vop3mods_nnan :
39    GIComplexOperandMatcher<s32, "selectVOP3Mods_nnan">,
40    GIComplexPatternEquiv<VOP3Mods_nnan>;
41
42def gi_vop3omods :
43    GIComplexOperandMatcher<s32, "selectVOP3OMods">,
44    GIComplexPatternEquiv<VOP3OMods>;
45
46def gi_vop3pmods :
47    GIComplexOperandMatcher<s32, "selectVOP3PMods">,
48    GIComplexPatternEquiv<VOP3PMods>;
49
50def gi_vop3pmodsdot :
51    GIComplexOperandMatcher<s32, "selectVOP3PModsDOT">,
52    GIComplexPatternEquiv<VOP3PModsDOT>;
53
54def gi_dotiuvop3pmods :
55    GIComplexOperandMatcher<s32, "selectDotIUVOP3PMods">,
56    GIComplexPatternEquiv<DotIUVOP3PMods>;
57
58def gi_wmmaopselvop3pmods :
59    GIComplexOperandMatcher<s32, "selectWMMAOpSelVOP3PMods">,
60    GIComplexPatternEquiv<WMMAOpSelVOP3PMods>;
61
62def gi_vop3opselmods :
63    GIComplexOperandMatcher<s32, "selectVOP3OpSelMods">,
64    GIComplexPatternEquiv<VOP3OpSelMods>;
65
66def gi_vinterpmods :
67    GIComplexOperandMatcher<s32, "selectVINTERPMods">,
68    GIComplexPatternEquiv<VINTERPMods>;
69
70def gi_vinterpmods_hi :
71    GIComplexOperandMatcher<s32, "selectVINTERPModsHi">,
72    GIComplexPatternEquiv<VINTERPModsHi>;
73
74// FIXME: Why do we have both VOP3OpSel and VOP3OpSelMods?
75def gi_vop3opsel :
76    GIComplexOperandMatcher<s32, "selectVOP3OpSelMods">,
77    GIComplexPatternEquiv<VOP3OpSel>;
78
79def gi_smrd_imm :
80    GIComplexOperandMatcher<s64, "selectSmrdImm">,
81    GIComplexPatternEquiv<SMRDImm>;
82
83def gi_smrd_imm32 :
84    GIComplexOperandMatcher<s64, "selectSmrdImm32">,
85    GIComplexPatternEquiv<SMRDImm32>;
86
87def gi_smrd_sgpr :
88    GIComplexOperandMatcher<s64, "selectSmrdSgpr">,
89    GIComplexPatternEquiv<SMRDSgpr>;
90
91def gi_flat_offset :
92    GIComplexOperandMatcher<s64, "selectFlatOffset">,
93    GIComplexPatternEquiv<FlatOffset>;
94def gi_global_offset :
95    GIComplexOperandMatcher<s64, "selectGlobalOffset">,
96    GIComplexPatternEquiv<GlobalOffset>;
97def gi_global_saddr :
98    GIComplexOperandMatcher<s64, "selectGlobalSAddr">,
99    GIComplexPatternEquiv<GlobalSAddr>;
100
101def gi_mubuf_scratch_offset :
102    GIComplexOperandMatcher<s32, "selectMUBUFScratchOffset">,
103    GIComplexPatternEquiv<MUBUFScratchOffset>;
104def gi_mubuf_scratch_offen :
105    GIComplexOperandMatcher<s32, "selectMUBUFScratchOffen">,
106    GIComplexPatternEquiv<MUBUFScratchOffen>;
107
108def gi_flat_scratch_offset :
109    GIComplexOperandMatcher<s32, "selectScratchOffset">,
110    GIComplexPatternEquiv<ScratchOffset>;
111
112def gi_flat_scratch_saddr :
113    GIComplexOperandMatcher<s32, "selectScratchSAddr">,
114    GIComplexPatternEquiv<ScratchSAddr>;
115
116def gi_flat_scratch_svaddr :
117    GIComplexOperandMatcher<s32, "selectScratchSVAddr">,
118    GIComplexPatternEquiv<ScratchSVAddr>;
119
120def gi_ds_1addr_1offset :
121    GIComplexOperandMatcher<s32, "selectDS1Addr1Offset">,
122    GIComplexPatternEquiv<DS1Addr1Offset>;
123
124def gi_ds_64bit_4byte_aligned :
125    GIComplexOperandMatcher<s64, "selectDS64Bit4ByteAligned">,
126    GIComplexPatternEquiv<DS64Bit4ByteAligned>;
127
128def gi_ds_128bit_8byte_aligned :
129    GIComplexOperandMatcher<s64, "selectDS128Bit8ByteAligned">,
130    GIComplexPatternEquiv<DS128Bit8ByteAligned>;
131
132def gi_mubuf_addr64 :
133    GIComplexOperandMatcher<s64, "selectMUBUFAddr64">,
134    GIComplexPatternEquiv<MUBUFAddr64>;
135
136def gi_mubuf_offset :
137    GIComplexOperandMatcher<s64, "selectMUBUFOffset">,
138    GIComplexPatternEquiv<MUBUFOffset>;
139
140def gi_smrd_buffer_imm :
141    GIComplexOperandMatcher<s64, "selectSMRDBufferImm">,
142    GIComplexPatternEquiv<SMRDBufferImm>;
143
144def gi_smrd_buffer_imm32 :
145    GIComplexOperandMatcher<s64, "selectSMRDBufferImm32">,
146    GIComplexPatternEquiv<SMRDBufferImm32>;
147
148// Separate load nodes are defined to glue m0 initialization in
149// SelectionDAG. The GISel selector can just insert m0 initialization
150// directly before selecting a glue-less load, so hide this
151// distinction.
152
153def : GINodeEquiv<G_LOAD, AMDGPUld_glue> {
154  let CheckMMOIsNonAtomic = 1;
155  let IfSignExtend = G_SEXTLOAD;
156  let IfZeroExtend = G_ZEXTLOAD;
157}
158
159def : GINodeEquiv<G_STORE, AMDGPUst_glue> {
160  let CheckMMOIsNonAtomic = 1;
161}
162
163def : GINodeEquiv<G_LOAD, AMDGPUatomic_ld_glue> {
164  bit CheckMMOIsAtomic = 1;
165}
166
167def : GINodeEquiv<G_STORE, AMDGPUatomic_st_glue> {
168  bit CheckMMOIsAtomic = 1;
169}
170
171
172def : GINodeEquiv<G_ATOMIC_CMPXCHG, atomic_cmp_swap_glue>;
173def : GINodeEquiv<G_ATOMICRMW_XCHG, atomic_swap_glue>;
174def : GINodeEquiv<G_ATOMICRMW_ADD, atomic_load_add_glue>;
175def : GINodeEquiv<G_ATOMICRMW_SUB, atomic_load_sub_glue>;
176def : GINodeEquiv<G_ATOMICRMW_AND, atomic_load_and_glue>;
177def : GINodeEquiv<G_ATOMICRMW_OR, atomic_load_or_glue>;
178def : GINodeEquiv<G_ATOMICRMW_XOR, atomic_load_xor_glue>;
179def : GINodeEquiv<G_ATOMICRMW_MIN, atomic_load_min_glue>;
180def : GINodeEquiv<G_ATOMICRMW_MAX, atomic_load_max_glue>;
181def : GINodeEquiv<G_ATOMICRMW_UMIN, atomic_load_umin_glue>;
182def : GINodeEquiv<G_ATOMICRMW_UMAX, atomic_load_umax_glue>;
183def : GINodeEquiv<G_ATOMICRMW_FADD, atomic_load_fadd_glue>;
184
185def : GINodeEquiv<G_AMDGPU_FFBH_U32, AMDGPUffbh_u32_impl>;
186def : GINodeEquiv<G_AMDGPU_FFBL_B32, AMDGPUffbl_b32_impl>;
187def : GINodeEquiv<G_AMDGPU_FMIN_LEGACY, AMDGPUfmin_legacy>;
188def : GINodeEquiv<G_AMDGPU_FMAX_LEGACY, AMDGPUfmax_legacy>;
189def : GINodeEquiv<G_AMDGPU_RCP_IFLAG, AMDGPUrcp_iflag>;
190
191def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE0, AMDGPUcvt_f32_ubyte0>;
192def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE1, AMDGPUcvt_f32_ubyte1>;
193def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE2, AMDGPUcvt_f32_ubyte2>;
194def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE3, AMDGPUcvt_f32_ubyte3>;
195
196def : GINodeEquiv<G_AMDGPU_CVT_PK_I16_I32, AMDGPUpk_i16_i32_impl>;
197def : GINodeEquiv<G_AMDGPU_SMED3, AMDGPUsmed3>;
198def : GINodeEquiv<G_AMDGPU_UMED3, AMDGPUumed3>;
199def : GINodeEquiv<G_AMDGPU_FMED3, AMDGPUfmed3_impl>;
200def : GINodeEquiv<G_AMDGPU_CLAMP, AMDGPUclamp>;
201
202def : GINodeEquiv<G_AMDGPU_ATOMIC_CMPXCHG, AMDGPUatomic_cmp_swap>;
203def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD, SIbuffer_load>;
204def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_USHORT, SIbuffer_load_ushort>;
205def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_UBYTE, SIbuffer_load_ubyte>;
206def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_SSHORT, SIbuffer_load_short>;
207def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_SBYTE, SIbuffer_load_byte>;
208def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_FORMAT, SIbuffer_load_format>;
209def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_FORMAT_D16, SIbuffer_load_format_d16>;
210def : GINodeEquiv<G_AMDGPU_TBUFFER_LOAD_FORMAT, SItbuffer_load>;
211def : GINodeEquiv<G_AMDGPU_TBUFFER_LOAD_FORMAT_D16, SItbuffer_load_d16>;
212def : GINodeEquiv<G_AMDGPU_BUFFER_STORE, SIbuffer_store>;
213def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_SHORT, SIbuffer_store_short>;
214def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_BYTE, SIbuffer_store_byte>;
215def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_FORMAT, SIbuffer_store_format>;
216def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_FORMAT_D16, SIbuffer_store_format_d16>;
217def : GINodeEquiv<G_AMDGPU_TBUFFER_STORE_FORMAT, SItbuffer_store>;
218def : GINodeEquiv<G_AMDGPU_TBUFFER_STORE_FORMAT_D16, SItbuffer_store_d16>;
219
220// FIXME: Check MMO is atomic
221def : GINodeEquiv<G_AMDGPU_ATOMIC_INC, SIatomic_inc>;
222def : GINodeEquiv<G_AMDGPU_ATOMIC_DEC, SIatomic_dec>;
223def : GINodeEquiv<G_AMDGPU_ATOMIC_INC, atomic_inc_glue>;
224def : GINodeEquiv<G_AMDGPU_ATOMIC_DEC, atomic_dec_glue>;
225def : GINodeEquiv<G_AMDGPU_ATOMIC_FMIN, SIatomic_fmin>;
226def : GINodeEquiv<G_AMDGPU_ATOMIC_FMAX, SIatomic_fmax>;
227def : GINodeEquiv<G_AMDGPU_ATOMIC_FMIN, atomic_load_fmin_glue>;
228def : GINodeEquiv<G_AMDGPU_ATOMIC_FMAX, atomic_load_fmax_glue>;
229
230
231def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SWAP, SIbuffer_atomic_swap>;
232def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_ADD, SIbuffer_atomic_add>;
233def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SUB, SIbuffer_atomic_sub>;
234def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SMIN, SIbuffer_atomic_smin>;
235def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_UMIN, SIbuffer_atomic_umin>;
236def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SMAX, SIbuffer_atomic_smax>;
237def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_UMAX, SIbuffer_atomic_umax>;
238def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_AND, SIbuffer_atomic_and>;
239def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_OR, SIbuffer_atomic_or>;
240def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_XOR, SIbuffer_atomic_xor>;
241def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_INC, SIbuffer_atomic_inc>;
242def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_DEC, SIbuffer_atomic_dec>;
243def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_FADD, SIbuffer_atomic_fadd>;
244def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_FMIN, SIbuffer_atomic_fmin>;
245def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_FMAX, SIbuffer_atomic_fmax>;
246def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_CMPSWAP, SIbuffer_atomic_cmpswap>;
247def : GINodeEquiv<G_AMDGPU_S_BUFFER_LOAD, SIsbuffer_load>;
248
249def : GINodeEquiv<G_FPTRUNC_ROUND_UPWARD, SIfptrunc_round_upward>;
250def : GINodeEquiv<G_FPTRUNC_ROUND_DOWNWARD, SIfptrunc_round_downward>;
251
252class GISelSop2Pat <
253  SDPatternOperator node,
254  Instruction inst,
255  ValueType dst_vt,
256  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
257
258  (dst_vt (node (src0_vt SReg_32:$src0), (src1_vt SReg_32:$src1))),
259  (inst src0_vt:$src0, src1_vt:$src1)
260>;
261
262class GISelVop2Pat <
263  SDPatternOperator node,
264  Instruction inst,
265  ValueType dst_vt,
266  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
267
268  (dst_vt (node (src0_vt (sd_vsrc0 src0_vt:$src0)), (src1_vt VGPR_32:$src1))),
269  (inst src0_vt:$src0, src1_vt:$src1)
270>;
271
272class GISelVop2CommutePat <
273  SDPatternOperator node,
274  Instruction inst,
275  ValueType dst_vt,
276  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
277
278  (dst_vt (node (src1_vt VGPR_32:$src1), (src0_vt (sd_vsrc0 src0_vt:$src0)))),
279  (inst src0_vt:$src0, src1_vt:$src1)
280>;
281
282class GISelVop3Pat2 <
283  SDPatternOperator node,
284  Instruction inst,
285  ValueType dst_vt,
286  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
287
288  (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))),
289  (inst src0_vt:$src0, src1_vt:$src1)
290>;
291
292class GISelVop3Pat2CommutePat <
293  SDPatternOperator node,
294  Instruction inst,
295  ValueType dst_vt,
296  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
297
298  (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))),
299  (inst src0_vt:$src1, src1_vt:$src0)
300>;
301
302class GISelVop3Pat2ModsPat <
303  SDPatternOperator node,
304  Instruction inst,
305  ValueType dst_vt,
306  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat <
307
308  (dst_vt (node (src0_vt (VOP3Mods0 src0_vt:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omods)),
309                (src1_vt (VOP3Mods src1_vt:$src1, i32:$src1_modifiers)))),
310  (inst i32:$src0_modifiers, src0_vt:$src0,
311        i32:$src1_modifiers, src1_vt:$src1, $clamp, $omods)
312>;
313
314multiclass GISelVop2IntrPat <
315  SDPatternOperator node, Instruction inst,
316  ValueType dst_vt, ValueType src_vt = dst_vt> {
317
318  def : GISelVop2Pat <node, inst, dst_vt, src_vt>;
319
320  // FIXME: Intrinsics aren't marked as commutable, so we need to add an explicit
321  // pattern to handle commuting.  This is another reason why legalizing to a
322  // generic machine instruction may be better that matching the intrinsic
323  // directly.
324  def : GISelVop2CommutePat <node, inst, dst_vt, src_vt>;
325}
326
327// Since GlobalISel is more flexible then SelectionDAG, I think we can get
328// away with adding patterns for integer types and not legalizing all
329// loads and stores to vector types.  This should help simplify the load/store
330// legalization.
331foreach Ty = [i64, p0, p1, p4] in {
332  defm : SMRD_Pattern <"S_LOAD_DWORDX2",  Ty>;
333}
334
335def gi_as_i32timm : GICustomOperandRenderer<"renderTruncTImm">,
336  GISDNodeXFormEquiv<as_i32timm>;
337
338def gi_as_i16timm : GICustomOperandRenderer<"renderTruncTImm">,
339  GISDNodeXFormEquiv<as_i16timm>;
340
341def gi_as_i8timm : GICustomOperandRenderer<"renderTruncTImm">,
342  GISDNodeXFormEquiv<as_i8timm>;
343
344def gi_as_i1timm : GICustomOperandRenderer<"renderTruncTImm">,
345  GISDNodeXFormEquiv<as_i1timm>;
346
347def gi_NegateImm : GICustomOperandRenderer<"renderNegateImm">,
348  GISDNodeXFormEquiv<NegateImm>;
349
350def gi_bitcast_fpimm_to_i32 : GICustomOperandRenderer<"renderBitcastImm">,
351  GISDNodeXFormEquiv<bitcast_fpimm_to_i32>;
352
353def gi_IMMPopCount : GICustomOperandRenderer<"renderPopcntImm">,
354  GISDNodeXFormEquiv<IMMPopCount>;
355
356def gi_extract_cpol : GICustomOperandRenderer<"renderExtractCPol">,
357  GISDNodeXFormEquiv<extract_cpol>;
358
359def gi_extract_swz : GICustomOperandRenderer<"renderExtractSWZ">,
360  GISDNodeXFormEquiv<extract_swz>;
361
362def gi_set_glc : GICustomOperandRenderer<"renderSetGLC">,
363  GISDNodeXFormEquiv<set_glc>;
364
365def gi_frameindex_to_targetframeindex : GICustomOperandRenderer<"renderFrameIndex">,
366  GISDNodeXFormEquiv<frameindex_to_targetframeindex>;
367