1//===-- AMDGPUGIsel.td - AMDGPU GlobalISel Patterns---------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8// This files contains patterns that should only be used by GlobalISel.  For
9// example patterns for V_* instructions that have S_* equivalents.
10// SelectionDAG does not support selecting V_* instructions.
11//===----------------------------------------------------------------------===//
12
13include "AMDGPU.td"
14include "AMDGPUCombine.td"
15
16def sd_vsrc0 : ComplexPattern<i32, 1, "">;
17def gi_vsrc0 :
18    GIComplexOperandMatcher<s32, "selectVSRC0">,
19    GIComplexPatternEquiv<sd_vsrc0>;
20
21def sd_vcsrc : ComplexPattern<i32, 1, "">;
22def gi_vcsrc :
23    GIComplexOperandMatcher<s32, "selectVCSRC">,
24    GIComplexPatternEquiv<sd_vcsrc>;
25
26def gi_vop3mods0 :
27    GIComplexOperandMatcher<s32, "selectVOP3Mods0">,
28    GIComplexPatternEquiv<VOP3Mods0>;
29
30def gi_vop3mods :
31    GIComplexOperandMatcher<s32, "selectVOP3Mods">,
32    GIComplexPatternEquiv<VOP3Mods>;
33
34def gi_vop3_no_mods :
35    GIComplexOperandMatcher<s32, "selectVOP3NoMods">,
36    GIComplexPatternEquiv<VOP3NoMods>;
37
38def gi_vop3mods_nnan :
39    GIComplexOperandMatcher<s32, "selectVOP3Mods_nnan">,
40    GIComplexPatternEquiv<VOP3Mods_nnan>;
41
42def gi_vop3omods :
43    GIComplexOperandMatcher<s32, "selectVOP3OMods">,
44    GIComplexPatternEquiv<VOP3OMods>;
45
46def gi_vop3pmods :
47    GIComplexOperandMatcher<s32, "selectVOP3PMods">,
48    GIComplexPatternEquiv<VOP3PMods>;
49
50def gi_vop3opselmods :
51    GIComplexOperandMatcher<s32, "selectVOP3OpSelMods">,
52    GIComplexPatternEquiv<VOP3OpSelMods>;
53
54def gi_smrd_imm :
55    GIComplexOperandMatcher<s64, "selectSmrdImm">,
56    GIComplexPatternEquiv<SMRDImm>;
57
58def gi_smrd_imm32 :
59    GIComplexOperandMatcher<s64, "selectSmrdImm32">,
60    GIComplexPatternEquiv<SMRDImm32>;
61
62def gi_smrd_sgpr :
63    GIComplexOperandMatcher<s64, "selectSmrdSgpr">,
64    GIComplexPatternEquiv<SMRDSgpr>;
65
66// FIXME: Why are the atomic versions separated?
67def gi_flat_offset :
68    GIComplexOperandMatcher<s64, "selectFlatOffset">,
69    GIComplexPatternEquiv<FLATOffset>;
70def gi_flat_offset_signed :
71    GIComplexOperandMatcher<s64, "selectFlatOffsetSigned">,
72    GIComplexPatternEquiv<FLATOffsetSigned>;
73def gi_flat_atomic :
74    GIComplexOperandMatcher<s64, "selectFlatOffset">,
75    GIComplexPatternEquiv<FLATAtomic>;
76def gi_flat_signed_atomic :
77    GIComplexOperandMatcher<s64, "selectFlatOffsetSigned">,
78    GIComplexPatternEquiv<FLATSignedAtomic>;
79
80def gi_mubuf_scratch_offset :
81    GIComplexOperandMatcher<s32, "selectMUBUFScratchOffset">,
82    GIComplexPatternEquiv<MUBUFScratchOffset>;
83def gi_mubuf_scratch_offen :
84    GIComplexOperandMatcher<s32, "selectMUBUFScratchOffen">,
85    GIComplexPatternEquiv<MUBUFScratchOffen>;
86
87def gi_ds_1addr_1offset :
88    GIComplexOperandMatcher<s32, "selectDS1Addr1Offset">,
89    GIComplexPatternEquiv<DS1Addr1Offset>;
90
91def gi_ds_64bit_4byte_aligned :
92    GIComplexOperandMatcher<s64, "selectDS64Bit4ByteAligned">,
93    GIComplexPatternEquiv<DS64Bit4ByteAligned>;
94
95def gi_mubuf_addr64 :
96    GIComplexOperandMatcher<s64, "selectMUBUFAddr64">,
97    GIComplexPatternEquiv<MUBUFAddr64>;
98
99def gi_mubuf_offset :
100    GIComplexOperandMatcher<s64, "selectMUBUFOffset">,
101    GIComplexPatternEquiv<MUBUFOffset>;
102
103def gi_mubuf_addr64_atomic :
104    GIComplexOperandMatcher<s64, "selectMUBUFAddr64Atomic">,
105    GIComplexPatternEquiv<MUBUFAddr64Atomic>;
106
107def gi_mubuf_offset_atomic :
108    GIComplexOperandMatcher<s64, "selectMUBUFOffsetAtomic">,
109    GIComplexPatternEquiv<MUBUFOffsetAtomic>;
110
111def gi_smrd_buffer_imm :
112    GIComplexOperandMatcher<s64, "selectSMRDBufferImm">,
113    GIComplexPatternEquiv<SMRDBufferImm>;
114
115def gi_smrd_buffer_imm32 :
116    GIComplexOperandMatcher<s64, "selectSMRDBufferImm32">,
117    GIComplexPatternEquiv<SMRDBufferImm32>;
118
119// Separate load nodes are defined to glue m0 initialization in
120// SelectionDAG. The GISel selector can just insert m0 initialization
121// directly before before selecting a glue-less load, so hide this
122// distinction.
123
124def : GINodeEquiv<G_LOAD, AMDGPUld_glue> {
125  let CheckMMOIsNonAtomic = 1;
126}
127
128def : GINodeEquiv<G_STORE, AMDGPUst_glue> {
129  let CheckMMOIsNonAtomic = 1;
130}
131
132def : GINodeEquiv<G_LOAD, AMDGPUatomic_ld_glue> {
133  bit CheckMMOIsAtomic = 1;
134}
135
136
137
138def : GINodeEquiv<G_ATOMIC_CMPXCHG, atomic_cmp_swap_glue>;
139def : GINodeEquiv<G_ATOMICRMW_XCHG, atomic_swap_glue>;
140def : GINodeEquiv<G_ATOMICRMW_ADD, atomic_load_add_glue>;
141def : GINodeEquiv<G_ATOMICRMW_SUB, atomic_load_sub_glue>;
142def : GINodeEquiv<G_ATOMICRMW_AND, atomic_load_and_glue>;
143def : GINodeEquiv<G_ATOMICRMW_OR, atomic_load_or_glue>;
144def : GINodeEquiv<G_ATOMICRMW_XOR, atomic_load_xor_glue>;
145def : GINodeEquiv<G_ATOMICRMW_MIN, atomic_load_min_glue>;
146def : GINodeEquiv<G_ATOMICRMW_MAX, atomic_load_max_glue>;
147def : GINodeEquiv<G_ATOMICRMW_UMIN, atomic_load_umin_glue>;
148def : GINodeEquiv<G_ATOMICRMW_UMAX, atomic_load_umax_glue>;
149def : GINodeEquiv<G_ATOMICRMW_FADD, atomic_load_fadd_glue>;
150
151def : GINodeEquiv<G_AMDGPU_FFBH_U32, AMDGPUffbh_u32_impl>;
152def : GINodeEquiv<G_AMDGPU_FMIN_LEGACY, AMDGPUfmin_legacy>;
153def : GINodeEquiv<G_AMDGPU_FMAX_LEGACY, AMDGPUfmax_legacy>;
154def : GINodeEquiv<G_AMDGPU_RCP_IFLAG, AMDGPUrcp_iflag>;
155
156def : GINodeEquiv<G_AMDGPU_ATOMIC_CMPXCHG, AMDGPUatomic_cmp_swap>;
157def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD, SIbuffer_load>;
158def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_USHORT, SIbuffer_load_ushort>;
159def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_UBYTE, SIbuffer_load_ubyte>;
160def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_SSHORT, SIbuffer_load_short>;
161def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_SBYTE, SIbuffer_load_byte>;
162def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_FORMAT, SIbuffer_load_format>;
163def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_FORMAT_D16, SIbuffer_load_format_d16>;
164def : GINodeEquiv<G_AMDGPU_TBUFFER_LOAD_FORMAT, SItbuffer_load>;
165def : GINodeEquiv<G_AMDGPU_TBUFFER_LOAD_FORMAT_D16, SItbuffer_load_d16>;
166def : GINodeEquiv<G_AMDGPU_BUFFER_STORE, SIbuffer_store>;
167def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_SHORT, SIbuffer_store_short>;
168def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_BYTE, SIbuffer_store_byte>;
169def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_FORMAT, SIbuffer_store_format>;
170def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_FORMAT_D16, SIbuffer_store_format_d16>;
171def : GINodeEquiv<G_AMDGPU_TBUFFER_STORE_FORMAT, SItbuffer_store>;
172def : GINodeEquiv<G_AMDGPU_TBUFFER_STORE_FORMAT_D16, SItbuffer_store_d16>;
173
174// FIXME: Check MMO is atomic
175def : GINodeEquiv<G_AMDGPU_ATOMIC_INC, SIatomic_inc>;
176def : GINodeEquiv<G_AMDGPU_ATOMIC_DEC, SIatomic_dec>;
177def : GINodeEquiv<G_AMDGPU_ATOMIC_INC, atomic_inc_glue>;
178def : GINodeEquiv<G_AMDGPU_ATOMIC_DEC, atomic_dec_glue>;
179
180def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SWAP, SIbuffer_atomic_swap>;
181def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_ADD, SIbuffer_atomic_add>;
182def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SUB, SIbuffer_atomic_sub>;
183def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SMIN, SIbuffer_atomic_smin>;
184def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_UMIN, SIbuffer_atomic_umin>;
185def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SMAX, SIbuffer_atomic_smax>;
186def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_UMAX, SIbuffer_atomic_umax>;
187def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_AND, SIbuffer_atomic_and>;
188def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_OR, SIbuffer_atomic_or>;
189def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_XOR, SIbuffer_atomic_xor>;
190def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_INC, SIbuffer_atomic_inc>;
191def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_DEC, SIbuffer_atomic_dec>;
192def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_CMPSWAP, SIbuffer_atomic_cmpswap>;
193def : GINodeEquiv<G_AMDGPU_S_BUFFER_LOAD, SIsbuffer_load>;
194
195class GISelSop2Pat <
196  SDPatternOperator node,
197  Instruction inst,
198  ValueType dst_vt,
199  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
200
201  (dst_vt (node (src0_vt SReg_32:$src0), (src1_vt SReg_32:$src1))),
202  (inst src0_vt:$src0, src1_vt:$src1)
203>;
204
205class GISelVop2Pat <
206  SDPatternOperator node,
207  Instruction inst,
208  ValueType dst_vt,
209  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
210
211  (dst_vt (node (src0_vt (sd_vsrc0 src0_vt:$src0)), (src1_vt VGPR_32:$src1))),
212  (inst src0_vt:$src0, src1_vt:$src1)
213>;
214
215class GISelVop2CommutePat <
216  SDPatternOperator node,
217  Instruction inst,
218  ValueType dst_vt,
219  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
220
221  (dst_vt (node (src1_vt VGPR_32:$src1), (src0_vt (sd_vsrc0 src0_vt:$src0)))),
222  (inst src0_vt:$src0, src1_vt:$src1)
223>;
224
225class GISelVop3Pat2 <
226  SDPatternOperator node,
227  Instruction inst,
228  ValueType dst_vt,
229  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
230
231  (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))),
232  (inst src0_vt:$src0, src1_vt:$src1)
233>;
234
235class GISelVop3Pat2CommutePat <
236  SDPatternOperator node,
237  Instruction inst,
238  ValueType dst_vt,
239  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
240
241  (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))),
242  (inst src0_vt:$src1, src1_vt:$src0)
243>;
244
245class GISelVop3Pat2ModsPat <
246  SDPatternOperator node,
247  Instruction inst,
248  ValueType dst_vt,
249  ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat <
250
251  (dst_vt (node (src0_vt (VOP3Mods0 src0_vt:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omods)),
252                (src1_vt (VOP3Mods src1_vt:$src1, i32:$src1_modifiers)))),
253  (inst i32:$src0_modifiers, src0_vt:$src0,
254        i32:$src1_modifiers, src1_vt:$src1, $clamp, $omods)
255>;
256
257multiclass GISelVop2IntrPat <
258  SDPatternOperator node, Instruction inst,
259  ValueType dst_vt, ValueType src_vt = dst_vt> {
260
261  def : GISelVop2Pat <node, inst, dst_vt, src_vt>;
262
263  // FIXME: Intrinsics aren't marked as commutable, so we need to add an explcit
264  // pattern to handle commuting.  This is another reason why legalizing to a
265  // generic machine instruction may be better that matching the intrinsic
266  // directly.
267  def : GISelVop2CommutePat <node, inst, dst_vt, src_vt>;
268}
269
270// Since GlobalISel is more flexible then SelectionDAG, I think we can get
271// away with adding patterns for integer types and not legalizing all
272// loads and stores to vector types.  This should help simplify the load/store
273// legalization.
274foreach Ty = [i64, p0, p1, p4] in {
275  defm : SMRD_Pattern <"S_LOAD_DWORDX2",  Ty>;
276}
277
278def gi_as_i32timm : GICustomOperandRenderer<"renderTruncTImm32">,
279  GISDNodeXFormEquiv<as_i32timm>;
280
281def gi_as_i16timm : GICustomOperandRenderer<"renderTruncTImm16">,
282  GISDNodeXFormEquiv<as_i16timm>;
283
284def gi_as_i8timm : GICustomOperandRenderer<"renderTruncTImm8">,
285  GISDNodeXFormEquiv<as_i8timm>;
286
287def gi_as_i1timm : GICustomOperandRenderer<"renderTruncTImm1">,
288  GISDNodeXFormEquiv<as_i1timm>;
289
290def gi_NegateImm : GICustomOperandRenderer<"renderNegateImm">,
291  GISDNodeXFormEquiv<NegateImm>;
292
293def gi_bitcast_fpimm_to_i32 : GICustomOperandRenderer<"renderBitcastImm">,
294  GISDNodeXFormEquiv<bitcast_fpimm_to_i32>;
295
296def gi_IMMPopCount : GICustomOperandRenderer<"renderPopcntImm">,
297  GISDNodeXFormEquiv<IMMPopCount>;
298
299def gi_extract_glc : GICustomOperandRenderer<"renderExtractGLC">,
300  GISDNodeXFormEquiv<extract_glc>;
301
302def gi_extract_slc : GICustomOperandRenderer<"renderExtractSLC">,
303  GISDNodeXFormEquiv<extract_slc>;
304
305def gi_extract_dlc : GICustomOperandRenderer<"renderExtractDLC">,
306  GISDNodeXFormEquiv<extract_dlc>;
307
308def gi_extract_swz : GICustomOperandRenderer<"renderExtractSWZ">,
309  GISDNodeXFormEquiv<extract_swz>;
310