1 //===-- AMDGPUAsmPrinter.h - Print AMDGPU assembly code ---------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief AMDGPU Assembly printer class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUASMPRINTER_H 16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUASMPRINTER_H 17 18 #include "AMDGPU.h" 19 #include "AMDKernelCodeT.h" 20 #include "MCTargetDesc/AMDGPUHSAMetadataStreamer.h" 21 #include "llvm/ADT/StringRef.h" 22 #include "llvm/CodeGen/AsmPrinter.h" 23 #include <cstddef> 24 #include <cstdint> 25 #include <limits> 26 #include <memory> 27 #include <string> 28 #include <vector> 29 30 namespace llvm { 31 32 class AMDGPUTargetStreamer; 33 class MCOperand; 34 class SISubtarget; 35 36 class AMDGPUAsmPrinter final : public AsmPrinter { 37 private: 38 // Track resource usage for callee functions. 39 struct SIFunctionResourceInfo { 40 // Track the number of explicitly used VGPRs. Special registers reserved at 41 // the end are tracked separately. 42 int32_t NumVGPR = 0; 43 int32_t NumExplicitSGPR = 0; 44 uint32_t PrivateSegmentSize = 0; 45 bool UsesVCC = false; 46 bool UsesFlatScratch = false; 47 bool HasDynamicallySizedStack = false; 48 bool HasRecursion = false; 49 50 int32_t getTotalNumSGPRs(const SISubtarget &ST) const; 51 }; 52 53 // Track resource usage for kernels / entry functions. 54 struct SIProgramInfo { 55 // Fields set in PGM_RSRC1 pm4 packet. 56 uint32_t VGPRBlocks = 0; 57 uint32_t SGPRBlocks = 0; 58 uint32_t Priority = 0; 59 uint32_t FloatMode = 0; 60 uint32_t Priv = 0; 61 uint32_t DX10Clamp = 0; 62 uint32_t DebugMode = 0; 63 uint32_t IEEEMode = 0; 64 uint32_t ScratchSize = 0; 65 66 uint64_t ComputePGMRSrc1 = 0; 67 68 // Fields set in PGM_RSRC2 pm4 packet. 69 uint32_t LDSBlocks = 0; 70 uint32_t ScratchBlocks = 0; 71 72 uint64_t ComputePGMRSrc2 = 0; 73 74 uint32_t NumVGPR = 0; 75 uint32_t NumSGPR = 0; 76 uint32_t LDSSize = 0; 77 bool FlatUsed = false; 78 79 // Number of SGPRs that meets number of waves per execution unit request. 80 uint32_t NumSGPRsForWavesPerEU = 0; 81 82 // Number of VGPRs that meets number of waves per execution unit request. 83 uint32_t NumVGPRsForWavesPerEU = 0; 84 85 // If ReservedVGPRCount is 0 then must be 0. Otherwise, this is the first 86 // fixed VGPR number reserved. 87 uint16_t ReservedVGPRFirst = 0; 88 89 // The number of consecutive VGPRs reserved. 90 uint16_t ReservedVGPRCount = 0; 91 92 // Fixed SGPR number used to hold wave scratch offset for entire kernel 93 // execution, or std::numeric_limits<uint16_t>::max() if the register is not 94 // used or not known. 95 uint16_t DebuggerWavefrontPrivateSegmentOffsetSGPR = 96 std::numeric_limits<uint16_t>::max(); 97 98 // Fixed SGPR number of the first 4 SGPRs used to hold scratch V# for entire 99 // kernel execution, or std::numeric_limits<uint16_t>::max() if the register 100 // is not used or not known. 101 uint16_t DebuggerPrivateSegmentBufferSGPR = 102 std::numeric_limits<uint16_t>::max(); 103 104 // Whether there is recursion, dynamic allocas, indirect calls or some other 105 // reason there may be statically unknown stack usage. 106 bool DynamicCallStack = false; 107 108 // Bonus information for debugging. 109 bool VCCUsed = false; 110 111 SIProgramInfo() = default; 112 }; 113 114 SIProgramInfo CurrentProgramInfo; 115 DenseMap<const Function *, SIFunctionResourceInfo> CallGraphResourceInfo; 116 117 AMDGPU::HSAMD::MetadataStreamer HSAMetadataStream; 118 std::map<uint32_t, uint32_t> PALMetadataMap; 119 120 uint64_t getFunctionCodeSize(const MachineFunction &MF) const; 121 SIFunctionResourceInfo analyzeResourceUsage(const MachineFunction &MF) const; 122 123 void readPALMetadata(Module &M); 124 void getSIProgramInfo(SIProgramInfo &Out, const MachineFunction &MF); 125 void getAmdKernelCode(amd_kernel_code_t &Out, const SIProgramInfo &KernelInfo, 126 const MachineFunction &MF) const; 127 void findNumUsedRegistersSI(const MachineFunction &MF, 128 unsigned &NumSGPR, 129 unsigned &NumVGPR) const; 130 131 /// \brief Emit register usage information so that the GPU driver 132 /// can correctly setup the GPU state. 133 void EmitProgramInfoR600(const MachineFunction &MF); 134 void EmitProgramInfoSI(const MachineFunction &MF, 135 const SIProgramInfo &KernelInfo); 136 void EmitPALMetadata(const MachineFunction &MF, 137 const SIProgramInfo &KernelInfo); 138 void emitCommonFunctionComments(uint32_t NumVGPR, 139 uint32_t NumSGPR, 140 uint32_t ScratchSize, 141 uint64_t CodeSize); 142 143 public: 144 explicit AMDGPUAsmPrinter(TargetMachine &TM, 145 std::unique_ptr<MCStreamer> Streamer); 146 147 StringRef getPassName() const override; 148 149 const MCSubtargetInfo* getSTI() const; 150 151 AMDGPUTargetStreamer& getTargetStreamer() const; 152 153 bool doFinalization(Module &M) override; 154 bool runOnMachineFunction(MachineFunction &MF) override; 155 156 /// \brief Wrapper for MCInstLowering.lowerOperand() for the tblgen'erated 157 /// pseudo lowering. 158 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const; 159 160 /// \brief Lower the specified LLVM Constant to an MCExpr. 161 /// The AsmPrinter::lowerConstantof does not know how to lower 162 /// addrspacecast, therefore they should be lowered by this function. 163 const MCExpr *lowerConstant(const Constant *CV) override; 164 165 /// \brief tblgen'erated driver function for lowering simple MI->MC pseudo 166 /// instructions. 167 bool emitPseudoExpansionLowering(MCStreamer &OutStreamer, 168 const MachineInstr *MI); 169 170 /// Implemented in AMDGPUMCInstLower.cpp 171 void EmitInstruction(const MachineInstr *MI) override; 172 173 void EmitFunctionBodyStart() override; 174 175 void EmitFunctionEntryLabel() override; 176 177 void EmitGlobalVariable(const GlobalVariable *GV) override; 178 179 void EmitStartOfAsmFile(Module &M) override; 180 181 void EmitEndOfAsmFile(Module &M) override; 182 183 bool isBlockOnlyReachableByFallthrough( 184 const MachineBasicBlock *MBB) const override; 185 186 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, 187 unsigned AsmVariant, const char *ExtraCode, 188 raw_ostream &O) override; 189 190 protected: 191 std::vector<std::string> DisasmLines, HexLines; 192 size_t DisasmLineMaxLen; 193 AMDGPUAS AMDGPUASI; 194 }; 195 196 } // end namespace llvm 197 198 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUASMPRINTER_H 199