1 //===-- AMDGPUAsmPrinter.h - Print AMDGPU assembly code ---------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief AMDGPU Assembly printer class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUASMPRINTER_H 16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUASMPRINTER_H 17 18 #include "AMDGPU.h" 19 #include "AMDKernelCodeT.h" 20 #include "llvm/ADT/StringRef.h" 21 #include "llvm/CodeGen/AsmPrinter.h" 22 #include <cstddef> 23 #include <cstdint> 24 #include <limits> 25 #include <memory> 26 #include <string> 27 #include <vector> 28 29 namespace llvm { 30 31 class AMDGPUTargetStreamer; 32 class MCOperand; 33 class SISubtarget; 34 35 class AMDGPUAsmPrinter final : public AsmPrinter { 36 private: 37 // Track resource usage for callee functions. 38 struct SIFunctionResourceInfo { 39 // Track the number of explicitly used VGPRs. Special registers reserved at 40 // the end are tracked separately. 41 int32_t NumVGPR = 0; 42 int32_t NumExplicitSGPR = 0; 43 uint32_t PrivateSegmentSize = 0; 44 bool UsesVCC = false; 45 bool UsesFlatScratch = false; 46 bool HasDynamicallySizedStack = false; 47 bool HasRecursion = false; 48 49 int32_t getTotalNumSGPRs(const SISubtarget &ST) const; 50 }; 51 52 // Track resource usage for kernels / entry functions. 53 struct SIProgramInfo { 54 // Fields set in PGM_RSRC1 pm4 packet. 55 uint32_t VGPRBlocks = 0; 56 uint32_t SGPRBlocks = 0; 57 uint32_t Priority = 0; 58 uint32_t FloatMode = 0; 59 uint32_t Priv = 0; 60 uint32_t DX10Clamp = 0; 61 uint32_t DebugMode = 0; 62 uint32_t IEEEMode = 0; 63 uint32_t ScratchSize = 0; 64 65 uint64_t ComputePGMRSrc1 = 0; 66 67 // Fields set in PGM_RSRC2 pm4 packet. 68 uint32_t LDSBlocks = 0; 69 uint32_t ScratchBlocks = 0; 70 71 uint64_t ComputePGMRSrc2 = 0; 72 73 uint32_t NumVGPR = 0; 74 uint32_t NumSGPR = 0; 75 uint32_t LDSSize = 0; 76 bool FlatUsed = false; 77 78 // Number of SGPRs that meets number of waves per execution unit request. 79 uint32_t NumSGPRsForWavesPerEU = 0; 80 81 // Number of VGPRs that meets number of waves per execution unit request. 82 uint32_t NumVGPRsForWavesPerEU = 0; 83 84 // If ReservedVGPRCount is 0 then must be 0. Otherwise, this is the first 85 // fixed VGPR number reserved. 86 uint16_t ReservedVGPRFirst = 0; 87 88 // The number of consecutive VGPRs reserved. 89 uint16_t ReservedVGPRCount = 0; 90 91 // Fixed SGPR number used to hold wave scratch offset for entire kernel 92 // execution, or std::numeric_limits<uint16_t>::max() if the register is not 93 // used or not known. 94 uint16_t DebuggerWavefrontPrivateSegmentOffsetSGPR = 95 std::numeric_limits<uint16_t>::max(); 96 97 // Fixed SGPR number of the first 4 SGPRs used to hold scratch V# for entire 98 // kernel execution, or std::numeric_limits<uint16_t>::max() if the register 99 // is not used or not known. 100 uint16_t DebuggerPrivateSegmentBufferSGPR = 101 std::numeric_limits<uint16_t>::max(); 102 103 // Whether there is recursion, dynamic allocas, indirect calls or some other 104 // reason there may be statically unknown stack usage. 105 bool DynamicCallStack = false; 106 107 // Bonus information for debugging. 108 bool VCCUsed = false; 109 110 SIProgramInfo() = default; 111 }; 112 113 SIProgramInfo CurrentProgramInfo; 114 DenseMap<const Function *, SIFunctionResourceInfo> CallGraphResourceInfo; 115 116 uint64_t getFunctionCodeSize(const MachineFunction &MF) const; 117 SIFunctionResourceInfo analyzeResourceUsage(const MachineFunction &MF) const; 118 119 void getSIProgramInfo(SIProgramInfo &Out, const MachineFunction &MF); 120 void getAmdKernelCode(amd_kernel_code_t &Out, const SIProgramInfo &KernelInfo, 121 const MachineFunction &MF) const; 122 void findNumUsedRegistersSI(const MachineFunction &MF, 123 unsigned &NumSGPR, 124 unsigned &NumVGPR) const; 125 126 /// \brief Emit register usage information so that the GPU driver 127 /// can correctly setup the GPU state. 128 void EmitProgramInfoR600(const MachineFunction &MF); 129 void EmitProgramInfoSI(const MachineFunction &MF, const SIProgramInfo &KernelInfo); 130 void emitCommonFunctionComments(uint32_t NumVGPR, 131 uint32_t NumSGPR, 132 uint32_t ScratchSize, 133 uint64_t CodeSize); 134 135 public: 136 explicit AMDGPUAsmPrinter(TargetMachine &TM, 137 std::unique_ptr<MCStreamer> Streamer); 138 139 StringRef getPassName() const override; 140 141 const MCSubtargetInfo* getSTI() const; 142 143 AMDGPUTargetStreamer& getTargetStreamer() const; 144 145 bool doFinalization(Module &M) override; 146 bool runOnMachineFunction(MachineFunction &MF) override; 147 148 /// \brief Wrapper for MCInstLowering.lowerOperand() for the tblgen'erated 149 /// pseudo lowering. 150 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const; 151 152 /// \brief Lower the specified LLVM Constant to an MCExpr. 153 /// The AsmPrinter::lowerConstantof does not know how to lower 154 /// addrspacecast, therefore they should be lowered by this function. 155 const MCExpr *lowerConstant(const Constant *CV) override; 156 157 /// \brief tblgen'erated driver function for lowering simple MI->MC pseudo 158 /// instructions. 159 bool emitPseudoExpansionLowering(MCStreamer &OutStreamer, 160 const MachineInstr *MI); 161 162 /// Implemented in AMDGPUMCInstLower.cpp 163 void EmitInstruction(const MachineInstr *MI) override; 164 165 void EmitFunctionBodyStart() override; 166 167 void EmitFunctionEntryLabel() override; 168 169 void EmitGlobalVariable(const GlobalVariable *GV) override; 170 171 void EmitStartOfAsmFile(Module &M) override; 172 173 void EmitEndOfAsmFile(Module &M) override; 174 175 bool isBlockOnlyReachableByFallthrough( 176 const MachineBasicBlock *MBB) const override; 177 178 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, 179 unsigned AsmVariant, const char *ExtraCode, 180 raw_ostream &O) override; 181 182 protected: 183 std::vector<std::string> DisasmLines, HexLines; 184 size_t DisasmLineMaxLen; 185 AMDGPUAS AMDGPUASI; 186 }; 187 188 } // end namespace llvm 189 190 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUASMPRINTER_H 191