1 //===-- AMDGPUAsmPrinter.h - Print AMDGPU assembly code ---------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief AMDGPU Assembly printer class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUASMPRINTER_H
16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUASMPRINTER_H
17 
18 #include "AMDGPUMCInstLower.h"
19 
20 #include "llvm/CodeGen/AsmPrinter.h"
21 #include <vector>
22 
23 namespace llvm {
24 class MCOperand;
25 
26 class AMDGPUAsmPrinter final : public AsmPrinter {
27 private:
28   struct SIProgramInfo {
29     SIProgramInfo() :
30       VGPRBlocks(0),
31       SGPRBlocks(0),
32       Priority(0),
33       FloatMode(0),
34       Priv(0),
35       DX10Clamp(0),
36       DebugMode(0),
37       IEEEMode(0),
38       ScratchSize(0),
39       ComputePGMRSrc1(0),
40       LDSBlocks(0),
41       ScratchBlocks(0),
42       ComputePGMRSrc2(0),
43       NumVGPR(0),
44       NumSGPR(0),
45       FlatUsed(false),
46       NumSGPRsForWavesPerEU(0),
47       NumVGPRsForWavesPerEU(0),
48       ReservedVGPRFirst(0),
49       ReservedVGPRCount(0),
50       DebuggerWavefrontPrivateSegmentOffsetSGPR((uint16_t)-1),
51       DebuggerPrivateSegmentBufferSGPR((uint16_t)-1),
52       VCCUsed(false),
53       CodeLen(0) {}
54 
55     // Fields set in PGM_RSRC1 pm4 packet.
56     uint32_t VGPRBlocks;
57     uint32_t SGPRBlocks;
58     uint32_t Priority;
59     uint32_t FloatMode;
60     uint32_t Priv;
61     uint32_t DX10Clamp;
62     uint32_t DebugMode;
63     uint32_t IEEEMode;
64     uint32_t ScratchSize;
65 
66     uint64_t ComputePGMRSrc1;
67 
68     // Fields set in PGM_RSRC2 pm4 packet.
69     uint32_t LDSBlocks;
70     uint32_t ScratchBlocks;
71 
72     uint64_t ComputePGMRSrc2;
73 
74     uint32_t NumVGPR;
75     uint32_t NumSGPR;
76     uint32_t LDSSize;
77     bool FlatUsed;
78 
79     // Number of SGPRs that meets number of waves per execution unit request.
80     uint32_t NumSGPRsForWavesPerEU;
81 
82     // Number of VGPRs that meets number of waves per execution unit request.
83     uint32_t NumVGPRsForWavesPerEU;
84 
85     // If ReservedVGPRCount is 0 then must be 0. Otherwise, this is the first
86     // fixed VGPR number reserved.
87     uint16_t ReservedVGPRFirst;
88 
89     // The number of consecutive VGPRs reserved.
90     uint16_t ReservedVGPRCount;
91 
92     // Fixed SGPR number used to hold wave scratch offset for entire kernel
93     // execution, or uint16_t(-1) if the register is not used or not known.
94     uint16_t DebuggerWavefrontPrivateSegmentOffsetSGPR;
95 
96     // Fixed SGPR number of the first 4 SGPRs used to hold scratch V# for entire
97     // kernel execution, or uint16_t(-1) if the register is not used or not
98     // known.
99     uint16_t DebuggerPrivateSegmentBufferSGPR;
100 
101     // Bonus information for debugging.
102     bool VCCUsed;
103     uint64_t CodeLen;
104   };
105 
106   void getSIProgramInfo(SIProgramInfo &Out, const MachineFunction &MF) const;
107   void findNumUsedRegistersSI(const MachineFunction &MF,
108                               unsigned &NumSGPR,
109                               unsigned &NumVGPR) const;
110 
111   /// \brief Emit register usage information so that the GPU driver
112   /// can correctly setup the GPU state.
113   void EmitProgramInfoR600(const MachineFunction &MF);
114   void EmitProgramInfoSI(const MachineFunction &MF, const SIProgramInfo &KernelInfo);
115   void EmitAmdKernelCodeT(const MachineFunction &MF,
116                           const SIProgramInfo &KernelInfo) const;
117 
118 public:
119   explicit AMDGPUAsmPrinter(TargetMachine &TM,
120                             std::unique_ptr<MCStreamer> Streamer);
121 
122   bool runOnMachineFunction(MachineFunction &MF) override;
123 
124   StringRef getPassName() const override;
125 
126   /// \brief Wrapper for MCInstLowering.lowerOperand() for the tblgen'erated
127   /// pseudo lowering.
128   bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const;
129 
130   /// \brief tblgen'erated driver function for lowering simple MI->MC pseudo
131   /// instructions.
132   bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
133                                    const MachineInstr *MI);
134 
135   /// Implemented in AMDGPUMCInstLower.cpp
136   void EmitInstruction(const MachineInstr *MI) override;
137 
138   void EmitFunctionBodyStart() override;
139 
140   void EmitFunctionEntryLabel() override;
141 
142   void EmitGlobalVariable(const GlobalVariable *GV) override;
143 
144   void EmitStartOfAsmFile(Module &M) override;
145 
146   bool isBlockOnlyReachableByFallthrough(
147     const MachineBasicBlock *MBB) const override;
148 
149   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
150                        unsigned AsmVariant, const char *ExtraCode,
151                        raw_ostream &O) override;
152 
153 protected:
154   std::vector<std::string> DisasmLines, HexLines;
155   size_t DisasmLineMaxLen;
156 };
157 
158 } // End anonymous llvm
159 
160 #endif
161