1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU assembly printer --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 ///
11 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
12 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
13 /// an MCObjectStreamer it outputs binary code.
14 //
15 //===----------------------------------------------------------------------===//
16 //
17 
18 #include "AMDGPUAsmPrinter.h"
19 #include "AMDGPU.h"
20 #include "AMDGPUSubtarget.h"
21 #include "AMDGPUTargetMachine.h"
22 #include "MCTargetDesc/AMDGPUInstPrinter.h"
23 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
24 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
25 #include "R600AsmPrinter.h"
26 #include "R600Defines.h"
27 #include "R600MachineFunctionInfo.h"
28 #include "R600RegisterInfo.h"
29 #include "SIDefines.h"
30 #include "SIInstrInfo.h"
31 #include "SIMachineFunctionInfo.h"
32 #include "SIRegisterInfo.h"
33 #include "TargetInfo/AMDGPUTargetInfo.h"
34 #include "Utils/AMDGPUBaseInfo.h"
35 #include "llvm/BinaryFormat/ELF.h"
36 #include "llvm/CodeGen/MachineFrameInfo.h"
37 #include "llvm/IR/DiagnosticInfo.h"
38 #include "llvm/MC/MCAssembler.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCSectionELF.h"
41 #include "llvm/MC/MCStreamer.h"
42 #include "llvm/Support/AMDGPUMetadata.h"
43 #include "llvm/Support/MathExtras.h"
44 #include "llvm/Support/TargetParser.h"
45 #include "llvm/Support/TargetRegistry.h"
46 #include "llvm/Target/TargetLoweringObjectFile.h"
47 
48 using namespace llvm;
49 using namespace llvm::AMDGPU;
50 using namespace llvm::AMDGPU::HSAMD;
51 
52 // This should get the default rounding mode from the kernel. We just set the
53 // default here, but this could change if the OpenCL rounding mode pragmas are
54 // used.
55 //
56 // The denormal mode here should match what is reported by the OpenCL runtime
57 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
58 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
59 //
60 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
61 // precision, and leaves single precision to flush all and does not report
62 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
63 // CL_FP_DENORM for both.
64 //
65 // FIXME: It seems some instructions do not support single precision denormals
66 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
67 // and sin_f32, cos_f32 on most parts).
68 
69 // We want to use these instructions, and using fp32 denormals also causes
70 // instructions to run at the double precision rate for the device so it's
71 // probably best to just report no single precision denormals.
72 static uint32_t getFPMode(AMDGPU::SIModeRegisterDefaults Mode) {
73   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
74          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
75          FP_DENORM_MODE_SP(Mode.fpDenormModeSPValue()) |
76          FP_DENORM_MODE_DP(Mode.fpDenormModeDPValue());
77 }
78 
79 static AsmPrinter *
80 createAMDGPUAsmPrinterPass(TargetMachine &tm,
81                            std::unique_ptr<MCStreamer> &&Streamer) {
82   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
83 }
84 
85 extern "C" void LLVM_EXTERNAL_VISIBILITY LLVMInitializeAMDGPUAsmPrinter() {
86   TargetRegistry::RegisterAsmPrinter(getTheAMDGPUTarget(),
87                                      llvm::createR600AsmPrinterPass);
88   TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(),
89                                      createAMDGPUAsmPrinterPass);
90 }
91 
92 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
93                                    std::unique_ptr<MCStreamer> Streamer)
94   : AsmPrinter(TM, std::move(Streamer)) {
95     if (IsaInfo::hasCodeObjectV3(getGlobalSTI()))
96       HSAMetadataStream.reset(new MetadataStreamerV3());
97     else
98       HSAMetadataStream.reset(new MetadataStreamerV2());
99 }
100 
101 StringRef AMDGPUAsmPrinter::getPassName() const {
102   return "AMDGPU Assembly Printer";
103 }
104 
105 const MCSubtargetInfo *AMDGPUAsmPrinter::getGlobalSTI() const {
106   return TM.getMCSubtargetInfo();
107 }
108 
109 AMDGPUTargetStreamer* AMDGPUAsmPrinter::getTargetStreamer() const {
110   if (!OutStreamer)
111     return nullptr;
112   return static_cast<AMDGPUTargetStreamer*>(OutStreamer->getTargetStreamer());
113 }
114 
115 void AMDGPUAsmPrinter::emitStartOfAsmFile(Module &M) {
116   if (IsaInfo::hasCodeObjectV3(getGlobalSTI())) {
117     std::string ExpectedTarget;
118     raw_string_ostream ExpectedTargetOS(ExpectedTarget);
119     IsaInfo::streamIsaVersion(getGlobalSTI(), ExpectedTargetOS);
120 
121     getTargetStreamer()->EmitDirectiveAMDGCNTarget(ExpectedTarget);
122   }
123 
124   if (TM.getTargetTriple().getOS() != Triple::AMDHSA &&
125       TM.getTargetTriple().getOS() != Triple::AMDPAL)
126     return;
127 
128   if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
129     HSAMetadataStream->begin(M);
130 
131   if (TM.getTargetTriple().getOS() == Triple::AMDPAL)
132     getTargetStreamer()->getPALMetadata()->readFromIR(M);
133 
134   if (IsaInfo::hasCodeObjectV3(getGlobalSTI()))
135     return;
136 
137   // HSA emits NT_AMDGPU_HSA_CODE_OBJECT_VERSION for code objects v2.
138   if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
139     getTargetStreamer()->EmitDirectiveHSACodeObjectVersion(2, 1);
140 
141   // HSA and PAL emit NT_AMDGPU_HSA_ISA for code objects v2.
142   IsaVersion Version = getIsaVersion(getGlobalSTI()->getCPU());
143   getTargetStreamer()->EmitDirectiveHSACodeObjectISA(
144       Version.Major, Version.Minor, Version.Stepping, "AMD", "AMDGPU");
145 }
146 
147 void AMDGPUAsmPrinter::emitEndOfAsmFile(Module &M) {
148   // Following code requires TargetStreamer to be present.
149   if (!getTargetStreamer())
150     return;
151 
152   if (!IsaInfo::hasCodeObjectV3(getGlobalSTI())) {
153     // Emit ISA Version (NT_AMD_AMDGPU_ISA).
154     std::string ISAVersionString;
155     raw_string_ostream ISAVersionStream(ISAVersionString);
156     IsaInfo::streamIsaVersion(getGlobalSTI(), ISAVersionStream);
157     getTargetStreamer()->EmitISAVersion(ISAVersionStream.str());
158   }
159 
160   // Emit HSA Metadata (NT_AMD_AMDGPU_HSA_METADATA).
161   if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
162     HSAMetadataStream->end();
163     bool Success = HSAMetadataStream->emitTo(*getTargetStreamer());
164     (void)Success;
165     assert(Success && "Malformed HSA Metadata");
166   }
167 }
168 
169 bool AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough(
170   const MachineBasicBlock *MBB) const {
171   if (!AsmPrinter::isBlockOnlyReachableByFallthrough(MBB))
172     return false;
173 
174   if (MBB->empty())
175     return true;
176 
177   // If this is a block implementing a long branch, an expression relative to
178   // the start of the block is needed.  to the start of the block.
179   // XXX - Is there a smarter way to check this?
180   return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
181 }
182 
183 void AMDGPUAsmPrinter::emitFunctionBodyStart() {
184   const SIMachineFunctionInfo &MFI = *MF->getInfo<SIMachineFunctionInfo>();
185   if (!MFI.isEntryFunction())
186     return;
187 
188   const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
189   const Function &F = MF->getFunction();
190   if (!STM.hasCodeObjectV3() && STM.isAmdHsaOrMesa(F) &&
191       (F.getCallingConv() == CallingConv::AMDGPU_KERNEL ||
192        F.getCallingConv() == CallingConv::SPIR_KERNEL)) {
193     amd_kernel_code_t KernelCode;
194     getAmdKernelCode(KernelCode, CurrentProgramInfo, *MF);
195     getTargetStreamer()->EmitAMDKernelCodeT(KernelCode);
196   }
197 
198   if (STM.isAmdHsaOS())
199     HSAMetadataStream->emitKernel(*MF, CurrentProgramInfo);
200 }
201 
202 void AMDGPUAsmPrinter::emitFunctionBodyEnd() {
203   const SIMachineFunctionInfo &MFI = *MF->getInfo<SIMachineFunctionInfo>();
204   if (!MFI.isEntryFunction())
205     return;
206 
207   if (!IsaInfo::hasCodeObjectV3(getGlobalSTI()) ||
208       TM.getTargetTriple().getOS() != Triple::AMDHSA)
209     return;
210 
211   auto &Streamer = getTargetStreamer()->getStreamer();
212   auto &Context = Streamer.getContext();
213   auto &ObjectFileInfo = *Context.getObjectFileInfo();
214   auto &ReadOnlySection = *ObjectFileInfo.getReadOnlySection();
215 
216   Streamer.PushSection();
217   Streamer.SwitchSection(&ReadOnlySection);
218 
219   // CP microcode requires the kernel descriptor to be allocated on 64 byte
220   // alignment.
221   Streamer.emitValueToAlignment(64, 0, 1, 0);
222   if (ReadOnlySection.getAlignment() < 64)
223     ReadOnlySection.setAlignment(Align(64));
224 
225   const MCSubtargetInfo &STI = MF->getSubtarget();
226 
227   SmallString<128> KernelName;
228   getNameWithPrefix(KernelName, &MF->getFunction());
229   getTargetStreamer()->EmitAmdhsaKernelDescriptor(
230       STI, KernelName, getAmdhsaKernelDescriptor(*MF, CurrentProgramInfo),
231       CurrentProgramInfo.NumVGPRsForWavesPerEU,
232       CurrentProgramInfo.NumSGPRsForWavesPerEU -
233           IsaInfo::getNumExtraSGPRs(&STI,
234                                     CurrentProgramInfo.VCCUsed,
235                                     CurrentProgramInfo.FlatUsed),
236       CurrentProgramInfo.VCCUsed, CurrentProgramInfo.FlatUsed,
237       hasXNACK(STI));
238 
239   Streamer.PopSection();
240 }
241 
242 void AMDGPUAsmPrinter::emitFunctionEntryLabel() {
243   if (IsaInfo::hasCodeObjectV3(getGlobalSTI()) &&
244       TM.getTargetTriple().getOS() == Triple::AMDHSA) {
245     AsmPrinter::emitFunctionEntryLabel();
246     return;
247   }
248 
249   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
250   const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
251   if (MFI->isEntryFunction() && STM.isAmdHsaOrMesa(MF->getFunction())) {
252     SmallString<128> SymbolName;
253     getNameWithPrefix(SymbolName, &MF->getFunction()),
254     getTargetStreamer()->EmitAMDGPUSymbolType(
255         SymbolName, ELF::STT_AMDGPU_HSA_KERNEL);
256   }
257   if (DumpCodeInstEmitter) {
258     // Disassemble function name label to text.
259     DisasmLines.push_back(MF->getName().str() + ":");
260     DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size());
261     HexLines.push_back("");
262   }
263 
264   AsmPrinter::emitFunctionEntryLabel();
265 }
266 
267 void AMDGPUAsmPrinter::emitBasicBlockStart(const MachineBasicBlock &MBB) {
268   if (DumpCodeInstEmitter && !isBlockOnlyReachableByFallthrough(&MBB)) {
269     // Write a line for the basic block label if it is not only fallthrough.
270     DisasmLines.push_back(
271         (Twine("BB") + Twine(getFunctionNumber())
272          + "_" + Twine(MBB.getNumber()) + ":").str());
273     DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size());
274     HexLines.push_back("");
275   }
276   AsmPrinter::emitBasicBlockStart(MBB);
277 }
278 
279 void AMDGPUAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) {
280   if (GV->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) {
281     if (GV->hasInitializer() && !isa<UndefValue>(GV->getInitializer())) {
282       OutContext.reportError({},
283                              Twine(GV->getName()) +
284                                  ": unsupported initializer for address space");
285       return;
286     }
287 
288     // LDS variables aren't emitted in HSA or PAL yet.
289     const Triple::OSType OS = TM.getTargetTriple().getOS();
290     if (OS == Triple::AMDHSA || OS == Triple::AMDPAL)
291       return;
292 
293     MCSymbol *GVSym = getSymbol(GV);
294 
295     GVSym->redefineIfPossible();
296     if (GVSym->isDefined() || GVSym->isVariable())
297       report_fatal_error("symbol '" + Twine(GVSym->getName()) +
298                          "' is already defined");
299 
300     const DataLayout &DL = GV->getParent()->getDataLayout();
301     uint64_t Size = DL.getTypeAllocSize(GV->getValueType());
302     unsigned Align = GV->getAlignment();
303     if (!Align)
304       Align = 4;
305 
306     emitVisibility(GVSym, GV->getVisibility(), !GV->isDeclaration());
307     emitLinkage(GV, GVSym);
308     if (auto TS = getTargetStreamer())
309       TS->emitAMDGPULDS(GVSym, Size, Align);
310     return;
311   }
312 
313   AsmPrinter::emitGlobalVariable(GV);
314 }
315 
316 bool AMDGPUAsmPrinter::doFinalization(Module &M) {
317   CallGraphResourceInfo.clear();
318 
319   // Pad with s_code_end to help tools and guard against instruction prefetch
320   // causing stale data in caches. Arguably this should be done by the linker,
321   // which is why this isn't done for Mesa.
322   const MCSubtargetInfo &STI = *getGlobalSTI();
323   if (AMDGPU::isGFX10(STI) &&
324       (STI.getTargetTriple().getOS() == Triple::AMDHSA ||
325        STI.getTargetTriple().getOS() == Triple::AMDPAL)) {
326     OutStreamer->SwitchSection(getObjFileLowering().getTextSection());
327     getTargetStreamer()->EmitCodeEnd();
328   }
329 
330   return AsmPrinter::doFinalization(M);
331 }
332 
333 // Print comments that apply to both callable functions and entry points.
334 void AMDGPUAsmPrinter::emitCommonFunctionComments(
335   uint32_t NumVGPR,
336   Optional<uint32_t> NumAGPR,
337   uint32_t TotalNumVGPR,
338   uint32_t NumSGPR,
339   uint64_t ScratchSize,
340   uint64_t CodeSize,
341   const AMDGPUMachineFunction *MFI) {
342   OutStreamer->emitRawComment(" codeLenInByte = " + Twine(CodeSize), false);
343   OutStreamer->emitRawComment(" NumSgprs: " + Twine(NumSGPR), false);
344   OutStreamer->emitRawComment(" NumVgprs: " + Twine(NumVGPR), false);
345   if (NumAGPR) {
346     OutStreamer->emitRawComment(" NumAgprs: " + Twine(*NumAGPR), false);
347     OutStreamer->emitRawComment(" TotalNumVgprs: " + Twine(TotalNumVGPR),
348                                 false);
349   }
350   OutStreamer->emitRawComment(" ScratchSize: " + Twine(ScratchSize), false);
351   OutStreamer->emitRawComment(" MemoryBound: " + Twine(MFI->isMemoryBound()),
352                               false);
353 }
354 
355 uint16_t AMDGPUAsmPrinter::getAmdhsaKernelCodeProperties(
356     const MachineFunction &MF) const {
357   const SIMachineFunctionInfo &MFI = *MF.getInfo<SIMachineFunctionInfo>();
358   uint16_t KernelCodeProperties = 0;
359 
360   if (MFI.hasPrivateSegmentBuffer()) {
361     KernelCodeProperties |=
362         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
363   }
364   if (MFI.hasDispatchPtr()) {
365     KernelCodeProperties |=
366         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
367   }
368   if (MFI.hasQueuePtr()) {
369     KernelCodeProperties |=
370         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
371   }
372   if (MFI.hasKernargSegmentPtr()) {
373     KernelCodeProperties |=
374         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
375   }
376   if (MFI.hasDispatchID()) {
377     KernelCodeProperties |=
378         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
379   }
380   if (MFI.hasFlatScratchInit()) {
381     KernelCodeProperties |=
382         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
383   }
384   if (MF.getSubtarget<GCNSubtarget>().isWave32()) {
385     KernelCodeProperties |=
386         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32;
387   }
388 
389   return KernelCodeProperties;
390 }
391 
392 amdhsa::kernel_descriptor_t AMDGPUAsmPrinter::getAmdhsaKernelDescriptor(
393     const MachineFunction &MF,
394     const SIProgramInfo &PI) const {
395   amdhsa::kernel_descriptor_t KernelDescriptor;
396   memset(&KernelDescriptor, 0x0, sizeof(KernelDescriptor));
397 
398   assert(isUInt<32>(PI.ScratchSize));
399   assert(isUInt<32>(PI.ComputePGMRSrc1));
400   assert(isUInt<32>(PI.ComputePGMRSrc2));
401 
402   KernelDescriptor.group_segment_fixed_size = PI.LDSSize;
403   KernelDescriptor.private_segment_fixed_size = PI.ScratchSize;
404   KernelDescriptor.compute_pgm_rsrc1 = PI.ComputePGMRSrc1;
405   KernelDescriptor.compute_pgm_rsrc2 = PI.ComputePGMRSrc2;
406   KernelDescriptor.kernel_code_properties = getAmdhsaKernelCodeProperties(MF);
407 
408   return KernelDescriptor;
409 }
410 
411 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
412   CurrentProgramInfo = SIProgramInfo();
413 
414   const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
415 
416   // The starting address of all shader programs must be 256 bytes aligned.
417   // Regular functions just need the basic required instruction alignment.
418   MF.setAlignment(MFI->isEntryFunction() ? Align(256) : Align(4));
419 
420   SetupMachineFunction(MF);
421 
422   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
423   MCContext &Context = getObjFileLowering().getContext();
424   // FIXME: This should be an explicit check for Mesa.
425   if (!STM.isAmdHsaOS() && !STM.isAmdPalOS()) {
426     MCSectionELF *ConfigSection =
427         Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
428     OutStreamer->SwitchSection(ConfigSection);
429   }
430 
431   if (MFI->isEntryFunction()) {
432     getSIProgramInfo(CurrentProgramInfo, MF);
433   } else {
434     auto I = CallGraphResourceInfo.insert(
435       std::make_pair(&MF.getFunction(), SIFunctionResourceInfo()));
436     SIFunctionResourceInfo &Info = I.first->second;
437     assert(I.second && "should only be called once per function");
438     Info = analyzeResourceUsage(MF);
439   }
440 
441   if (STM.isAmdPalOS())
442     EmitPALMetadata(MF, CurrentProgramInfo);
443   else if (!STM.isAmdHsaOS()) {
444     EmitProgramInfoSI(MF, CurrentProgramInfo);
445   }
446 
447   DumpCodeInstEmitter = nullptr;
448   if (STM.dumpCode()) {
449     // For -dumpcode, get the assembler out of the streamer, even if it does
450     // not really want to let us have it. This only works with -filetype=obj.
451     bool SaveFlag = OutStreamer->getUseAssemblerInfoForParsing();
452     OutStreamer->setUseAssemblerInfoForParsing(true);
453     MCAssembler *Assembler = OutStreamer->getAssemblerPtr();
454     OutStreamer->setUseAssemblerInfoForParsing(SaveFlag);
455     if (Assembler)
456       DumpCodeInstEmitter = Assembler->getEmitterPtr();
457   }
458 
459   DisasmLines.clear();
460   HexLines.clear();
461   DisasmLineMaxLen = 0;
462 
463   emitFunctionBody();
464 
465   if (isVerbose()) {
466     MCSectionELF *CommentSection =
467         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
468     OutStreamer->SwitchSection(CommentSection);
469 
470     if (!MFI->isEntryFunction()) {
471       OutStreamer->emitRawComment(" Function info:", false);
472       SIFunctionResourceInfo &Info = CallGraphResourceInfo[&MF.getFunction()];
473       emitCommonFunctionComments(
474         Info.NumVGPR,
475         STM.hasMAIInsts() ? Info.NumAGPR : Optional<uint32_t>(),
476         Info.getTotalNumVGPRs(STM),
477         Info.getTotalNumSGPRs(MF.getSubtarget<GCNSubtarget>()),
478         Info.PrivateSegmentSize,
479         getFunctionCodeSize(MF), MFI);
480       return false;
481     }
482 
483     OutStreamer->emitRawComment(" Kernel info:", false);
484     emitCommonFunctionComments(CurrentProgramInfo.NumArchVGPR,
485                                STM.hasMAIInsts()
486                                  ? CurrentProgramInfo.NumAccVGPR
487                                  : Optional<uint32_t>(),
488                                CurrentProgramInfo.NumVGPR,
489                                CurrentProgramInfo.NumSGPR,
490                                CurrentProgramInfo.ScratchSize,
491                                getFunctionCodeSize(MF), MFI);
492 
493     OutStreamer->emitRawComment(
494       " FloatMode: " + Twine(CurrentProgramInfo.FloatMode), false);
495     OutStreamer->emitRawComment(
496       " IeeeMode: " + Twine(CurrentProgramInfo.IEEEMode), false);
497     OutStreamer->emitRawComment(
498       " LDSByteSize: " + Twine(CurrentProgramInfo.LDSSize) +
499       " bytes/workgroup (compile time only)", false);
500 
501     OutStreamer->emitRawComment(
502       " SGPRBlocks: " + Twine(CurrentProgramInfo.SGPRBlocks), false);
503     OutStreamer->emitRawComment(
504       " VGPRBlocks: " + Twine(CurrentProgramInfo.VGPRBlocks), false);
505 
506     OutStreamer->emitRawComment(
507       " NumSGPRsForWavesPerEU: " +
508       Twine(CurrentProgramInfo.NumSGPRsForWavesPerEU), false);
509     OutStreamer->emitRawComment(
510       " NumVGPRsForWavesPerEU: " +
511       Twine(CurrentProgramInfo.NumVGPRsForWavesPerEU), false);
512 
513     OutStreamer->emitRawComment(
514       " Occupancy: " +
515       Twine(CurrentProgramInfo.Occupancy), false);
516 
517     OutStreamer->emitRawComment(
518       " WaveLimiterHint : " + Twine(MFI->needsWaveLimiter()), false);
519 
520     OutStreamer->emitRawComment(
521       " COMPUTE_PGM_RSRC2:USER_SGPR: " +
522       Twine(G_00B84C_USER_SGPR(CurrentProgramInfo.ComputePGMRSrc2)), false);
523     OutStreamer->emitRawComment(
524       " COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
525       Twine(G_00B84C_TRAP_HANDLER(CurrentProgramInfo.ComputePGMRSrc2)), false);
526     OutStreamer->emitRawComment(
527       " COMPUTE_PGM_RSRC2:TGID_X_EN: " +
528       Twine(G_00B84C_TGID_X_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
529     OutStreamer->emitRawComment(
530       " COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
531       Twine(G_00B84C_TGID_Y_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
532     OutStreamer->emitRawComment(
533       " COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
534       Twine(G_00B84C_TGID_Z_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
535     OutStreamer->emitRawComment(
536       " COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
537       Twine(G_00B84C_TIDIG_COMP_CNT(CurrentProgramInfo.ComputePGMRSrc2)),
538       false);
539   }
540 
541   if (DumpCodeInstEmitter) {
542 
543     OutStreamer->SwitchSection(
544         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_PROGBITS, 0));
545 
546     for (size_t i = 0; i < DisasmLines.size(); ++i) {
547       std::string Comment = "\n";
548       if (!HexLines[i].empty()) {
549         Comment = std::string(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
550         Comment += " ; " + HexLines[i] + "\n";
551       }
552 
553       OutStreamer->emitBytes(StringRef(DisasmLines[i]));
554       OutStreamer->emitBytes(StringRef(Comment));
555     }
556   }
557 
558   return false;
559 }
560 
561 uint64_t AMDGPUAsmPrinter::getFunctionCodeSize(const MachineFunction &MF) const {
562   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
563   const SIInstrInfo *TII = STM.getInstrInfo();
564 
565   uint64_t CodeSize = 0;
566 
567   for (const MachineBasicBlock &MBB : MF) {
568     for (const MachineInstr &MI : MBB) {
569       // TODO: CodeSize should account for multiple functions.
570 
571       // TODO: Should we count size of debug info?
572       if (MI.isDebugInstr())
573         continue;
574 
575       CodeSize += TII->getInstSizeInBytes(MI);
576     }
577   }
578 
579   return CodeSize;
580 }
581 
582 static bool hasAnyNonFlatUseOfReg(const MachineRegisterInfo &MRI,
583                                   const SIInstrInfo &TII,
584                                   unsigned Reg) {
585   for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) {
586     if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent()))
587       return true;
588   }
589 
590   return false;
591 }
592 
593 int32_t AMDGPUAsmPrinter::SIFunctionResourceInfo::getTotalNumSGPRs(
594   const GCNSubtarget &ST) const {
595   return NumExplicitSGPR + IsaInfo::getNumExtraSGPRs(&ST,
596                                                      UsesVCC, UsesFlatScratch);
597 }
598 
599 int32_t AMDGPUAsmPrinter::SIFunctionResourceInfo::getTotalNumVGPRs(
600   const GCNSubtarget &ST) const {
601   return std::max(NumVGPR, NumAGPR);
602 }
603 
604 static const Function *getCalleeFunction(const MachineOperand &Op) {
605   if (Op.isImm()) {
606     assert(Op.getImm() == 0);
607     return nullptr;
608   }
609 
610   return cast<Function>(Op.getGlobal());
611 }
612 
613 AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
614   const MachineFunction &MF) const {
615   SIFunctionResourceInfo Info;
616 
617   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
618   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
619   const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
620   const MachineRegisterInfo &MRI = MF.getRegInfo();
621   const SIInstrInfo *TII = ST.getInstrInfo();
622   const SIRegisterInfo &TRI = TII->getRegisterInfo();
623 
624   Info.UsesFlatScratch = MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_LO) ||
625                          MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_HI);
626 
627   // Even if FLAT_SCRATCH is implicitly used, it has no effect if flat
628   // instructions aren't used to access the scratch buffer. Inline assembly may
629   // need it though.
630   //
631   // If we only have implicit uses of flat_scr on flat instructions, it is not
632   // really needed.
633   if (Info.UsesFlatScratch && !MFI->hasFlatScratchInit() &&
634       (!hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR) &&
635        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_LO) &&
636        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_HI))) {
637     Info.UsesFlatScratch = false;
638   }
639 
640   Info.HasDynamicallySizedStack = FrameInfo.hasVarSizedObjects();
641   Info.PrivateSegmentSize = FrameInfo.getStackSize();
642   if (MFI->isStackRealigned())
643     Info.PrivateSegmentSize += FrameInfo.getMaxAlign().value();
644 
645   Info.UsesVCC = MRI.isPhysRegUsed(AMDGPU::VCC_LO) ||
646                  MRI.isPhysRegUsed(AMDGPU::VCC_HI);
647 
648   // If there are no calls, MachineRegisterInfo can tell us the used register
649   // count easily.
650   // A tail call isn't considered a call for MachineFrameInfo's purposes.
651   if (!FrameInfo.hasCalls() && !FrameInfo.hasTailCall()) {
652     MCPhysReg HighestVGPRReg = AMDGPU::NoRegister;
653     for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) {
654       if (MRI.isPhysRegUsed(Reg)) {
655         HighestVGPRReg = Reg;
656         break;
657       }
658     }
659 
660     if (ST.hasMAIInsts()) {
661       MCPhysReg HighestAGPRReg = AMDGPU::NoRegister;
662       for (MCPhysReg Reg : reverse(AMDGPU::AGPR_32RegClass.getRegisters())) {
663         if (MRI.isPhysRegUsed(Reg)) {
664           HighestAGPRReg = Reg;
665           break;
666         }
667       }
668       Info.NumAGPR = HighestAGPRReg == AMDGPU::NoRegister ? 0 :
669         TRI.getHWRegIndex(HighestAGPRReg) + 1;
670     }
671 
672     MCPhysReg HighestSGPRReg = AMDGPU::NoRegister;
673     for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) {
674       if (MRI.isPhysRegUsed(Reg)) {
675         HighestSGPRReg = Reg;
676         break;
677       }
678     }
679 
680     // We found the maximum register index. They start at 0, so add one to get the
681     // number of registers.
682     Info.NumVGPR = HighestVGPRReg == AMDGPU::NoRegister ? 0 :
683       TRI.getHWRegIndex(HighestVGPRReg) + 1;
684     Info.NumExplicitSGPR = HighestSGPRReg == AMDGPU::NoRegister ? 0 :
685       TRI.getHWRegIndex(HighestSGPRReg) + 1;
686 
687     return Info;
688   }
689 
690   int32_t MaxVGPR = -1;
691   int32_t MaxAGPR = -1;
692   int32_t MaxSGPR = -1;
693   uint64_t CalleeFrameSize = 0;
694 
695   for (const MachineBasicBlock &MBB : MF) {
696     for (const MachineInstr &MI : MBB) {
697       // TODO: Check regmasks? Do they occur anywhere except calls?
698       for (const MachineOperand &MO : MI.operands()) {
699         unsigned Width = 0;
700         bool IsSGPR = false;
701         bool IsAGPR = false;
702 
703         if (!MO.isReg())
704           continue;
705 
706         Register Reg = MO.getReg();
707         switch (Reg) {
708         case AMDGPU::EXEC:
709         case AMDGPU::EXEC_LO:
710         case AMDGPU::EXEC_HI:
711         case AMDGPU::SCC:
712         case AMDGPU::M0:
713         case AMDGPU::SRC_SHARED_BASE:
714         case AMDGPU::SRC_SHARED_LIMIT:
715         case AMDGPU::SRC_PRIVATE_BASE:
716         case AMDGPU::SRC_PRIVATE_LIMIT:
717         case AMDGPU::SGPR_NULL:
718           continue;
719 
720         case AMDGPU::SRC_POPS_EXITING_WAVE_ID:
721           llvm_unreachable("src_pops_exiting_wave_id should not be used");
722 
723         case AMDGPU::NoRegister:
724           assert(MI.isDebugInstr());
725           continue;
726 
727         case AMDGPU::VCC:
728         case AMDGPU::VCC_LO:
729         case AMDGPU::VCC_HI:
730           Info.UsesVCC = true;
731           continue;
732 
733         case AMDGPU::FLAT_SCR:
734         case AMDGPU::FLAT_SCR_LO:
735         case AMDGPU::FLAT_SCR_HI:
736           continue;
737 
738         case AMDGPU::XNACK_MASK:
739         case AMDGPU::XNACK_MASK_LO:
740         case AMDGPU::XNACK_MASK_HI:
741           llvm_unreachable("xnack_mask registers should not be used");
742 
743         case AMDGPU::LDS_DIRECT:
744           llvm_unreachable("lds_direct register should not be used");
745 
746         case AMDGPU::TBA:
747         case AMDGPU::TBA_LO:
748         case AMDGPU::TBA_HI:
749         case AMDGPU::TMA:
750         case AMDGPU::TMA_LO:
751         case AMDGPU::TMA_HI:
752           llvm_unreachable("trap handler registers should not be used");
753 
754         case AMDGPU::SRC_VCCZ:
755           llvm_unreachable("src_vccz register should not be used");
756 
757         case AMDGPU::SRC_EXECZ:
758           llvm_unreachable("src_execz register should not be used");
759 
760         case AMDGPU::SRC_SCC:
761           llvm_unreachable("src_scc register should not be used");
762 
763         default:
764           break;
765         }
766 
767         if (AMDGPU::SReg_32RegClass.contains(Reg)) {
768           assert(!AMDGPU::TTMP_32RegClass.contains(Reg) &&
769                  "trap handler registers should not be used");
770           IsSGPR = true;
771           Width = 1;
772         } else if (AMDGPU::VGPR_32RegClass.contains(Reg)) {
773           IsSGPR = false;
774           Width = 1;
775         } else if (AMDGPU::AGPR_32RegClass.contains(Reg)) {
776           IsSGPR = false;
777           IsAGPR = true;
778           Width = 1;
779         } else if (AMDGPU::SReg_64RegClass.contains(Reg)) {
780           assert(!AMDGPU::TTMP_64RegClass.contains(Reg) &&
781                  "trap handler registers should not be used");
782           IsSGPR = true;
783           Width = 2;
784         } else if (AMDGPU::VReg_64RegClass.contains(Reg)) {
785           IsSGPR = false;
786           Width = 2;
787         } else if (AMDGPU::AReg_64RegClass.contains(Reg)) {
788           IsSGPR = false;
789           IsAGPR = true;
790           Width = 2;
791         } else if (AMDGPU::VReg_96RegClass.contains(Reg)) {
792           IsSGPR = false;
793           Width = 3;
794         } else if (AMDGPU::SReg_96RegClass.contains(Reg)) {
795           IsSGPR = true;
796           Width = 3;
797         } else if (AMDGPU::SReg_128RegClass.contains(Reg)) {
798           assert(!AMDGPU::TTMP_128RegClass.contains(Reg) &&
799             "trap handler registers should not be used");
800           IsSGPR = true;
801           Width = 4;
802         } else if (AMDGPU::VReg_128RegClass.contains(Reg)) {
803           IsSGPR = false;
804           Width = 4;
805         } else if (AMDGPU::AReg_128RegClass.contains(Reg)) {
806           IsSGPR = false;
807           IsAGPR = true;
808           Width = 4;
809         } else if (AMDGPU::VReg_160RegClass.contains(Reg)) {
810           IsSGPR = false;
811           Width = 5;
812         } else if (AMDGPU::SReg_160RegClass.contains(Reg)) {
813           IsSGPR = true;
814           Width = 5;
815         } else if (AMDGPU::SReg_256RegClass.contains(Reg)) {
816           assert(!AMDGPU::TTMP_256RegClass.contains(Reg) &&
817             "trap handler registers should not be used");
818           IsSGPR = true;
819           Width = 8;
820         } else if (AMDGPU::VReg_256RegClass.contains(Reg)) {
821           IsSGPR = false;
822           Width = 8;
823         } else if (AMDGPU::SReg_512RegClass.contains(Reg)) {
824           assert(!AMDGPU::TTMP_512RegClass.contains(Reg) &&
825             "trap handler registers should not be used");
826           IsSGPR = true;
827           Width = 16;
828         } else if (AMDGPU::VReg_512RegClass.contains(Reg)) {
829           IsSGPR = false;
830           Width = 16;
831         } else if (AMDGPU::AReg_512RegClass.contains(Reg)) {
832           IsSGPR = false;
833           IsAGPR = true;
834           Width = 16;
835         } else if (AMDGPU::SReg_1024RegClass.contains(Reg)) {
836           IsSGPR = true;
837           Width = 32;
838         } else if (AMDGPU::VReg_1024RegClass.contains(Reg)) {
839           IsSGPR = false;
840           Width = 32;
841         } else if (AMDGPU::AReg_1024RegClass.contains(Reg)) {
842           IsSGPR = false;
843           IsAGPR = true;
844           Width = 32;
845         } else {
846           llvm_unreachable("Unknown register class");
847         }
848         unsigned HWReg = TRI.getHWRegIndex(Reg);
849         int MaxUsed = HWReg + Width - 1;
850         if (IsSGPR) {
851           MaxSGPR = MaxUsed > MaxSGPR ? MaxUsed : MaxSGPR;
852         } else if (IsAGPR) {
853           MaxAGPR = MaxUsed > MaxAGPR ? MaxUsed : MaxAGPR;
854         } else {
855           MaxVGPR = MaxUsed > MaxVGPR ? MaxUsed : MaxVGPR;
856         }
857       }
858 
859       if (MI.isCall()) {
860         // Pseudo used just to encode the underlying global. Is there a better
861         // way to track this?
862 
863         const MachineOperand *CalleeOp
864           = TII->getNamedOperand(MI, AMDGPU::OpName::callee);
865 
866         const Function *Callee = getCalleeFunction(*CalleeOp);
867         if (!Callee || Callee->isDeclaration()) {
868           // If this is a call to an external function, we can't do much. Make
869           // conservative guesses.
870 
871           // 48 SGPRs - vcc, - flat_scr, -xnack
872           int MaxSGPRGuess =
873             47 - IsaInfo::getNumExtraSGPRs(&ST, true, ST.hasFlatAddressSpace());
874           MaxSGPR = std::max(MaxSGPR, MaxSGPRGuess);
875           MaxVGPR = std::max(MaxVGPR, 23);
876           MaxAGPR = std::max(MaxAGPR, 23);
877 
878           CalleeFrameSize = std::max(CalleeFrameSize, UINT64_C(16384));
879           Info.UsesVCC = true;
880           Info.UsesFlatScratch = ST.hasFlatAddressSpace();
881           Info.HasDynamicallySizedStack = true;
882         } else {
883           // We force CodeGen to run in SCC order, so the callee's register
884           // usage etc. should be the cumulative usage of all callees.
885 
886           auto I = CallGraphResourceInfo.find(Callee);
887           if (I == CallGraphResourceInfo.end()) {
888             // Avoid crashing on undefined behavior with an illegal call to a
889             // kernel. If a callsite's calling convention doesn't match the
890             // function's, it's undefined behavior. If the callsite calling
891             // convention does match, that would have errored earlier.
892             // FIXME: The verifier shouldn't allow this.
893             if (AMDGPU::isEntryFunctionCC(Callee->getCallingConv()))
894               report_fatal_error("invalid call to entry function");
895 
896             llvm_unreachable("callee should have been handled before caller");
897           }
898 
899           MaxSGPR = std::max(I->second.NumExplicitSGPR - 1, MaxSGPR);
900           MaxVGPR = std::max(I->second.NumVGPR - 1, MaxVGPR);
901           MaxAGPR = std::max(I->second.NumAGPR - 1, MaxAGPR);
902           CalleeFrameSize
903             = std::max(I->second.PrivateSegmentSize, CalleeFrameSize);
904           Info.UsesVCC |= I->second.UsesVCC;
905           Info.UsesFlatScratch |= I->second.UsesFlatScratch;
906           Info.HasDynamicallySizedStack |= I->second.HasDynamicallySizedStack;
907           Info.HasRecursion |= I->second.HasRecursion;
908         }
909 
910         // FIXME: Call site could have norecurse on it
911         if (!Callee || !Callee->doesNotRecurse())
912           Info.HasRecursion = true;
913       }
914     }
915   }
916 
917   Info.NumExplicitSGPR = MaxSGPR + 1;
918   Info.NumVGPR = MaxVGPR + 1;
919   Info.NumAGPR = MaxAGPR + 1;
920   Info.PrivateSegmentSize += CalleeFrameSize;
921 
922   return Info;
923 }
924 
925 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
926                                         const MachineFunction &MF) {
927   SIFunctionResourceInfo Info = analyzeResourceUsage(MF);
928   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
929 
930   ProgInfo.NumArchVGPR = Info.NumVGPR;
931   ProgInfo.NumAccVGPR = Info.NumAGPR;
932   ProgInfo.NumVGPR = Info.getTotalNumVGPRs(STM);
933   ProgInfo.NumSGPR = Info.NumExplicitSGPR;
934   ProgInfo.ScratchSize = Info.PrivateSegmentSize;
935   ProgInfo.VCCUsed = Info.UsesVCC;
936   ProgInfo.FlatUsed = Info.UsesFlatScratch;
937   ProgInfo.DynamicCallStack = Info.HasDynamicallySizedStack || Info.HasRecursion;
938 
939   if (!isUInt<32>(ProgInfo.ScratchSize)) {
940     DiagnosticInfoStackSize DiagStackSize(MF.getFunction(),
941                                           ProgInfo.ScratchSize, DS_Error);
942     MF.getFunction().getContext().diagnose(DiagStackSize);
943   }
944 
945   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
946 
947   // TODO(scott.linder): The calculations related to SGPR/VGPR blocks are
948   // duplicated in part in AMDGPUAsmParser::calculateGPRBlocks, and could be
949   // unified.
950   unsigned ExtraSGPRs = IsaInfo::getNumExtraSGPRs(
951       &STM, ProgInfo.VCCUsed, ProgInfo.FlatUsed);
952 
953   // Check the addressable register limit before we add ExtraSGPRs.
954   if (STM.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
955       !STM.hasSGPRInitBug()) {
956     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
957     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
958       // This can happen due to a compiler bug or when using inline asm.
959       LLVMContext &Ctx = MF.getFunction().getContext();
960       DiagnosticInfoResourceLimit Diag(MF.getFunction(),
961                                        "addressable scalar registers",
962                                        ProgInfo.NumSGPR, DS_Error,
963                                        DK_ResourceLimit,
964                                        MaxAddressableNumSGPRs);
965       Ctx.diagnose(Diag);
966       ProgInfo.NumSGPR = MaxAddressableNumSGPRs - 1;
967     }
968   }
969 
970   // Account for extra SGPRs and VGPRs reserved for debugger use.
971   ProgInfo.NumSGPR += ExtraSGPRs;
972 
973   // Ensure there are enough SGPRs and VGPRs for wave dispatch, where wave
974   // dispatch registers are function args.
975   unsigned WaveDispatchNumSGPR = 0, WaveDispatchNumVGPR = 0;
976   for (auto &Arg : MF.getFunction().args()) {
977     unsigned NumRegs = (Arg.getType()->getPrimitiveSizeInBits() + 31) / 32;
978     if (Arg.hasAttribute(Attribute::InReg))
979       WaveDispatchNumSGPR += NumRegs;
980     else
981       WaveDispatchNumVGPR += NumRegs;
982   }
983   ProgInfo.NumSGPR = std::max(ProgInfo.NumSGPR, WaveDispatchNumSGPR);
984   ProgInfo.NumVGPR = std::max(ProgInfo.NumVGPR, WaveDispatchNumVGPR);
985 
986   // Adjust number of registers used to meet default/requested minimum/maximum
987   // number of waves per execution unit request.
988   ProgInfo.NumSGPRsForWavesPerEU = std::max(
989     std::max(ProgInfo.NumSGPR, 1u), STM.getMinNumSGPRs(MFI->getMaxWavesPerEU()));
990   ProgInfo.NumVGPRsForWavesPerEU = std::max(
991     std::max(ProgInfo.NumVGPR, 1u), STM.getMinNumVGPRs(MFI->getMaxWavesPerEU()));
992 
993   if (STM.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ||
994       STM.hasSGPRInitBug()) {
995     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
996     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
997       // This can happen due to a compiler bug or when using inline asm to use
998       // the registers which are usually reserved for vcc etc.
999       LLVMContext &Ctx = MF.getFunction().getContext();
1000       DiagnosticInfoResourceLimit Diag(MF.getFunction(),
1001                                        "scalar registers",
1002                                        ProgInfo.NumSGPR, DS_Error,
1003                                        DK_ResourceLimit,
1004                                        MaxAddressableNumSGPRs);
1005       Ctx.diagnose(Diag);
1006       ProgInfo.NumSGPR = MaxAddressableNumSGPRs;
1007       ProgInfo.NumSGPRsForWavesPerEU = MaxAddressableNumSGPRs;
1008     }
1009   }
1010 
1011   if (STM.hasSGPRInitBug()) {
1012     ProgInfo.NumSGPR =
1013         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
1014     ProgInfo.NumSGPRsForWavesPerEU =
1015         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
1016   }
1017 
1018   if (MFI->getNumUserSGPRs() > STM.getMaxNumUserSGPRs()) {
1019     LLVMContext &Ctx = MF.getFunction().getContext();
1020     DiagnosticInfoResourceLimit Diag(MF.getFunction(), "user SGPRs",
1021                                      MFI->getNumUserSGPRs(), DS_Error);
1022     Ctx.diagnose(Diag);
1023   }
1024 
1025   if (MFI->getLDSSize() > static_cast<unsigned>(STM.getLocalMemorySize())) {
1026     LLVMContext &Ctx = MF.getFunction().getContext();
1027     DiagnosticInfoResourceLimit Diag(MF.getFunction(), "local memory",
1028                                      MFI->getLDSSize(), DS_Error);
1029     Ctx.diagnose(Diag);
1030   }
1031 
1032   ProgInfo.SGPRBlocks = IsaInfo::getNumSGPRBlocks(
1033       &STM, ProgInfo.NumSGPRsForWavesPerEU);
1034   ProgInfo.VGPRBlocks = IsaInfo::getNumVGPRBlocks(
1035       &STM, ProgInfo.NumVGPRsForWavesPerEU);
1036 
1037   const SIModeRegisterDefaults Mode = MFI->getMode();
1038 
1039   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
1040   // register.
1041   ProgInfo.FloatMode = getFPMode(Mode);
1042 
1043   ProgInfo.IEEEMode = Mode.IEEE;
1044 
1045   // Make clamp modifier on NaN input returns 0.
1046   ProgInfo.DX10Clamp = Mode.DX10Clamp;
1047 
1048   unsigned LDSAlignShift;
1049   if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
1050     // LDS is allocated in 64 dword blocks.
1051     LDSAlignShift = 8;
1052   } else {
1053     // LDS is allocated in 128 dword blocks.
1054     LDSAlignShift = 9;
1055   }
1056 
1057   unsigned LDSSpillSize =
1058     MFI->getLDSWaveSpillSize() * MFI->getMaxFlatWorkGroupSize();
1059 
1060   ProgInfo.LDSSize = MFI->getLDSSize() + LDSSpillSize;
1061   ProgInfo.LDSBlocks =
1062       alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
1063 
1064   // Scratch is allocated in 256 dword blocks.
1065   unsigned ScratchAlignShift = 10;
1066   // We need to program the hardware with the amount of scratch memory that
1067   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
1068   // scratch memory used per thread.
1069   ProgInfo.ScratchBlocks =
1070       alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
1071               1ULL << ScratchAlignShift) >>
1072       ScratchAlignShift;
1073 
1074   if (getIsaVersion(getGlobalSTI()->getCPU()).Major >= 10) {
1075     ProgInfo.WgpMode = STM.isCuModeEnabled() ? 0 : 1;
1076     ProgInfo.MemOrdered = 1;
1077   }
1078 
1079   ProgInfo.ComputePGMRSrc1 =
1080       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
1081       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
1082       S_00B848_PRIORITY(ProgInfo.Priority) |
1083       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
1084       S_00B848_PRIV(ProgInfo.Priv) |
1085       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
1086       S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
1087       S_00B848_IEEE_MODE(ProgInfo.IEEEMode) |
1088       S_00B848_WGP_MODE(ProgInfo.WgpMode) |
1089       S_00B848_MEM_ORDERED(ProgInfo.MemOrdered);
1090 
1091   // 0 = X, 1 = XY, 2 = XYZ
1092   unsigned TIDIGCompCnt = 0;
1093   if (MFI->hasWorkItemIDZ())
1094     TIDIGCompCnt = 2;
1095   else if (MFI->hasWorkItemIDY())
1096     TIDIGCompCnt = 1;
1097 
1098   ProgInfo.ComputePGMRSrc2 =
1099       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
1100       S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
1101       // For AMDHSA, TRAP_HANDLER must be zero, as it is populated by the CP.
1102       S_00B84C_TRAP_HANDLER(STM.isAmdHsaOS() ? 0 : STM.isTrapHandlerEnabled()) |
1103       S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
1104       S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
1105       S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
1106       S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
1107       S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
1108       S_00B84C_EXCP_EN_MSB(0) |
1109       // For AMDHSA, LDS_SIZE must be zero, as it is populated by the CP.
1110       S_00B84C_LDS_SIZE(STM.isAmdHsaOS() ? 0 : ProgInfo.LDSBlocks) |
1111       S_00B84C_EXCP_EN(0);
1112 
1113   ProgInfo.Occupancy = STM.computeOccupancy(MF, ProgInfo.LDSSize,
1114                                             ProgInfo.NumSGPRsForWavesPerEU,
1115                                             ProgInfo.NumVGPRsForWavesPerEU);
1116 }
1117 
1118 static unsigned getRsrcReg(CallingConv::ID CallConv) {
1119   switch (CallConv) {
1120   default: LLVM_FALLTHROUGH;
1121   case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
1122   case CallingConv::AMDGPU_LS: return R_00B528_SPI_SHADER_PGM_RSRC1_LS;
1123   case CallingConv::AMDGPU_HS: return R_00B428_SPI_SHADER_PGM_RSRC1_HS;
1124   case CallingConv::AMDGPU_ES: return R_00B328_SPI_SHADER_PGM_RSRC1_ES;
1125   case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
1126   case CallingConv::AMDGPU_VS: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
1127   case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
1128   }
1129 }
1130 
1131 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
1132                                          const SIProgramInfo &CurrentProgramInfo) {
1133   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1134   unsigned RsrcReg = getRsrcReg(MF.getFunction().getCallingConv());
1135 
1136   if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
1137     OutStreamer->emitInt32(R_00B848_COMPUTE_PGM_RSRC1);
1138 
1139     OutStreamer->emitInt32(CurrentProgramInfo.ComputePGMRSrc1);
1140 
1141     OutStreamer->emitInt32(R_00B84C_COMPUTE_PGM_RSRC2);
1142     OutStreamer->emitInt32(CurrentProgramInfo.ComputePGMRSrc2);
1143 
1144     OutStreamer->emitInt32(R_00B860_COMPUTE_TMPRING_SIZE);
1145     OutStreamer->emitInt32(S_00B860_WAVESIZE(CurrentProgramInfo.ScratchBlocks));
1146 
1147     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
1148     // 0" comment but I don't see a corresponding field in the register spec.
1149   } else {
1150     OutStreamer->emitInt32(RsrcReg);
1151     OutStreamer->emitIntValue(S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
1152                               S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks), 4);
1153     OutStreamer->emitInt32(R_0286E8_SPI_TMPRING_SIZE);
1154     OutStreamer->emitIntValue(
1155         S_0286E8_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
1156   }
1157 
1158   if (MF.getFunction().getCallingConv() == CallingConv::AMDGPU_PS) {
1159     OutStreamer->emitInt32(R_00B02C_SPI_SHADER_PGM_RSRC2_PS);
1160     OutStreamer->emitInt32(
1161         S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks));
1162     OutStreamer->emitInt32(R_0286CC_SPI_PS_INPUT_ENA);
1163     OutStreamer->emitInt32(MFI->getPSInputEnable());
1164     OutStreamer->emitInt32(R_0286D0_SPI_PS_INPUT_ADDR);
1165     OutStreamer->emitInt32(MFI->getPSInputAddr());
1166   }
1167 
1168   OutStreamer->emitInt32(R_SPILLED_SGPRS);
1169   OutStreamer->emitInt32(MFI->getNumSpilledSGPRs());
1170   OutStreamer->emitInt32(R_SPILLED_VGPRS);
1171   OutStreamer->emitInt32(MFI->getNumSpilledVGPRs());
1172 }
1173 
1174 // This is the equivalent of EmitProgramInfoSI above, but for when the OS type
1175 // is AMDPAL.  It stores each compute/SPI register setting and other PAL
1176 // metadata items into the PALMD::Metadata, combining with any provided by the
1177 // frontend as LLVM metadata. Once all functions are written, the PAL metadata
1178 // is then written as a single block in the .note section.
1179 void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
1180        const SIProgramInfo &CurrentProgramInfo) {
1181   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1182   auto CC = MF.getFunction().getCallingConv();
1183   auto MD = getTargetStreamer()->getPALMetadata();
1184 
1185   MD->setEntryPoint(CC, MF.getFunction().getName());
1186   MD->setNumUsedVgprs(CC, CurrentProgramInfo.NumVGPRsForWavesPerEU);
1187   MD->setNumUsedSgprs(CC, CurrentProgramInfo.NumSGPRsForWavesPerEU);
1188   if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
1189     MD->setRsrc1(CC, CurrentProgramInfo.ComputePGMRSrc1);
1190     MD->setRsrc2(CC, CurrentProgramInfo.ComputePGMRSrc2);
1191   } else {
1192     MD->setRsrc1(CC, S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
1193         S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks));
1194     if (CurrentProgramInfo.ScratchBlocks > 0)
1195       MD->setRsrc2(CC, S_00B84C_SCRATCH_EN(1));
1196   }
1197   // ScratchSize is in bytes, 16 aligned.
1198   MD->setScratchSize(CC, alignTo(CurrentProgramInfo.ScratchSize, 16));
1199   if (MF.getFunction().getCallingConv() == CallingConv::AMDGPU_PS) {
1200     MD->setRsrc2(CC, S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks));
1201     MD->setSpiPsInputEna(MFI->getPSInputEnable());
1202     MD->setSpiPsInputAddr(MFI->getPSInputAddr());
1203   }
1204 
1205   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
1206   if (STM.isWave32())
1207     MD->setWave32(MF.getFunction().getCallingConv());
1208 }
1209 
1210 // This is supposed to be log2(Size)
1211 static amd_element_byte_size_t getElementByteSizeValue(unsigned Size) {
1212   switch (Size) {
1213   case 4:
1214     return AMD_ELEMENT_4_BYTES;
1215   case 8:
1216     return AMD_ELEMENT_8_BYTES;
1217   case 16:
1218     return AMD_ELEMENT_16_BYTES;
1219   default:
1220     llvm_unreachable("invalid private_element_size");
1221   }
1222 }
1223 
1224 void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out,
1225                                         const SIProgramInfo &CurrentProgramInfo,
1226                                         const MachineFunction &MF) const {
1227   const Function &F = MF.getFunction();
1228   assert(F.getCallingConv() == CallingConv::AMDGPU_KERNEL ||
1229          F.getCallingConv() == CallingConv::SPIR_KERNEL);
1230 
1231   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1232   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
1233 
1234   AMDGPU::initDefaultAMDKernelCodeT(Out, &STM);
1235 
1236   Out.compute_pgm_resource_registers =
1237       CurrentProgramInfo.ComputePGMRSrc1 |
1238       (CurrentProgramInfo.ComputePGMRSrc2 << 32);
1239   Out.code_properties |= AMD_CODE_PROPERTY_IS_PTR64;
1240 
1241   if (CurrentProgramInfo.DynamicCallStack)
1242     Out.code_properties |= AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK;
1243 
1244   AMD_HSA_BITS_SET(Out.code_properties,
1245                    AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE,
1246                    getElementByteSizeValue(STM.getMaxPrivateElementSize()));
1247 
1248   if (MFI->hasPrivateSegmentBuffer()) {
1249     Out.code_properties |=
1250       AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
1251   }
1252 
1253   if (MFI->hasDispatchPtr())
1254     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
1255 
1256   if (MFI->hasQueuePtr())
1257     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
1258 
1259   if (MFI->hasKernargSegmentPtr())
1260     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
1261 
1262   if (MFI->hasDispatchID())
1263     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
1264 
1265   if (MFI->hasFlatScratchInit())
1266     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
1267 
1268   if (MFI->hasDispatchPtr())
1269     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
1270 
1271   if (STM.isXNACKEnabled())
1272     Out.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED;
1273 
1274   Align MaxKernArgAlign;
1275   Out.kernarg_segment_byte_size = STM.getKernArgSegmentSize(F, MaxKernArgAlign);
1276   Out.wavefront_sgpr_count = CurrentProgramInfo.NumSGPR;
1277   Out.workitem_vgpr_count = CurrentProgramInfo.NumVGPR;
1278   Out.workitem_private_segment_byte_size = CurrentProgramInfo.ScratchSize;
1279   Out.workgroup_group_segment_byte_size = CurrentProgramInfo.LDSSize;
1280 
1281   // kernarg_segment_alignment is specified as log of the alignment.
1282   // The minimum alignment is 16.
1283   Out.kernarg_segment_alignment = Log2(std::max(Align(16), MaxKernArgAlign));
1284 }
1285 
1286 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
1287                                        const char *ExtraCode, raw_ostream &O) {
1288   // First try the generic code, which knows about modifiers like 'c' and 'n'.
1289   if (!AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, O))
1290     return false;
1291 
1292   if (ExtraCode && ExtraCode[0]) {
1293     if (ExtraCode[1] != 0)
1294       return true; // Unknown modifier.
1295 
1296     switch (ExtraCode[0]) {
1297     case 'r':
1298       break;
1299     default:
1300       return true;
1301     }
1302   }
1303 
1304   // TODO: Should be able to support other operand types like globals.
1305   const MachineOperand &MO = MI->getOperand(OpNo);
1306   if (MO.isReg()) {
1307     AMDGPUInstPrinter::printRegOperand(MO.getReg(), O,
1308                                        *MF->getSubtarget().getRegisterInfo());
1309     return false;
1310   }
1311 
1312   return true;
1313 }
1314