1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
15 //
16 //===----------------------------------------------------------------------===//
17 //
18 
19 #include "AMDGPUAsmPrinter.h"
20 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
21 #include "InstPrinter/AMDGPUInstPrinter.h"
22 #include "Utils/AMDGPUBaseInfo.h"
23 #include "AMDGPU.h"
24 #include "AMDKernelCodeT.h"
25 #include "AMDGPUSubtarget.h"
26 #include "R600Defines.h"
27 #include "R600MachineFunctionInfo.h"
28 #include "R600RegisterInfo.h"
29 #include "SIDefines.h"
30 #include "SIMachineFunctionInfo.h"
31 #include "SIInstrInfo.h"
32 #include "SIRegisterInfo.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/IR/DiagnosticInfo.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCSectionELF.h"
37 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/Support/ELF.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Target/TargetLoweringObjectFile.h"
42 
43 using namespace llvm;
44 
45 // TODO: This should get the default rounding mode from the kernel. We just set
46 // the default here, but this could change if the OpenCL rounding mode pragmas
47 // are used.
48 //
49 // The denormal mode here should match what is reported by the OpenCL runtime
50 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
51 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
52 //
53 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
54 // precision, and leaves single precision to flush all and does not report
55 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
56 // CL_FP_DENORM for both.
57 //
58 // FIXME: It seems some instructions do not support single precision denormals
59 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
60 // and sin_f32, cos_f32 on most parts).
61 
62 // We want to use these instructions, and using fp32 denormals also causes
63 // instructions to run at the double precision rate for the device so it's
64 // probably best to just report no single precision denormals.
65 static uint32_t getFPMode(const MachineFunction &F) {
66   const SISubtarget& ST = F.getSubtarget<SISubtarget>();
67   // TODO: Is there any real use for the flush in only / flush out only modes?
68 
69   uint32_t FP32Denormals =
70     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
71 
72   uint32_t FP64Denormals =
73     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
74 
75   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
76          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
77          FP_DENORM_MODE_SP(FP32Denormals) |
78          FP_DENORM_MODE_DP(FP64Denormals);
79 }
80 
81 static AsmPrinter *
82 createAMDGPUAsmPrinterPass(TargetMachine &tm,
83                            std::unique_ptr<MCStreamer> &&Streamer) {
84   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
85 }
86 
87 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
88   TargetRegistry::RegisterAsmPrinter(getTheAMDGPUTarget(),
89                                      createAMDGPUAsmPrinterPass);
90   TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(),
91                                      createAMDGPUAsmPrinterPass);
92 }
93 
94 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
95                                    std::unique_ptr<MCStreamer> Streamer)
96   : AsmPrinter(TM, std::move(Streamer)) {}
97 
98 StringRef AMDGPUAsmPrinter::getPassName() const {
99   return "AMDGPU Assembly Printer";
100 }
101 
102 void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) {
103   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
104     return;
105 
106   AMDGPUTargetStreamer *TS =
107       static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
108 
109   TS->EmitDirectiveHSACodeObjectVersion(2, 1);
110 
111   const MCSubtargetInfo *STI = TM.getMCSubtargetInfo();
112   AMDGPU::IsaInfo::IsaVersion ISA =
113       AMDGPU::IsaInfo::getIsaVersion(STI->getFeatureBits());
114   TS->EmitDirectiveHSACodeObjectISA(ISA.Major, ISA.Minor, ISA.Stepping,
115                                     "AMD", "AMDGPU");
116 
117   // Emit runtime metadata.
118   TS->EmitRuntimeMetadata(STI->getFeatureBits(), M);
119 }
120 
121 bool AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough(
122   const MachineBasicBlock *MBB) const {
123   if (!AsmPrinter::isBlockOnlyReachableByFallthrough(MBB))
124     return false;
125 
126   if (MBB->empty())
127     return true;
128 
129   // If this is a block implementing a long branch, an expression relative to
130   // the start of the block is needed.  to the start of the block.
131   // XXX - Is there a smarter way to check this?
132   return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
133 }
134 
135 
136 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
137   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
138   SIProgramInfo KernelInfo;
139   if (STM.isAmdCodeObjectV2(*MF)) {
140     getSIProgramInfo(KernelInfo, *MF);
141     EmitAmdKernelCodeT(*MF, KernelInfo);
142   }
143 }
144 
145 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
146   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
147   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
148   if (MFI->isKernel() && STM.isAmdCodeObjectV2(*MF)) {
149     AMDGPUTargetStreamer *TS =
150         static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
151     SmallString<128> SymbolName;
152     getNameWithPrefix(SymbolName, MF->getFunction()),
153     TS->EmitAMDGPUSymbolType(SymbolName, ELF::STT_AMDGPU_HSA_KERNEL);
154   }
155 
156   AsmPrinter::EmitFunctionEntryLabel();
157 }
158 
159 void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
160 
161   // Group segment variables aren't emitted in HSA.
162   if (AMDGPU::isGroupSegment(GV))
163     return;
164 
165   AsmPrinter::EmitGlobalVariable(GV);
166 }
167 
168 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
169 
170   // The starting address of all shader programs must be 256 bytes aligned.
171   MF.setAlignment(8);
172 
173   SetupMachineFunction(MF);
174 
175   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
176   MCContext &Context = getObjFileLowering().getContext();
177   if (!STM.isAmdHsaOS()) {
178     MCSectionELF *ConfigSection =
179         Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
180     OutStreamer->SwitchSection(ConfigSection);
181   }
182 
183   SIProgramInfo KernelInfo;
184   if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
185     getSIProgramInfo(KernelInfo, MF);
186     if (!STM.isAmdHsaOS()) {
187       EmitProgramInfoSI(MF, KernelInfo);
188     }
189   } else {
190     EmitProgramInfoR600(MF);
191   }
192 
193   DisasmLines.clear();
194   HexLines.clear();
195   DisasmLineMaxLen = 0;
196 
197   EmitFunctionBody();
198 
199   if (isVerbose()) {
200     MCSectionELF *CommentSection =
201         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
202     OutStreamer->SwitchSection(CommentSection);
203 
204     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
205       OutStreamer->emitRawComment(" Kernel info:", false);
206       OutStreamer->emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
207                                   false);
208       OutStreamer->emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
209                                   false);
210       OutStreamer->emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
211                                   false);
212       OutStreamer->emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
213                                   false);
214       OutStreamer->emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
215                                   false);
216       OutStreamer->emitRawComment(" ScratchSize: " + Twine(KernelInfo.ScratchSize),
217                                   false);
218       OutStreamer->emitRawComment(" LDSByteSize: " + Twine(KernelInfo.LDSSize) +
219                                   " bytes/workgroup (compile time only)", false);
220 
221       OutStreamer->emitRawComment(" SGPRBlocks: " +
222                                   Twine(KernelInfo.SGPRBlocks), false);
223       OutStreamer->emitRawComment(" VGPRBlocks: " +
224                                   Twine(KernelInfo.VGPRBlocks), false);
225 
226       OutStreamer->emitRawComment(" NumSGPRsForWavesPerEU: " +
227                                   Twine(KernelInfo.NumSGPRsForWavesPerEU), false);
228       OutStreamer->emitRawComment(" NumVGPRsForWavesPerEU: " +
229                                   Twine(KernelInfo.NumVGPRsForWavesPerEU), false);
230 
231       OutStreamer->emitRawComment(" ReservedVGPRFirst: " + Twine(KernelInfo.ReservedVGPRFirst),
232                                   false);
233       OutStreamer->emitRawComment(" ReservedVGPRCount: " + Twine(KernelInfo.ReservedVGPRCount),
234                                   false);
235 
236       if (MF.getSubtarget<SISubtarget>().debuggerEmitPrologue()) {
237         OutStreamer->emitRawComment(" DebuggerWavefrontPrivateSegmentOffsetSGPR: s" +
238                                     Twine(KernelInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR), false);
239         OutStreamer->emitRawComment(" DebuggerPrivateSegmentBufferSGPR: s" +
240                                     Twine(KernelInfo.DebuggerPrivateSegmentBufferSGPR), false);
241       }
242 
243       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:USER_SGPR: " +
244                                   Twine(G_00B84C_USER_SGPR(KernelInfo.ComputePGMRSrc2)),
245                                   false);
246       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
247                                   Twine(G_00B84C_TRAP_HANDLER(KernelInfo.ComputePGMRSrc2)),
248                                   false);
249       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_X_EN: " +
250                                   Twine(G_00B84C_TGID_X_EN(KernelInfo.ComputePGMRSrc2)),
251                                   false);
252       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
253                                   Twine(G_00B84C_TGID_Y_EN(KernelInfo.ComputePGMRSrc2)),
254                                   false);
255       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
256                                   Twine(G_00B84C_TGID_Z_EN(KernelInfo.ComputePGMRSrc2)),
257                                   false);
258       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
259                                   Twine(G_00B84C_TIDIG_COMP_CNT(KernelInfo.ComputePGMRSrc2)),
260                                   false);
261 
262     } else {
263       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
264       OutStreamer->emitRawComment(
265         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->CFStackSize)));
266     }
267   }
268 
269   if (STM.dumpCode()) {
270 
271     OutStreamer->SwitchSection(
272         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
273 
274     for (size_t i = 0; i < DisasmLines.size(); ++i) {
275       std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
276       Comment += " ; " + HexLines[i] + "\n";
277 
278       OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
279       OutStreamer->EmitBytes(StringRef(Comment));
280     }
281   }
282 
283   return false;
284 }
285 
286 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
287   unsigned MaxGPR = 0;
288   bool killPixel = false;
289   const R600Subtarget &STM = MF.getSubtarget<R600Subtarget>();
290   const R600RegisterInfo *RI = STM.getRegisterInfo();
291   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
292 
293   for (const MachineBasicBlock &MBB : MF) {
294     for (const MachineInstr &MI : MBB) {
295       if (MI.getOpcode() == AMDGPU::KILLGT)
296         killPixel = true;
297       unsigned numOperands = MI.getNumOperands();
298       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
299         const MachineOperand &MO = MI.getOperand(op_idx);
300         if (!MO.isReg())
301           continue;
302         unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
303 
304         // Register with value > 127 aren't GPR
305         if (HWReg > 127)
306           continue;
307         MaxGPR = std::max(MaxGPR, HWReg);
308       }
309     }
310   }
311 
312   unsigned RsrcReg;
313   if (STM.getGeneration() >= R600Subtarget::EVERGREEN) {
314     // Evergreen / Northern Islands
315     switch (MF.getFunction()->getCallingConv()) {
316     default: LLVM_FALLTHROUGH;
317     case CallingConv::AMDGPU_CS: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
318     case CallingConv::AMDGPU_GS: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
319     case CallingConv::AMDGPU_PS: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
320     case CallingConv::AMDGPU_VS: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
321     }
322   } else {
323     // R600 / R700
324     switch (MF.getFunction()->getCallingConv()) {
325     default: LLVM_FALLTHROUGH;
326     case CallingConv::AMDGPU_GS: LLVM_FALLTHROUGH;
327     case CallingConv::AMDGPU_CS: LLVM_FALLTHROUGH;
328     case CallingConv::AMDGPU_VS: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
329     case CallingConv::AMDGPU_PS: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
330     }
331   }
332 
333   OutStreamer->EmitIntValue(RsrcReg, 4);
334   OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
335                            S_STACK_SIZE(MFI->CFStackSize), 4);
336   OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
337   OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
338 
339   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
340     OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
341     OutStreamer->EmitIntValue(alignTo(MFI->getLDSSize(), 4) >> 2, 4);
342   }
343 }
344 
345 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
346                                         const MachineFunction &MF) const {
347   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
348   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
349   uint64_t CodeSize = 0;
350   unsigned MaxSGPR = 0;
351   unsigned MaxVGPR = 0;
352   bool VCCUsed = false;
353   bool FlatUsed = false;
354   const SIRegisterInfo *RI = STM.getRegisterInfo();
355   const SIInstrInfo *TII = STM.getInstrInfo();
356 
357   for (const MachineBasicBlock &MBB : MF) {
358     for (const MachineInstr &MI : MBB) {
359       // TODO: CodeSize should account for multiple functions.
360 
361       // TODO: Should we count size of debug info?
362       if (MI.isDebugValue())
363         continue;
364 
365       if (isVerbose())
366         CodeSize += TII->getInstSizeInBytes(MI);
367 
368       unsigned numOperands = MI.getNumOperands();
369       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
370         const MachineOperand &MO = MI.getOperand(op_idx);
371         unsigned width = 0;
372         bool isSGPR = false;
373 
374         if (!MO.isReg())
375           continue;
376 
377         unsigned reg = MO.getReg();
378         switch (reg) {
379         case AMDGPU::EXEC:
380         case AMDGPU::EXEC_LO:
381         case AMDGPU::EXEC_HI:
382         case AMDGPU::SCC:
383         case AMDGPU::M0:
384           continue;
385 
386         case AMDGPU::VCC:
387         case AMDGPU::VCC_LO:
388         case AMDGPU::VCC_HI:
389           VCCUsed = true;
390           continue;
391 
392         case AMDGPU::FLAT_SCR:
393         case AMDGPU::FLAT_SCR_LO:
394         case AMDGPU::FLAT_SCR_HI:
395           // Even if FLAT_SCRATCH is implicitly used, it has no effect if flat
396           // instructions aren't used to access the scratch buffer.
397           if (MFI->hasFlatScratchInit())
398             FlatUsed = true;
399           continue;
400 
401         case AMDGPU::TBA:
402         case AMDGPU::TBA_LO:
403         case AMDGPU::TBA_HI:
404         case AMDGPU::TMA:
405         case AMDGPU::TMA_LO:
406         case AMDGPU::TMA_HI:
407           llvm_unreachable("trap handler registers should not be used");
408 
409         default:
410           break;
411         }
412 
413         if (AMDGPU::SReg_32RegClass.contains(reg)) {
414           assert(!AMDGPU::TTMP_32RegClass.contains(reg) &&
415                  "trap handler registers should not be used");
416           isSGPR = true;
417           width = 1;
418         } else if (AMDGPU::VGPR_32RegClass.contains(reg)) {
419           isSGPR = false;
420           width = 1;
421         } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
422           assert(!AMDGPU::TTMP_64RegClass.contains(reg) &&
423                  "trap handler registers should not be used");
424           isSGPR = true;
425           width = 2;
426         } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
427           isSGPR = false;
428           width = 2;
429         } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
430           isSGPR = false;
431           width = 3;
432         } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
433           isSGPR = true;
434           width = 4;
435         } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
436           isSGPR = false;
437           width = 4;
438         } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
439           isSGPR = true;
440           width = 8;
441         } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
442           isSGPR = false;
443           width = 8;
444         } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
445           isSGPR = true;
446           width = 16;
447         } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
448           isSGPR = false;
449           width = 16;
450         } else {
451           llvm_unreachable("Unknown register class");
452         }
453         unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
454         unsigned maxUsed = hwReg + width - 1;
455         if (isSGPR) {
456           MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
457         } else {
458           MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
459         }
460       }
461     }
462   }
463 
464   unsigned ExtraSGPRs = 0;
465 
466   if (VCCUsed)
467     ExtraSGPRs = 2;
468 
469   if (STM.getGeneration() < SISubtarget::VOLCANIC_ISLANDS) {
470     if (FlatUsed)
471       ExtraSGPRs = 4;
472   } else {
473     if (STM.isXNACKEnabled())
474       ExtraSGPRs = 4;
475 
476     if (FlatUsed)
477       ExtraSGPRs = 6;
478   }
479 
480   unsigned ExtraVGPRs = STM.getReservedNumVGPRs(MF);
481 
482   // Check the addressable register limit before we add ExtraSGPRs.
483   if (STM.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
484       !STM.hasSGPRInitBug()) {
485     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
486     if (MaxSGPR + 1 > MaxAddressableNumSGPRs) {
487       // This can happen due to a compiler bug or when using inline asm.
488       LLVMContext &Ctx = MF.getFunction()->getContext();
489       DiagnosticInfoResourceLimit Diag(*MF.getFunction(),
490                                        "addressable scalar registers",
491                                        MaxSGPR + 1, DS_Error,
492                                        DK_ResourceLimit,
493                                        MaxAddressableNumSGPRs);
494       Ctx.diagnose(Diag);
495       MaxSGPR = MaxAddressableNumSGPRs - 1;
496     }
497   }
498 
499   // Account for extra SGPRs and VGPRs reserved for debugger use.
500   MaxSGPR += ExtraSGPRs;
501   MaxVGPR += ExtraVGPRs;
502 
503   // We found the maximum register index. They start at 0, so add one to get the
504   // number of registers.
505   ProgInfo.NumSGPR = MaxSGPR + 1;
506   ProgInfo.NumVGPR = MaxVGPR + 1;
507 
508   // Adjust number of registers used to meet default/requested minimum/maximum
509   // number of waves per execution unit request.
510   ProgInfo.NumSGPRsForWavesPerEU = std::max(
511     ProgInfo.NumSGPR, STM.getMinNumSGPRs(MFI->getMaxWavesPerEU()));
512   ProgInfo.NumVGPRsForWavesPerEU = std::max(
513     ProgInfo.NumVGPR, STM.getMinNumVGPRs(MFI->getMaxWavesPerEU()));
514 
515   if (STM.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ||
516       STM.hasSGPRInitBug()) {
517     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
518     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
519       // This can happen due to a compiler bug or when using inline asm to use
520       // the registers which are usually reserved for vcc etc.
521       LLVMContext &Ctx = MF.getFunction()->getContext();
522       DiagnosticInfoResourceLimit Diag(*MF.getFunction(),
523                                        "scalar registers",
524                                        ProgInfo.NumSGPR, DS_Error,
525                                        DK_ResourceLimit,
526                                        MaxAddressableNumSGPRs);
527       Ctx.diagnose(Diag);
528       ProgInfo.NumSGPR = MaxAddressableNumSGPRs;
529       ProgInfo.NumSGPRsForWavesPerEU = MaxAddressableNumSGPRs;
530     }
531   }
532 
533   if (STM.hasSGPRInitBug()) {
534     ProgInfo.NumSGPR =
535         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
536     ProgInfo.NumSGPRsForWavesPerEU =
537         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
538   }
539 
540   if (MFI->NumUserSGPRs > STM.getMaxNumUserSGPRs()) {
541     LLVMContext &Ctx = MF.getFunction()->getContext();
542     DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "user SGPRs",
543                                      MFI->NumUserSGPRs, DS_Error);
544     Ctx.diagnose(Diag);
545   }
546 
547   if (MFI->getLDSSize() > static_cast<unsigned>(STM.getLocalMemorySize())) {
548     LLVMContext &Ctx = MF.getFunction()->getContext();
549     DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "local memory",
550                                      MFI->getLDSSize(), DS_Error);
551     Ctx.diagnose(Diag);
552   }
553 
554   // SGPRBlocks is actual number of SGPR blocks minus 1.
555   ProgInfo.SGPRBlocks = alignTo(ProgInfo.NumSGPRsForWavesPerEU,
556                                 STM.getSGPREncodingGranule());
557   ProgInfo.SGPRBlocks = ProgInfo.SGPRBlocks / STM.getSGPREncodingGranule() - 1;
558 
559   // VGPRBlocks is actual number of VGPR blocks minus 1.
560   ProgInfo.VGPRBlocks = alignTo(ProgInfo.NumVGPRsForWavesPerEU,
561                                 STM.getVGPREncodingGranule());
562   ProgInfo.VGPRBlocks = ProgInfo.VGPRBlocks / STM.getVGPREncodingGranule() - 1;
563 
564   // Record first reserved VGPR and number of reserved VGPRs.
565   ProgInfo.ReservedVGPRFirst = STM.debuggerReserveRegs() ? MaxVGPR + 1 : 0;
566   ProgInfo.ReservedVGPRCount = STM.getReservedNumVGPRs(MF);
567 
568   // Update DebuggerWavefrontPrivateSegmentOffsetSGPR and
569   // DebuggerPrivateSegmentBufferSGPR fields if "amdgpu-debugger-emit-prologue"
570   // attribute was requested.
571   if (STM.debuggerEmitPrologue()) {
572     ProgInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR =
573       RI->getHWRegIndex(MFI->getScratchWaveOffsetReg());
574     ProgInfo.DebuggerPrivateSegmentBufferSGPR =
575       RI->getHWRegIndex(MFI->getScratchRSrcReg());
576   }
577 
578   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
579   // register.
580   ProgInfo.FloatMode = getFPMode(MF);
581 
582   ProgInfo.IEEEMode = STM.enableIEEEBit(MF);
583 
584   // Make clamp modifier on NaN input returns 0.
585   ProgInfo.DX10Clamp = 1;
586 
587   const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
588   ProgInfo.ScratchSize = FrameInfo.getStackSize();
589 
590   ProgInfo.FlatUsed = FlatUsed;
591   ProgInfo.VCCUsed = VCCUsed;
592   ProgInfo.CodeLen = CodeSize;
593 
594   unsigned LDSAlignShift;
595   if (STM.getGeneration() < SISubtarget::SEA_ISLANDS) {
596     // LDS is allocated in 64 dword blocks.
597     LDSAlignShift = 8;
598   } else {
599     // LDS is allocated in 128 dword blocks.
600     LDSAlignShift = 9;
601   }
602 
603   unsigned LDSSpillSize =
604     MFI->LDSWaveSpillSize * MFI->getMaxFlatWorkGroupSize();
605 
606   ProgInfo.LDSSize = MFI->getLDSSize() + LDSSpillSize;
607   ProgInfo.LDSBlocks =
608       alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
609 
610   // Scratch is allocated in 256 dword blocks.
611   unsigned ScratchAlignShift = 10;
612   // We need to program the hardware with the amount of scratch memory that
613   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
614   // scratch memory used per thread.
615   ProgInfo.ScratchBlocks =
616       alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
617               1ULL << ScratchAlignShift) >>
618       ScratchAlignShift;
619 
620   ProgInfo.ComputePGMRSrc1 =
621       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
622       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
623       S_00B848_PRIORITY(ProgInfo.Priority) |
624       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
625       S_00B848_PRIV(ProgInfo.Priv) |
626       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
627       S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
628       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
629 
630   // 0 = X, 1 = XY, 2 = XYZ
631   unsigned TIDIGCompCnt = 0;
632   if (MFI->hasWorkItemIDZ())
633     TIDIGCompCnt = 2;
634   else if (MFI->hasWorkItemIDY())
635     TIDIGCompCnt = 1;
636 
637   ProgInfo.ComputePGMRSrc2 =
638       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
639       S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
640       S_00B84C_TRAP_HANDLER(STM.isTrapHandlerEnabled()) |
641       S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
642       S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
643       S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
644       S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
645       S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
646       S_00B84C_EXCP_EN_MSB(0) |
647       S_00B84C_LDS_SIZE(ProgInfo.LDSBlocks) |
648       S_00B84C_EXCP_EN(0);
649 }
650 
651 static unsigned getRsrcReg(CallingConv::ID CallConv) {
652   switch (CallConv) {
653   default: LLVM_FALLTHROUGH;
654   case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
655   case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
656   case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
657   case CallingConv::AMDGPU_VS: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
658   }
659 }
660 
661 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
662                                          const SIProgramInfo &KernelInfo) {
663   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
664   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
665   unsigned RsrcReg = getRsrcReg(MF.getFunction()->getCallingConv());
666 
667   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
668     OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
669 
670     OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc1, 4);
671 
672     OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
673     OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc2, 4);
674 
675     OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
676     OutStreamer->EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4);
677 
678     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
679     // 0" comment but I don't see a corresponding field in the register spec.
680   } else {
681     OutStreamer->EmitIntValue(RsrcReg, 4);
682     OutStreamer->EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
683                               S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4);
684     if (STM.isVGPRSpillingEnabled(*MF.getFunction())) {
685       OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
686       OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(KernelInfo.ScratchBlocks), 4);
687     }
688   }
689 
690   if (MF.getFunction()->getCallingConv() == CallingConv::AMDGPU_PS) {
691     OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
692     OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4);
693     OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
694     OutStreamer->EmitIntValue(MFI->PSInputEna, 4);
695     OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
696     OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4);
697   }
698 
699   OutStreamer->EmitIntValue(R_SPILLED_SGPRS, 4);
700   OutStreamer->EmitIntValue(MFI->getNumSpilledSGPRs(), 4);
701   OutStreamer->EmitIntValue(R_SPILLED_VGPRS, 4);
702   OutStreamer->EmitIntValue(MFI->getNumSpilledVGPRs(), 4);
703 }
704 
705 // This is supposed to be log2(Size)
706 static amd_element_byte_size_t getElementByteSizeValue(unsigned Size) {
707   switch (Size) {
708   case 4:
709     return AMD_ELEMENT_4_BYTES;
710   case 8:
711     return AMD_ELEMENT_8_BYTES;
712   case 16:
713     return AMD_ELEMENT_16_BYTES;
714   default:
715     llvm_unreachable("invalid private_element_size");
716   }
717 }
718 
719 void AMDGPUAsmPrinter::EmitAmdKernelCodeT(const MachineFunction &MF,
720                                          const SIProgramInfo &KernelInfo) const {
721   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
722   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
723   amd_kernel_code_t header;
724 
725   AMDGPU::initDefaultAMDKernelCodeT(header, STM.getFeatureBits());
726 
727   header.compute_pgm_resource_registers =
728       KernelInfo.ComputePGMRSrc1 |
729       (KernelInfo.ComputePGMRSrc2 << 32);
730   header.code_properties = AMD_CODE_PROPERTY_IS_PTR64;
731 
732 
733   AMD_HSA_BITS_SET(header.code_properties,
734                    AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE,
735                    getElementByteSizeValue(STM.getMaxPrivateElementSize()));
736 
737   if (MFI->hasPrivateSegmentBuffer()) {
738     header.code_properties |=
739       AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
740   }
741 
742   if (MFI->hasDispatchPtr())
743     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
744 
745   if (MFI->hasQueuePtr())
746     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
747 
748   if (MFI->hasKernargSegmentPtr())
749     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
750 
751   if (MFI->hasDispatchID())
752     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
753 
754   if (MFI->hasFlatScratchInit())
755     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
756 
757   // TODO: Private segment size
758 
759   if (MFI->hasGridWorkgroupCountX()) {
760     header.code_properties |=
761       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X;
762   }
763 
764   if (MFI->hasGridWorkgroupCountY()) {
765     header.code_properties |=
766       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y;
767   }
768 
769   if (MFI->hasGridWorkgroupCountZ()) {
770     header.code_properties |=
771       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z;
772   }
773 
774   if (MFI->hasDispatchPtr())
775     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
776 
777   if (STM.debuggerSupported())
778     header.code_properties |= AMD_CODE_PROPERTY_IS_DEBUG_SUPPORTED;
779 
780   if (STM.isXNACKEnabled())
781     header.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED;
782 
783   // FIXME: Should use getKernArgSize
784   header.kernarg_segment_byte_size =
785     STM.getKernArgSegmentSize(MF, MFI->getABIArgOffset());
786   header.wavefront_sgpr_count = KernelInfo.NumSGPR;
787   header.workitem_vgpr_count = KernelInfo.NumVGPR;
788   header.workitem_private_segment_byte_size = KernelInfo.ScratchSize;
789   header.workgroup_group_segment_byte_size = KernelInfo.LDSSize;
790   header.reserved_vgpr_first = KernelInfo.ReservedVGPRFirst;
791   header.reserved_vgpr_count = KernelInfo.ReservedVGPRCount;
792 
793   // These alignment values are specified in powers of two, so alignment =
794   // 2^n.  The minimum alignment is 2^4 = 16.
795   header.kernarg_segment_alignment = std::max((size_t)4,
796       countTrailingZeros(MFI->getMaxKernArgAlign()));
797 
798   if (STM.debuggerEmitPrologue()) {
799     header.debug_wavefront_private_segment_offset_sgpr =
800       KernelInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR;
801     header.debug_private_segment_buffer_sgpr =
802       KernelInfo.DebuggerPrivateSegmentBufferSGPR;
803   }
804 
805   AMDGPUTargetStreamer *TS =
806       static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
807 
808   OutStreamer->SwitchSection(getObjFileLowering().getTextSection());
809   TS->EmitAMDKernelCodeT(header);
810 }
811 
812 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
813                                        unsigned AsmVariant,
814                                        const char *ExtraCode, raw_ostream &O) {
815   if (ExtraCode && ExtraCode[0]) {
816     if (ExtraCode[1] != 0)
817       return true; // Unknown modifier.
818 
819     switch (ExtraCode[0]) {
820     default:
821       // See if this is a generic print operand
822       return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
823     case 'r':
824       break;
825     }
826   }
827 
828   AMDGPUInstPrinter::printRegOperand(MI->getOperand(OpNo).getReg(), O,
829                    *TM.getSubtargetImpl(*MF->getFunction())->getRegisterInfo());
830   return false;
831 }
832