1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
15 //
16 //===----------------------------------------------------------------------===//
17 //
18 
19 #include "AMDGPUAsmPrinter.h"
20 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
21 #include "InstPrinter/AMDGPUInstPrinter.h"
22 #include "Utils/AMDGPUBaseInfo.h"
23 #include "AMDGPU.h"
24 #include "AMDKernelCodeT.h"
25 #include "AMDGPUSubtarget.h"
26 #include "R600Defines.h"
27 #include "R600MachineFunctionInfo.h"
28 #include "R600RegisterInfo.h"
29 #include "SIDefines.h"
30 #include "SIMachineFunctionInfo.h"
31 #include "SIRegisterInfo.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/MC/MCContext.h"
34 #include "llvm/MC/MCSectionELF.h"
35 #include "llvm/MC/MCStreamer.h"
36 #include "llvm/Support/ELF.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/TargetRegistry.h"
39 #include "llvm/Target/TargetLoweringObjectFile.h"
40 
41 using namespace llvm;
42 
43 // TODO: This should get the default rounding mode from the kernel. We just set
44 // the default here, but this could change if the OpenCL rounding mode pragmas
45 // are used.
46 //
47 // The denormal mode here should match what is reported by the OpenCL runtime
48 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
49 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
50 //
51 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
52 // precision, and leaves single precision to flush all and does not report
53 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
54 // CL_FP_DENORM for both.
55 //
56 // FIXME: It seems some instructions do not support single precision denormals
57 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
58 // and sin_f32, cos_f32 on most parts).
59 
60 // We want to use these instructions, and using fp32 denormals also causes
61 // instructions to run at the double precision rate for the device so it's
62 // probably best to just report no single precision denormals.
63 static uint32_t getFPMode(const MachineFunction &F) {
64   const AMDGPUSubtarget& ST = F.getSubtarget<AMDGPUSubtarget>();
65   // TODO: Is there any real use for the flush in only / flush out only modes?
66 
67   uint32_t FP32Denormals =
68     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
69 
70   uint32_t FP64Denormals =
71     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
72 
73   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
74          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
75          FP_DENORM_MODE_SP(FP32Denormals) |
76          FP_DENORM_MODE_DP(FP64Denormals);
77 }
78 
79 static AsmPrinter *
80 createAMDGPUAsmPrinterPass(TargetMachine &tm,
81                            std::unique_ptr<MCStreamer> &&Streamer) {
82   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
83 }
84 
85 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
86   TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
87   TargetRegistry::RegisterAsmPrinter(TheGCNTarget, createAMDGPUAsmPrinterPass);
88 }
89 
90 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
91                                    std::unique_ptr<MCStreamer> Streamer)
92     : AsmPrinter(TM, std::move(Streamer)) {}
93 
94 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
95   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
96   SIProgramInfo KernelInfo;
97   if (STM.isAmdHsaOS()) {
98     getSIProgramInfo(KernelInfo, *MF);
99     EmitAmdKernelCodeT(*MF, KernelInfo);
100   }
101 }
102 
103 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
104 
105   // This label is used to mark the end of the .text section.
106   const TargetLoweringObjectFile &TLOF = getObjFileLowering();
107   OutStreamer->SwitchSection(TLOF.getTextSection());
108   MCSymbol *EndOfTextLabel =
109       OutContext.getOrCreateSymbol(StringRef(END_OF_TEXT_LABEL_NAME));
110   OutStreamer->EmitLabel(EndOfTextLabel);
111 }
112 
113 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
114   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
115   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
116   if (MFI->isKernel() && STM.isAmdHsaOS()) {
117     AMDGPUTargetStreamer *TS =
118         static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
119     TS->EmitAMDGPUSymbolType(CurrentFnSym->getName(),
120                              ELF::STT_AMDGPU_HSA_KERNEL);
121   }
122 
123   AsmPrinter::EmitFunctionEntryLabel();
124 }
125 
126 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
127 
128   // The starting address of all shader programs must be 256 bytes aligned.
129   MF.setAlignment(8);
130 
131   SetupMachineFunction(MF);
132 
133   MCContext &Context = getObjFileLowering().getContext();
134   MCSectionELF *ConfigSection =
135       Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
136   OutStreamer->SwitchSection(ConfigSection);
137 
138   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
139   SIProgramInfo KernelInfo;
140   if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
141     getSIProgramInfo(KernelInfo, MF);
142     if (!STM.isAmdHsaOS()) {
143       EmitProgramInfoSI(MF, KernelInfo);
144     }
145     // Emit directives
146     AMDGPUTargetStreamer *TS =
147         static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
148     TS->EmitDirectiveHSACodeObjectVersion(1, 0);
149     AMDGPU::IsaVersion ISA = STM.getIsaVersion();
150     TS->EmitDirectiveHSACodeObjectISA(ISA.Major, ISA.Minor, ISA.Stepping,
151                                       "AMD", "AMDGPU");
152   } else {
153     EmitProgramInfoR600(MF);
154   }
155 
156   DisasmLines.clear();
157   HexLines.clear();
158   DisasmLineMaxLen = 0;
159 
160   EmitFunctionBody();
161 
162   if (isVerbose()) {
163     MCSectionELF *CommentSection =
164         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
165     OutStreamer->SwitchSection(CommentSection);
166 
167     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
168       OutStreamer->emitRawComment(" Kernel info:", false);
169       OutStreamer->emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
170                                   false);
171       OutStreamer->emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
172                                   false);
173       OutStreamer->emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
174                                   false);
175       OutStreamer->emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
176                                   false);
177       OutStreamer->emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
178                                   false);
179       OutStreamer->emitRawComment(" ScratchSize: " + Twine(KernelInfo.ScratchSize),
180                                   false);
181 
182       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:USER_SGPR: " +
183                                   Twine(G_00B84C_USER_SGPR(KernelInfo.ComputePGMRSrc2)),
184                                   false);
185       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_X_EN: " +
186                                   Twine(G_00B84C_TGID_X_EN(KernelInfo.ComputePGMRSrc2)),
187                                   false);
188       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
189                                   Twine(G_00B84C_TGID_Y_EN(KernelInfo.ComputePGMRSrc2)),
190                                   false);
191       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
192                                   Twine(G_00B84C_TGID_Z_EN(KernelInfo.ComputePGMRSrc2)),
193                                   false);
194       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
195                                   Twine(G_00B84C_TIDIG_COMP_CNT(KernelInfo.ComputePGMRSrc2)),
196                                   false);
197 
198     } else {
199       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
200       OutStreamer->emitRawComment(
201         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
202     }
203   }
204 
205   if (STM.dumpCode()) {
206 
207     OutStreamer->SwitchSection(
208         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
209 
210     for (size_t i = 0; i < DisasmLines.size(); ++i) {
211       std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
212       Comment += " ; " + HexLines[i] + "\n";
213 
214       OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
215       OutStreamer->EmitBytes(StringRef(Comment));
216     }
217   }
218 
219   return false;
220 }
221 
222 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
223   unsigned MaxGPR = 0;
224   bool killPixel = false;
225   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
226   const R600RegisterInfo *RI =
227       static_cast<const R600RegisterInfo *>(STM.getRegisterInfo());
228   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
229 
230   for (const MachineBasicBlock &MBB : MF) {
231     for (const MachineInstr &MI : MBB) {
232       if (MI.getOpcode() == AMDGPU::KILLGT)
233         killPixel = true;
234       unsigned numOperands = MI.getNumOperands();
235       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
236         const MachineOperand &MO = MI.getOperand(op_idx);
237         if (!MO.isReg())
238           continue;
239         unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
240 
241         // Register with value > 127 aren't GPR
242         if (HWReg > 127)
243           continue;
244         MaxGPR = std::max(MaxGPR, HWReg);
245       }
246     }
247   }
248 
249   unsigned RsrcReg;
250   if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
251     // Evergreen / Northern Islands
252     switch (MFI->getShaderType()) {
253     default: // Fall through
254     case ShaderType::COMPUTE:  RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
255     case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
256     case ShaderType::PIXEL:    RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
257     case ShaderType::VERTEX:   RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
258     }
259   } else {
260     // R600 / R700
261     switch (MFI->getShaderType()) {
262     default: // Fall through
263     case ShaderType::GEOMETRY: // Fall through
264     case ShaderType::COMPUTE:  // Fall through
265     case ShaderType::VERTEX:   RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
266     case ShaderType::PIXEL:    RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
267     }
268   }
269 
270   OutStreamer->EmitIntValue(RsrcReg, 4);
271   OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
272                            S_STACK_SIZE(MFI->StackSize), 4);
273   OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
274   OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
275 
276   if (MFI->getShaderType() == ShaderType::COMPUTE) {
277     OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
278     OutStreamer->EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
279   }
280 }
281 
282 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
283                                         const MachineFunction &MF) const {
284   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
285   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
286   uint64_t CodeSize = 0;
287   unsigned MaxSGPR = 0;
288   unsigned MaxVGPR = 0;
289   bool VCCUsed = false;
290   bool FlatUsed = false;
291   const SIRegisterInfo *RI =
292       static_cast<const SIRegisterInfo *>(STM.getRegisterInfo());
293 
294   for (const MachineBasicBlock &MBB : MF) {
295     for (const MachineInstr &MI : MBB) {
296       // TODO: CodeSize should account for multiple functions.
297 
298       // TODO: Should we count size of debug info?
299       if (MI.isDebugValue())
300         continue;
301 
302       // FIXME: This is reporting 0 for many instructions.
303       CodeSize += MI.getDesc().Size;
304 
305       unsigned numOperands = MI.getNumOperands();
306       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
307         const MachineOperand &MO = MI.getOperand(op_idx);
308         unsigned width = 0;
309         bool isSGPR = false;
310 
311         if (!MO.isReg())
312           continue;
313 
314         unsigned reg = MO.getReg();
315         switch (reg) {
316         case AMDGPU::EXEC:
317         case AMDGPU::SCC:
318         case AMDGPU::M0:
319           continue;
320 
321         case AMDGPU::VCC:
322         case AMDGPU::VCC_LO:
323         case AMDGPU::VCC_HI:
324           VCCUsed = true;
325           continue;
326 
327         case AMDGPU::FLAT_SCR:
328         case AMDGPU::FLAT_SCR_LO:
329         case AMDGPU::FLAT_SCR_HI:
330           FlatUsed = true;
331           continue;
332 
333         default:
334           break;
335         }
336 
337         if (AMDGPU::SReg_32RegClass.contains(reg)) {
338           isSGPR = true;
339           width = 1;
340         } else if (AMDGPU::VGPR_32RegClass.contains(reg)) {
341           isSGPR = false;
342           width = 1;
343         } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
344           isSGPR = true;
345           width = 2;
346         } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
347           isSGPR = false;
348           width = 2;
349         } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
350           isSGPR = false;
351           width = 3;
352         } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
353           isSGPR = true;
354           width = 4;
355         } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
356           isSGPR = false;
357           width = 4;
358         } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
359           isSGPR = true;
360           width = 8;
361         } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
362           isSGPR = false;
363           width = 8;
364         } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
365           isSGPR = true;
366           width = 16;
367         } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
368           isSGPR = false;
369           width = 16;
370         } else {
371           llvm_unreachable("Unknown register class");
372         }
373         unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
374         unsigned maxUsed = hwReg + width - 1;
375         if (isSGPR) {
376           MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
377         } else {
378           MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
379         }
380       }
381     }
382   }
383 
384   if (VCCUsed)
385     MaxSGPR += 2;
386 
387   if (FlatUsed)
388     MaxSGPR += 2;
389 
390   // We found the maximum register index. They start at 0, so add one to get the
391   // number of registers.
392   ProgInfo.NumVGPR = MaxVGPR + 1;
393   ProgInfo.NumSGPR = MaxSGPR + 1;
394 
395   if (STM.hasSGPRInitBug()) {
396     if (ProgInfo.NumSGPR > AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG) {
397       LLVMContext &Ctx = MF.getFunction()->getContext();
398       Ctx.emitError("too many SGPRs used with the SGPR init bug");
399     }
400 
401     ProgInfo.NumSGPR = AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG;
402   }
403 
404   ProgInfo.VGPRBlocks = (ProgInfo.NumVGPR - 1) / 4;
405   ProgInfo.SGPRBlocks = (ProgInfo.NumSGPR - 1) / 8;
406   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
407   // register.
408   ProgInfo.FloatMode = getFPMode(MF);
409 
410   // XXX: Not quite sure what this does, but sc seems to unset this.
411   ProgInfo.IEEEMode = 0;
412 
413   // Do not clamp NAN to 0.
414   ProgInfo.DX10Clamp = 0;
415 
416   const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
417   ProgInfo.ScratchSize = FrameInfo->estimateStackSize(MF);
418 
419   ProgInfo.FlatUsed = FlatUsed;
420   ProgInfo.VCCUsed = VCCUsed;
421   ProgInfo.CodeLen = CodeSize;
422 
423   unsigned LDSAlignShift;
424   if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
425     // LDS is allocated in 64 dword blocks.
426     LDSAlignShift = 8;
427   } else {
428     // LDS is allocated in 128 dword blocks.
429     LDSAlignShift = 9;
430   }
431 
432   unsigned LDSSpillSize = MFI->LDSWaveSpillSize *
433                           MFI->getMaximumWorkGroupSize(MF);
434 
435   ProgInfo.LDSSize = MFI->LDSSize + LDSSpillSize;
436   ProgInfo.LDSBlocks =
437      RoundUpToAlignment(ProgInfo.LDSSize, 1 << LDSAlignShift) >> LDSAlignShift;
438 
439   // Scratch is allocated in 256 dword blocks.
440   unsigned ScratchAlignShift = 10;
441   // We need to program the hardware with the amount of scratch memory that
442   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
443   // scratch memory used per thread.
444   ProgInfo.ScratchBlocks =
445     RoundUpToAlignment(ProgInfo.ScratchSize * STM.getWavefrontSize(),
446                        1 << ScratchAlignShift) >> ScratchAlignShift;
447 
448   ProgInfo.ComputePGMRSrc1 =
449       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
450       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
451       S_00B848_PRIORITY(ProgInfo.Priority) |
452       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
453       S_00B848_PRIV(ProgInfo.Priv) |
454       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
455       S_00B848_IEEE_MODE(ProgInfo.DebugMode) |
456       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
457 
458   ProgInfo.ComputePGMRSrc2 =
459       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
460       S_00B84C_USER_SGPR(MFI->NumUserSGPRs) |
461       S_00B84C_TGID_X_EN(1) |
462       S_00B84C_TGID_Y_EN(1) |
463       S_00B84C_TGID_Z_EN(1) |
464       S_00B84C_TG_SIZE_EN(1) |
465       S_00B84C_TIDIG_COMP_CNT(2) |
466       S_00B84C_LDS_SIZE(ProgInfo.LDSBlocks);
467 }
468 
469 static unsigned getRsrcReg(unsigned ShaderType) {
470   switch (ShaderType) {
471   default: // Fall through
472   case ShaderType::COMPUTE:  return R_00B848_COMPUTE_PGM_RSRC1;
473   case ShaderType::GEOMETRY: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
474   case ShaderType::PIXEL:    return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
475   case ShaderType::VERTEX:   return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
476   }
477 }
478 
479 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
480                                          const SIProgramInfo &KernelInfo) {
481   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
482   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
483   unsigned RsrcReg = getRsrcReg(MFI->getShaderType());
484 
485   if (MFI->getShaderType() == ShaderType::COMPUTE) {
486     OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
487 
488     OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc1, 4);
489 
490     OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
491     OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc2, 4);
492 
493     OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
494     OutStreamer->EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4);
495 
496     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
497     // 0" comment but I don't see a corresponding field in the register spec.
498   } else {
499     OutStreamer->EmitIntValue(RsrcReg, 4);
500     OutStreamer->EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
501                               S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4);
502     if (STM.isVGPRSpillingEnabled(MFI)) {
503       OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
504       OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(KernelInfo.ScratchBlocks), 4);
505     }
506   }
507 
508   if (MFI->getShaderType() == ShaderType::PIXEL) {
509     OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
510     OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4);
511     OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
512     OutStreamer->EmitIntValue(MFI->PSInputAddr, 4);
513   }
514 }
515 
516 void AMDGPUAsmPrinter::EmitAmdKernelCodeT(const MachineFunction &MF,
517                                          const SIProgramInfo &KernelInfo) const {
518   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
519   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
520   amd_kernel_code_t header;
521 
522   AMDGPU::initDefaultAMDKernelCodeT(header, STM.getFeatureBits());
523 
524   header.compute_pgm_resource_registers =
525       KernelInfo.ComputePGMRSrc1 |
526       (KernelInfo.ComputePGMRSrc2 << 32);
527   header.code_properties =
528       AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR |
529       AMD_CODE_PROPERTY_IS_PTR64;
530 
531   header.kernarg_segment_byte_size = MFI->ABIArgOffset;
532   header.wavefront_sgpr_count = KernelInfo.NumSGPR;
533   header.workitem_vgpr_count = KernelInfo.NumVGPR;
534 
535   AMDGPUTargetStreamer *TS =
536       static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
537   TS->EmitAMDKernelCodeT(header);
538 }
539 
540 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
541                                        unsigned AsmVariant,
542                                        const char *ExtraCode, raw_ostream &O) {
543   if (ExtraCode && ExtraCode[0]) {
544     if (ExtraCode[1] != 0)
545       return true; // Unknown modifier.
546 
547     switch (ExtraCode[0]) {
548     default:
549       // See if this is a generic print operand
550       return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
551     case 'r':
552       break;
553     }
554   }
555 
556   AMDGPUInstPrinter::printRegOperand(MI->getOperand(OpNo).getReg(), O,
557                    *TM.getSubtargetImpl(*MF->getFunction())->getRegisterInfo());
558   return false;
559 }
560