1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
15 //
16 //===----------------------------------------------------------------------===//
17 //
18 
19 #include "AMDGPUAsmPrinter.h"
20 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
21 #include "InstPrinter/AMDGPUInstPrinter.h"
22 #include "Utils/AMDGPUBaseInfo.h"
23 #include "AMDGPU.h"
24 #include "AMDKernelCodeT.h"
25 #include "AMDGPUSubtarget.h"
26 #include "R600Defines.h"
27 #include "R600MachineFunctionInfo.h"
28 #include "R600RegisterInfo.h"
29 #include "SIDefines.h"
30 #include "SIMachineFunctionInfo.h"
31 #include "SIRegisterInfo.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/MC/MCContext.h"
34 #include "llvm/MC/MCSectionELF.h"
35 #include "llvm/MC/MCStreamer.h"
36 #include "llvm/Support/ELF.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/TargetRegistry.h"
39 #include "llvm/Target/TargetLoweringObjectFile.h"
40 
41 using namespace llvm;
42 
43 // TODO: This should get the default rounding mode from the kernel. We just set
44 // the default here, but this could change if the OpenCL rounding mode pragmas
45 // are used.
46 //
47 // The denormal mode here should match what is reported by the OpenCL runtime
48 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
49 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
50 //
51 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
52 // precision, and leaves single precision to flush all and does not report
53 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
54 // CL_FP_DENORM for both.
55 //
56 // FIXME: It seems some instructions do not support single precision denormals
57 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
58 // and sin_f32, cos_f32 on most parts).
59 
60 // We want to use these instructions, and using fp32 denormals also causes
61 // instructions to run at the double precision rate for the device so it's
62 // probably best to just report no single precision denormals.
63 static uint32_t getFPMode(const MachineFunction &F) {
64   const AMDGPUSubtarget& ST = F.getSubtarget<AMDGPUSubtarget>();
65   // TODO: Is there any real use for the flush in only / flush out only modes?
66 
67   uint32_t FP32Denormals =
68     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
69 
70   uint32_t FP64Denormals =
71     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
72 
73   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
74          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
75          FP_DENORM_MODE_SP(FP32Denormals) |
76          FP_DENORM_MODE_DP(FP64Denormals);
77 }
78 
79 static AsmPrinter *
80 createAMDGPUAsmPrinterPass(TargetMachine &tm,
81                            std::unique_ptr<MCStreamer> &&Streamer) {
82   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
83 }
84 
85 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
86   TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
87   TargetRegistry::RegisterAsmPrinter(TheGCNTarget, createAMDGPUAsmPrinterPass);
88 }
89 
90 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
91                                    std::unique_ptr<MCStreamer> Streamer)
92     : AsmPrinter(TM, std::move(Streamer)) {}
93 
94 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
95   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
96   SIProgramInfo KernelInfo;
97   if (STM.isAmdHsaOS()) {
98     getSIProgramInfo(KernelInfo, *MF);
99     EmitAmdKernelCodeT(*MF, KernelInfo);
100   }
101 }
102 
103 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
104 
105   // This label is used to mark the end of the .text section.
106   const TargetLoweringObjectFile &TLOF = getObjFileLowering();
107   OutStreamer->SwitchSection(TLOF.getTextSection());
108   MCSymbol *EndOfTextLabel =
109       OutContext.getOrCreateSymbol(StringRef(END_OF_TEXT_LABEL_NAME));
110   OutStreamer->EmitLabel(EndOfTextLabel);
111 }
112 
113 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
114 
115   // The starting address of all shader programs must be 256 bytes aligned.
116   MF.setAlignment(8);
117 
118   SetupMachineFunction(MF);
119 
120   MCContext &Context = getObjFileLowering().getContext();
121   MCSectionELF *ConfigSection =
122       Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
123   OutStreamer->SwitchSection(ConfigSection);
124 
125   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
126   SIProgramInfo KernelInfo;
127   if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
128     getSIProgramInfo(KernelInfo, MF);
129     if (!STM.isAmdHsaOS()) {
130       EmitProgramInfoSI(MF, KernelInfo);
131     }
132     // Emit directives
133     AMDGPUTargetStreamer *TS =
134         static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
135     TS->EmitDirectiveHSACodeObjectVersion(1, 0);
136     AMDGPU::IsaVersion ISA = STM.getIsaVersion();
137     TS->EmitDirectiveHSACodeObjectISA(ISA.Major, ISA.Minor, ISA.Stepping,
138                                       "AMD", "AMDGPU");
139   } else {
140     EmitProgramInfoR600(MF);
141   }
142 
143   DisasmLines.clear();
144   HexLines.clear();
145   DisasmLineMaxLen = 0;
146 
147   EmitFunctionBody();
148 
149   if (isVerbose()) {
150     MCSectionELF *CommentSection =
151         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
152     OutStreamer->SwitchSection(CommentSection);
153 
154     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
155       OutStreamer->emitRawComment(" Kernel info:", false);
156       OutStreamer->emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
157                                   false);
158       OutStreamer->emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
159                                   false);
160       OutStreamer->emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
161                                   false);
162       OutStreamer->emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
163                                   false);
164       OutStreamer->emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
165                                   false);
166       OutStreamer->emitRawComment(" ScratchSize: " + Twine(KernelInfo.ScratchSize),
167                                   false);
168 
169       const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
170 
171       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:USER_SGPR: " +
172                                   Twine(MFI->NumUserSGPRs),
173                                   false);
174     } else {
175       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
176       OutStreamer->emitRawComment(
177         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
178     }
179   }
180 
181   if (STM.dumpCode()) {
182 
183     OutStreamer->SwitchSection(
184         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
185 
186     for (size_t i = 0; i < DisasmLines.size(); ++i) {
187       std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
188       Comment += " ; " + HexLines[i] + "\n";
189 
190       OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
191       OutStreamer->EmitBytes(StringRef(Comment));
192     }
193   }
194 
195   return false;
196 }
197 
198 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
199   unsigned MaxGPR = 0;
200   bool killPixel = false;
201   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
202   const R600RegisterInfo *RI =
203       static_cast<const R600RegisterInfo *>(STM.getRegisterInfo());
204   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
205 
206   for (const MachineBasicBlock &MBB : MF) {
207     for (const MachineInstr &MI : MBB) {
208       if (MI.getOpcode() == AMDGPU::KILLGT)
209         killPixel = true;
210       unsigned numOperands = MI.getNumOperands();
211       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
212         const MachineOperand &MO = MI.getOperand(op_idx);
213         if (!MO.isReg())
214           continue;
215         unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
216 
217         // Register with value > 127 aren't GPR
218         if (HWReg > 127)
219           continue;
220         MaxGPR = std::max(MaxGPR, HWReg);
221       }
222     }
223   }
224 
225   unsigned RsrcReg;
226   if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
227     // Evergreen / Northern Islands
228     switch (MFI->getShaderType()) {
229     default: // Fall through
230     case ShaderType::COMPUTE:  RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
231     case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
232     case ShaderType::PIXEL:    RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
233     case ShaderType::VERTEX:   RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
234     }
235   } else {
236     // R600 / R700
237     switch (MFI->getShaderType()) {
238     default: // Fall through
239     case ShaderType::GEOMETRY: // Fall through
240     case ShaderType::COMPUTE:  // Fall through
241     case ShaderType::VERTEX:   RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
242     case ShaderType::PIXEL:    RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
243     }
244   }
245 
246   OutStreamer->EmitIntValue(RsrcReg, 4);
247   OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
248                            S_STACK_SIZE(MFI->StackSize), 4);
249   OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
250   OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
251 
252   if (MFI->getShaderType() == ShaderType::COMPUTE) {
253     OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
254     OutStreamer->EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
255   }
256 }
257 
258 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
259                                         const MachineFunction &MF) const {
260   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
261   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
262   uint64_t CodeSize = 0;
263   unsigned MaxSGPR = 0;
264   unsigned MaxVGPR = 0;
265   bool VCCUsed = false;
266   bool FlatUsed = false;
267   const SIRegisterInfo *RI =
268       static_cast<const SIRegisterInfo *>(STM.getRegisterInfo());
269 
270   for (const MachineBasicBlock &MBB : MF) {
271     for (const MachineInstr &MI : MBB) {
272       // TODO: CodeSize should account for multiple functions.
273 
274       // TODO: Should we count size of debug info?
275       if (MI.isDebugValue())
276         continue;
277 
278       // FIXME: This is reporting 0 for many instructions.
279       CodeSize += MI.getDesc().Size;
280 
281       unsigned numOperands = MI.getNumOperands();
282       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
283         const MachineOperand &MO = MI.getOperand(op_idx);
284         unsigned width = 0;
285         bool isSGPR = false;
286 
287         if (!MO.isReg())
288           continue;
289 
290         unsigned reg = MO.getReg();
291         switch (reg) {
292         case AMDGPU::EXEC:
293         case AMDGPU::SCC:
294         case AMDGPU::M0:
295           continue;
296 
297         case AMDGPU::VCC:
298         case AMDGPU::VCC_LO:
299         case AMDGPU::VCC_HI:
300           VCCUsed = true;
301           continue;
302 
303         case AMDGPU::FLAT_SCR:
304         case AMDGPU::FLAT_SCR_LO:
305         case AMDGPU::FLAT_SCR_HI:
306           FlatUsed = true;
307           continue;
308 
309         default:
310           break;
311         }
312 
313         if (AMDGPU::SReg_32RegClass.contains(reg)) {
314           isSGPR = true;
315           width = 1;
316         } else if (AMDGPU::VGPR_32RegClass.contains(reg)) {
317           isSGPR = false;
318           width = 1;
319         } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
320           isSGPR = true;
321           width = 2;
322         } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
323           isSGPR = false;
324           width = 2;
325         } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
326           isSGPR = false;
327           width = 3;
328         } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
329           isSGPR = true;
330           width = 4;
331         } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
332           isSGPR = false;
333           width = 4;
334         } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
335           isSGPR = true;
336           width = 8;
337         } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
338           isSGPR = false;
339           width = 8;
340         } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
341           isSGPR = true;
342           width = 16;
343         } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
344           isSGPR = false;
345           width = 16;
346         } else {
347           llvm_unreachable("Unknown register class");
348         }
349         unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
350         unsigned maxUsed = hwReg + width - 1;
351         if (isSGPR) {
352           MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
353         } else {
354           MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
355         }
356       }
357     }
358   }
359 
360   if (VCCUsed)
361     MaxSGPR += 2;
362 
363   if (FlatUsed)
364     MaxSGPR += 2;
365 
366   // We found the maximum register index. They start at 0, so add one to get the
367   // number of registers.
368   ProgInfo.NumVGPR = MaxVGPR + 1;
369   ProgInfo.NumSGPR = MaxSGPR + 1;
370 
371   if (STM.hasSGPRInitBug()) {
372     if (ProgInfo.NumSGPR > AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG) {
373       LLVMContext &Ctx = MF.getFunction()->getContext();
374       Ctx.emitError("too many SGPRs used with the SGPR init bug");
375     }
376 
377     ProgInfo.NumSGPR = AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG;
378   }
379 
380   ProgInfo.VGPRBlocks = (ProgInfo.NumVGPR - 1) / 4;
381   ProgInfo.SGPRBlocks = (ProgInfo.NumSGPR - 1) / 8;
382   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
383   // register.
384   ProgInfo.FloatMode = getFPMode(MF);
385 
386   // XXX: Not quite sure what this does, but sc seems to unset this.
387   ProgInfo.IEEEMode = 0;
388 
389   // Do not clamp NAN to 0.
390   ProgInfo.DX10Clamp = 0;
391 
392   const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
393   ProgInfo.ScratchSize = FrameInfo->estimateStackSize(MF);
394 
395   ProgInfo.FlatUsed = FlatUsed;
396   ProgInfo.VCCUsed = VCCUsed;
397   ProgInfo.CodeLen = CodeSize;
398 
399   unsigned LDSAlignShift;
400   if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
401     // LDS is allocated in 64 dword blocks.
402     LDSAlignShift = 8;
403   } else {
404     // LDS is allocated in 128 dword blocks.
405     LDSAlignShift = 9;
406   }
407 
408   unsigned LDSSpillSize = MFI->LDSWaveSpillSize *
409                           MFI->getMaximumWorkGroupSize(MF);
410 
411   ProgInfo.LDSSize = MFI->LDSSize + LDSSpillSize;
412   ProgInfo.LDSBlocks =
413      RoundUpToAlignment(ProgInfo.LDSSize, 1 << LDSAlignShift) >> LDSAlignShift;
414 
415   // Scratch is allocated in 256 dword blocks.
416   unsigned ScratchAlignShift = 10;
417   // We need to program the hardware with the amount of scratch memory that
418   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
419   // scratch memory used per thread.
420   ProgInfo.ScratchBlocks =
421     RoundUpToAlignment(ProgInfo.ScratchSize * STM.getWavefrontSize(),
422                        1 << ScratchAlignShift) >> ScratchAlignShift;
423 
424   ProgInfo.ComputePGMRSrc1 =
425       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
426       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
427       S_00B848_PRIORITY(ProgInfo.Priority) |
428       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
429       S_00B848_PRIV(ProgInfo.Priv) |
430       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
431       S_00B848_IEEE_MODE(ProgInfo.DebugMode) |
432       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
433 
434   ProgInfo.ComputePGMRSrc2 =
435       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
436       S_00B84C_USER_SGPR(MFI->NumUserSGPRs) |
437       S_00B84C_TGID_X_EN(1) |
438       S_00B84C_TGID_Y_EN(1) |
439       S_00B84C_TGID_Z_EN(1) |
440       S_00B84C_TG_SIZE_EN(1) |
441       S_00B84C_TIDIG_COMP_CNT(2) |
442       S_00B84C_LDS_SIZE(ProgInfo.LDSBlocks);
443 }
444 
445 static unsigned getRsrcReg(unsigned ShaderType) {
446   switch (ShaderType) {
447   default: // Fall through
448   case ShaderType::COMPUTE:  return R_00B848_COMPUTE_PGM_RSRC1;
449   case ShaderType::GEOMETRY: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
450   case ShaderType::PIXEL:    return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
451   case ShaderType::VERTEX:   return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
452   }
453 }
454 
455 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
456                                          const SIProgramInfo &KernelInfo) {
457   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
458   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
459   unsigned RsrcReg = getRsrcReg(MFI->getShaderType());
460 
461   if (MFI->getShaderType() == ShaderType::COMPUTE) {
462     OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
463 
464     OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc1, 4);
465 
466     OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
467     OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc2, 4);
468 
469     OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
470     OutStreamer->EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4);
471 
472     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
473     // 0" comment but I don't see a corresponding field in the register spec.
474   } else {
475     OutStreamer->EmitIntValue(RsrcReg, 4);
476     OutStreamer->EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
477                               S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4);
478     if (STM.isVGPRSpillingEnabled(MFI)) {
479       OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
480       OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(KernelInfo.ScratchBlocks), 4);
481     }
482   }
483 
484   if (MFI->getShaderType() == ShaderType::PIXEL) {
485     OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
486     OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4);
487     OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
488     OutStreamer->EmitIntValue(MFI->PSInputAddr, 4);
489   }
490 }
491 
492 void AMDGPUAsmPrinter::EmitAmdKernelCodeT(const MachineFunction &MF,
493                                          const SIProgramInfo &KernelInfo) const {
494   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
495   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
496   amd_kernel_code_t header;
497 
498   AMDGPU::initDefaultAMDKernelCodeT(header, STM.getFeatureBits());
499 
500   header.compute_pgm_resource_registers =
501       KernelInfo.ComputePGMRSrc1 |
502       (KernelInfo.ComputePGMRSrc2 << 32);
503   header.code_properties =
504       AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR |
505       AMD_CODE_PROPERTY_IS_PTR64;
506 
507   header.kernarg_segment_byte_size = MFI->ABIArgOffset;
508   header.wavefront_sgpr_count = KernelInfo.NumSGPR;
509   header.workitem_vgpr_count = KernelInfo.NumVGPR;
510 
511   AMDGPUTargetStreamer *TS =
512       static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
513   TS->EmitAMDKernelCodeT(header);
514 }
515 
516 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
517                                        unsigned AsmVariant,
518                                        const char *ExtraCode, raw_ostream &O) {
519   if (ExtraCode && ExtraCode[0]) {
520     if (ExtraCode[1] != 0)
521       return true; // Unknown modifier.
522 
523     switch (ExtraCode[0]) {
524     default:
525       // See if this is a generic print operand
526       return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
527     case 'r':
528       break;
529     }
530   }
531 
532   AMDGPUInstPrinter::printRegOperand(MI->getOperand(OpNo).getReg(), O,
533                    *TM.getSubtargetImpl(*MF->getFunction())->getRegisterInfo());
534   return false;
535 }
536