1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
15 //
16 //===----------------------------------------------------------------------===//
17 //
18 
19 #include "AMDGPUAsmPrinter.h"
20 #include "AMDGPUTargetMachine.h"
21 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
22 #include "InstPrinter/AMDGPUInstPrinter.h"
23 #include "Utils/AMDGPUBaseInfo.h"
24 #include "AMDGPU.h"
25 #include "AMDGPUSubtarget.h"
26 #include "R600Defines.h"
27 #include "R600MachineFunctionInfo.h"
28 #include "R600RegisterInfo.h"
29 #include "SIDefines.h"
30 #include "SIMachineFunctionInfo.h"
31 #include "SIInstrInfo.h"
32 #include "SIRegisterInfo.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/IR/DiagnosticInfo.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCSectionELF.h"
37 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/Support/ELF.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Target/TargetLoweringObjectFile.h"
42 
43 using namespace llvm;
44 
45 // TODO: This should get the default rounding mode from the kernel. We just set
46 // the default here, but this could change if the OpenCL rounding mode pragmas
47 // are used.
48 //
49 // The denormal mode here should match what is reported by the OpenCL runtime
50 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
51 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
52 //
53 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
54 // precision, and leaves single precision to flush all and does not report
55 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
56 // CL_FP_DENORM for both.
57 //
58 // FIXME: It seems some instructions do not support single precision denormals
59 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
60 // and sin_f32, cos_f32 on most parts).
61 
62 // We want to use these instructions, and using fp32 denormals also causes
63 // instructions to run at the double precision rate for the device so it's
64 // probably best to just report no single precision denormals.
65 static uint32_t getFPMode(const MachineFunction &F) {
66   const SISubtarget& ST = F.getSubtarget<SISubtarget>();
67   // TODO: Is there any real use for the flush in only / flush out only modes?
68 
69   uint32_t FP32Denormals =
70     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
71 
72   uint32_t FP64Denormals =
73     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
74 
75   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
76          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
77          FP_DENORM_MODE_SP(FP32Denormals) |
78          FP_DENORM_MODE_DP(FP64Denormals);
79 }
80 
81 static AsmPrinter *
82 createAMDGPUAsmPrinterPass(TargetMachine &tm,
83                            std::unique_ptr<MCStreamer> &&Streamer) {
84   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
85 }
86 
87 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
88   TargetRegistry::RegisterAsmPrinter(getTheAMDGPUTarget(),
89                                      createAMDGPUAsmPrinterPass);
90   TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(),
91                                      createAMDGPUAsmPrinterPass);
92 }
93 
94 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
95                                    std::unique_ptr<MCStreamer> Streamer)
96   : AsmPrinter(TM, std::move(Streamer)) {
97     AMDGPUASI = static_cast<AMDGPUTargetMachine*>(&TM)->getAMDGPUAS();
98   }
99 
100 StringRef AMDGPUAsmPrinter::getPassName() const {
101   return "AMDGPU Assembly Printer";
102 }
103 
104 const MCSubtargetInfo* AMDGPUAsmPrinter::getSTI() const {
105   return TM.getMCSubtargetInfo();
106 }
107 
108 AMDGPUTargetStreamer& AMDGPUAsmPrinter::getTargetStreamer() const {
109   return static_cast<AMDGPUTargetStreamer&>(*OutStreamer->getTargetStreamer());
110 }
111 
112 void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) {
113   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
114     return;
115 
116   AMDGPU::IsaInfo::IsaVersion ISA =
117       AMDGPU::IsaInfo::getIsaVersion(getSTI()->getFeatureBits());
118 
119   getTargetStreamer().EmitDirectiveHSACodeObjectVersion(2, 1);
120   getTargetStreamer().EmitDirectiveHSACodeObjectISA(
121       ISA.Major, ISA.Minor, ISA.Stepping, "AMD", "AMDGPU");
122   getTargetStreamer().EmitStartOfCodeObjectMetadata(M);
123 }
124 
125 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
126   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
127     return;
128 
129   getTargetStreamer().EmitEndOfCodeObjectMetadata();
130 }
131 
132 bool AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough(
133   const MachineBasicBlock *MBB) const {
134   if (!AsmPrinter::isBlockOnlyReachableByFallthrough(MBB))
135     return false;
136 
137   if (MBB->empty())
138     return true;
139 
140   // If this is a block implementing a long branch, an expression relative to
141   // the start of the block is needed.  to the start of the block.
142   // XXX - Is there a smarter way to check this?
143   return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
144 }
145 
146 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
147   const AMDGPUMachineFunction *MFI = MF->getInfo<AMDGPUMachineFunction>();
148   if (!MFI->isEntryFunction())
149     return;
150 
151   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
152   SIProgramInfo KernelInfo;
153   amd_kernel_code_t KernelCode;
154   if (STM.isAmdCodeObjectV2(*MF)) {
155     getSIProgramInfo(KernelInfo, *MF);
156     getAmdKernelCode(KernelCode, KernelInfo, *MF);
157 
158     OutStreamer->SwitchSection(getObjFileLowering().getTextSection());
159     getTargetStreamer().EmitAMDKernelCodeT(KernelCode);
160   }
161 
162   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
163     return;
164   getTargetStreamer().EmitKernelCodeObjectMetadata(*MF->getFunction(),
165                                                    KernelCode);
166 }
167 
168 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
169   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
170   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
171   if (MFI->isEntryFunction() && STM.isAmdCodeObjectV2(*MF)) {
172     SmallString<128> SymbolName;
173     getNameWithPrefix(SymbolName, MF->getFunction()),
174     getTargetStreamer().EmitAMDGPUSymbolType(
175         SymbolName, ELF::STT_AMDGPU_HSA_KERNEL);
176   }
177 
178   AsmPrinter::EmitFunctionEntryLabel();
179 }
180 
181 void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
182 
183   // Group segment variables aren't emitted in HSA.
184   if (AMDGPU::isGroupSegment(GV, AMDGPUASI))
185     return;
186 
187   AsmPrinter::EmitGlobalVariable(GV);
188 }
189 
190 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
191   const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
192 
193   // The starting address of all shader programs must be 256 bytes aligned.
194   // Regular functions just need the basic required instruction alignment.
195   MF.setAlignment(MFI->isEntryFunction() ? 8 : 2);
196 
197   SetupMachineFunction(MF);
198 
199   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
200   MCContext &Context = getObjFileLowering().getContext();
201   if (!STM.isAmdHsaOS()) {
202     MCSectionELF *ConfigSection =
203         Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
204     OutStreamer->SwitchSection(ConfigSection);
205   }
206 
207   SIProgramInfo KernelInfo;
208   if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
209     getSIProgramInfo(KernelInfo, MF);
210     if (!STM.isAmdHsaOS()) {
211       EmitProgramInfoSI(MF, KernelInfo);
212     }
213   } else {
214     EmitProgramInfoR600(MF);
215   }
216 
217   DisasmLines.clear();
218   HexLines.clear();
219   DisasmLineMaxLen = 0;
220 
221   EmitFunctionBody();
222 
223   if (isVerbose()) {
224     MCSectionELF *CommentSection =
225         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
226     OutStreamer->SwitchSection(CommentSection);
227 
228     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
229       if (MFI->isEntryFunction()) {
230         OutStreamer->emitRawComment(" Kernel info:", false);
231       } else {
232         OutStreamer->emitRawComment(" Function info:", false);
233       }
234 
235       OutStreamer->emitRawComment(" codeLenInByte = " +
236                                   Twine(getFunctionCodeSize(MF)), false);
237       OutStreamer->emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
238                                   false);
239       OutStreamer->emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
240                                   false);
241 
242       OutStreamer->emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
243                                   false);
244       OutStreamer->emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
245                                   false);
246       OutStreamer->emitRawComment(" ScratchSize: " + Twine(KernelInfo.ScratchSize),
247                                   false);
248       OutStreamer->emitRawComment(" LDSByteSize: " + Twine(KernelInfo.LDSSize) +
249                                   " bytes/workgroup (compile time only)", false);
250 
251       if (!MFI->isEntryFunction())
252         return false;
253 
254       OutStreamer->emitRawComment(" SGPRBlocks: " +
255                                   Twine(KernelInfo.SGPRBlocks), false);
256       OutStreamer->emitRawComment(" VGPRBlocks: " +
257                                   Twine(KernelInfo.VGPRBlocks), false);
258 
259       OutStreamer->emitRawComment(" NumSGPRsForWavesPerEU: " +
260                                   Twine(KernelInfo.NumSGPRsForWavesPerEU), false);
261       OutStreamer->emitRawComment(" NumVGPRsForWavesPerEU: " +
262                                   Twine(KernelInfo.NumVGPRsForWavesPerEU), false);
263 
264       OutStreamer->emitRawComment(" ReservedVGPRFirst: " + Twine(KernelInfo.ReservedVGPRFirst),
265                                   false);
266       OutStreamer->emitRawComment(" ReservedVGPRCount: " + Twine(KernelInfo.ReservedVGPRCount),
267                                   false);
268 
269       if (MF.getSubtarget<SISubtarget>().debuggerEmitPrologue()) {
270         OutStreamer->emitRawComment(" DebuggerWavefrontPrivateSegmentOffsetSGPR: s" +
271                                     Twine(KernelInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR), false);
272         OutStreamer->emitRawComment(" DebuggerPrivateSegmentBufferSGPR: s" +
273                                     Twine(KernelInfo.DebuggerPrivateSegmentBufferSGPR), false);
274       }
275 
276       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:USER_SGPR: " +
277                                   Twine(G_00B84C_USER_SGPR(KernelInfo.ComputePGMRSrc2)),
278                                   false);
279       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
280                                   Twine(G_00B84C_TRAP_HANDLER(KernelInfo.ComputePGMRSrc2)),
281                                   false);
282       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_X_EN: " +
283                                   Twine(G_00B84C_TGID_X_EN(KernelInfo.ComputePGMRSrc2)),
284                                   false);
285       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
286                                   Twine(G_00B84C_TGID_Y_EN(KernelInfo.ComputePGMRSrc2)),
287                                   false);
288       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
289                                   Twine(G_00B84C_TGID_Z_EN(KernelInfo.ComputePGMRSrc2)),
290                                   false);
291       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
292                                   Twine(G_00B84C_TIDIG_COMP_CNT(KernelInfo.ComputePGMRSrc2)),
293                                   false);
294 
295     } else {
296       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
297       OutStreamer->emitRawComment(
298         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->CFStackSize)));
299     }
300   }
301 
302   if (STM.dumpCode()) {
303 
304     OutStreamer->SwitchSection(
305         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
306 
307     for (size_t i = 0; i < DisasmLines.size(); ++i) {
308       std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
309       Comment += " ; " + HexLines[i] + "\n";
310 
311       OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
312       OutStreamer->EmitBytes(StringRef(Comment));
313     }
314   }
315 
316   return false;
317 }
318 
319 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
320   unsigned MaxGPR = 0;
321   bool killPixel = false;
322   const R600Subtarget &STM = MF.getSubtarget<R600Subtarget>();
323   const R600RegisterInfo *RI = STM.getRegisterInfo();
324   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
325 
326   for (const MachineBasicBlock &MBB : MF) {
327     for (const MachineInstr &MI : MBB) {
328       if (MI.getOpcode() == AMDGPU::KILLGT)
329         killPixel = true;
330       unsigned numOperands = MI.getNumOperands();
331       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
332         const MachineOperand &MO = MI.getOperand(op_idx);
333         if (!MO.isReg())
334           continue;
335         unsigned HWReg = RI->getHWRegIndex(MO.getReg());
336 
337         // Register with value > 127 aren't GPR
338         if (HWReg > 127)
339           continue;
340         MaxGPR = std::max(MaxGPR, HWReg);
341       }
342     }
343   }
344 
345   unsigned RsrcReg;
346   if (STM.getGeneration() >= R600Subtarget::EVERGREEN) {
347     // Evergreen / Northern Islands
348     switch (MF.getFunction()->getCallingConv()) {
349     default: LLVM_FALLTHROUGH;
350     case CallingConv::AMDGPU_CS: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
351     case CallingConv::AMDGPU_GS: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
352     case CallingConv::AMDGPU_PS: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
353     case CallingConv::AMDGPU_VS: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
354     }
355   } else {
356     // R600 / R700
357     switch (MF.getFunction()->getCallingConv()) {
358     default: LLVM_FALLTHROUGH;
359     case CallingConv::AMDGPU_GS: LLVM_FALLTHROUGH;
360     case CallingConv::AMDGPU_CS: LLVM_FALLTHROUGH;
361     case CallingConv::AMDGPU_VS: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
362     case CallingConv::AMDGPU_PS: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
363     }
364   }
365 
366   OutStreamer->EmitIntValue(RsrcReg, 4);
367   OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
368                            S_STACK_SIZE(MFI->CFStackSize), 4);
369   OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
370   OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
371 
372   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
373     OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
374     OutStreamer->EmitIntValue(alignTo(MFI->getLDSSize(), 4) >> 2, 4);
375   }
376 }
377 
378 uint64_t AMDGPUAsmPrinter::getFunctionCodeSize(const MachineFunction &MF) const {
379   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
380   const SIInstrInfo *TII = STM.getInstrInfo();
381 
382   uint64_t CodeSize = 0;
383 
384   for (const MachineBasicBlock &MBB : MF) {
385     for (const MachineInstr &MI : MBB) {
386       // TODO: CodeSize should account for multiple functions.
387 
388       // TODO: Should we count size of debug info?
389       if (MI.isDebugValue())
390         continue;
391 
392       CodeSize += TII->getInstSizeInBytes(MI);
393     }
394   }
395 
396   return CodeSize;
397 }
398 
399 static bool hasAnyNonFlatUseOfReg(const MachineRegisterInfo &MRI,
400                                   const SIInstrInfo &TII,
401                                   unsigned Reg) {
402   for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) {
403     if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent()))
404       return true;
405   }
406 
407   return false;
408 }
409 
410 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
411                                         const MachineFunction &MF) const {
412   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
413   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
414   const MachineRegisterInfo &MRI = MF.getRegInfo();
415   const SIInstrInfo *TII = STM.getInstrInfo();
416   const SIRegisterInfo *RI = &TII->getRegisterInfo();
417 
418 
419   MCPhysReg NumVGPRReg = AMDGPU::NoRegister;
420   for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) {
421     if (MRI.isPhysRegUsed(Reg)) {
422       NumVGPRReg = Reg;
423       break;
424     }
425   }
426 
427   MCPhysReg NumSGPRReg = AMDGPU::NoRegister;
428   for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) {
429     if (MRI.isPhysRegUsed(Reg)) {
430       NumSGPRReg = Reg;
431       break;
432     }
433   }
434 
435   // We found the maximum register index. They start at 0, so add one to get the
436   // number of registers.
437   ProgInfo.NumVGPR = NumVGPRReg == AMDGPU::NoRegister ? 0 :
438     RI->getHWRegIndex(NumVGPRReg) + 1;
439   ProgInfo.NumSGPR = NumSGPRReg == AMDGPU::NoRegister ? 0 :
440     RI->getHWRegIndex(NumSGPRReg) + 1;
441   unsigned ExtraSGPRs = 0;
442 
443   ProgInfo.VCCUsed = MRI.isPhysRegUsed(AMDGPU::VCC_LO) ||
444                      MRI.isPhysRegUsed(AMDGPU::VCC_HI);
445   if (ProgInfo.VCCUsed)
446     ExtraSGPRs = 2;
447 
448   ProgInfo.FlatUsed = MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_LO) ||
449                       MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_HI);
450 
451   // Even if FLAT_SCRATCH is implicitly used, it has no effect if flat
452   // instructions aren't used to access the scratch buffer. Inline assembly
453   // may need it though.
454   //
455   // If we only have implicit uses of flat_scr on flat instructions, it is not
456   // really needed.
457   if (ProgInfo.FlatUsed && !MFI->hasFlatScratchInit() &&
458       (!hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR) &&
459        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_LO) &&
460        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_HI))) {
461     ProgInfo.FlatUsed = false;
462   }
463 
464   if (STM.getGeneration() < SISubtarget::VOLCANIC_ISLANDS) {
465     if (ProgInfo.FlatUsed)
466       ExtraSGPRs = 4;
467   } else {
468     if (STM.isXNACKEnabled())
469       ExtraSGPRs = 4;
470 
471     if (ProgInfo.FlatUsed)
472       ExtraSGPRs = 6;
473   }
474 
475   unsigned ExtraVGPRs = STM.getReservedNumVGPRs(MF);
476 
477   // Check the addressable register limit before we add ExtraSGPRs.
478   if (STM.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
479       !STM.hasSGPRInitBug()) {
480     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
481     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
482       // This can happen due to a compiler bug or when using inline asm.
483       LLVMContext &Ctx = MF.getFunction()->getContext();
484       DiagnosticInfoResourceLimit Diag(*MF.getFunction(),
485                                        "addressable scalar registers",
486                                        ProgInfo.NumSGPR, DS_Error,
487                                        DK_ResourceLimit,
488                                        MaxAddressableNumSGPRs);
489       Ctx.diagnose(Diag);
490       ProgInfo.NumSGPR = MaxAddressableNumSGPRs - 1;
491     }
492   }
493 
494   // Account for extra SGPRs and VGPRs reserved for debugger use.
495   ProgInfo.NumSGPR += ExtraSGPRs;
496   ProgInfo.NumVGPR += ExtraVGPRs;
497 
498   // Adjust number of registers used to meet default/requested minimum/maximum
499   // number of waves per execution unit request.
500   ProgInfo.NumSGPRsForWavesPerEU = std::max(
501     std::max(ProgInfo.NumSGPR, 1u), STM.getMinNumSGPRs(MFI->getMaxWavesPerEU()));
502   ProgInfo.NumVGPRsForWavesPerEU = std::max(
503     std::max(ProgInfo.NumVGPR, 1u), STM.getMinNumVGPRs(MFI->getMaxWavesPerEU()));
504 
505   if (STM.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ||
506       STM.hasSGPRInitBug()) {
507     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
508     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
509       // This can happen due to a compiler bug or when using inline asm to use
510       // the registers which are usually reserved for vcc etc.
511       LLVMContext &Ctx = MF.getFunction()->getContext();
512       DiagnosticInfoResourceLimit Diag(*MF.getFunction(),
513                                        "scalar registers",
514                                        ProgInfo.NumSGPR, DS_Error,
515                                        DK_ResourceLimit,
516                                        MaxAddressableNumSGPRs);
517       Ctx.diagnose(Diag);
518       ProgInfo.NumSGPR = MaxAddressableNumSGPRs;
519       ProgInfo.NumSGPRsForWavesPerEU = MaxAddressableNumSGPRs;
520     }
521   }
522 
523   if (STM.hasSGPRInitBug()) {
524     ProgInfo.NumSGPR =
525         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
526     ProgInfo.NumSGPRsForWavesPerEU =
527         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
528   }
529 
530   if (MFI->getNumUserSGPRs() > STM.getMaxNumUserSGPRs()) {
531     LLVMContext &Ctx = MF.getFunction()->getContext();
532     DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "user SGPRs",
533                                      MFI->getNumUserSGPRs(), DS_Error);
534     Ctx.diagnose(Diag);
535   }
536 
537   if (MFI->getLDSSize() > static_cast<unsigned>(STM.getLocalMemorySize())) {
538     LLVMContext &Ctx = MF.getFunction()->getContext();
539     DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "local memory",
540                                      MFI->getLDSSize(), DS_Error);
541     Ctx.diagnose(Diag);
542   }
543 
544   // SGPRBlocks is actual number of SGPR blocks minus 1.
545   ProgInfo.SGPRBlocks = alignTo(ProgInfo.NumSGPRsForWavesPerEU,
546                                 STM.getSGPREncodingGranule());
547   ProgInfo.SGPRBlocks = ProgInfo.SGPRBlocks / STM.getSGPREncodingGranule() - 1;
548 
549   // VGPRBlocks is actual number of VGPR blocks minus 1.
550   ProgInfo.VGPRBlocks = alignTo(ProgInfo.NumVGPRsForWavesPerEU,
551                                 STM.getVGPREncodingGranule());
552   ProgInfo.VGPRBlocks = ProgInfo.VGPRBlocks / STM.getVGPREncodingGranule() - 1;
553 
554   // Record first reserved VGPR and number of reserved VGPRs.
555   ProgInfo.ReservedVGPRFirst = STM.debuggerReserveRegs() ? ProgInfo.NumVGPR : 0;
556   ProgInfo.ReservedVGPRCount = STM.getReservedNumVGPRs(MF);
557 
558   // Update DebuggerWavefrontPrivateSegmentOffsetSGPR and
559   // DebuggerPrivateSegmentBufferSGPR fields if "amdgpu-debugger-emit-prologue"
560   // attribute was requested.
561   if (STM.debuggerEmitPrologue()) {
562     ProgInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR =
563       RI->getHWRegIndex(MFI->getScratchWaveOffsetReg());
564     ProgInfo.DebuggerPrivateSegmentBufferSGPR =
565       RI->getHWRegIndex(MFI->getScratchRSrcReg());
566   }
567 
568   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
569   // register.
570   ProgInfo.FloatMode = getFPMode(MF);
571 
572   ProgInfo.IEEEMode = STM.enableIEEEBit(MF);
573 
574   // Make clamp modifier on NaN input returns 0.
575   ProgInfo.DX10Clamp = STM.enableDX10Clamp();
576 
577   const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
578   ProgInfo.ScratchSize = FrameInfo.getStackSize();
579 
580   unsigned LDSAlignShift;
581   if (STM.getGeneration() < SISubtarget::SEA_ISLANDS) {
582     // LDS is allocated in 64 dword blocks.
583     LDSAlignShift = 8;
584   } else {
585     // LDS is allocated in 128 dword blocks.
586     LDSAlignShift = 9;
587   }
588 
589   unsigned LDSSpillSize =
590     MFI->getLDSWaveSpillSize() * MFI->getMaxFlatWorkGroupSize();
591 
592   ProgInfo.LDSSize = MFI->getLDSSize() + LDSSpillSize;
593   ProgInfo.LDSBlocks =
594       alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
595 
596   // Scratch is allocated in 256 dword blocks.
597   unsigned ScratchAlignShift = 10;
598   // We need to program the hardware with the amount of scratch memory that
599   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
600   // scratch memory used per thread.
601   ProgInfo.ScratchBlocks =
602       alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
603               1ULL << ScratchAlignShift) >>
604       ScratchAlignShift;
605 
606   ProgInfo.ComputePGMRSrc1 =
607       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
608       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
609       S_00B848_PRIORITY(ProgInfo.Priority) |
610       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
611       S_00B848_PRIV(ProgInfo.Priv) |
612       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
613       S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
614       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
615 
616   // 0 = X, 1 = XY, 2 = XYZ
617   unsigned TIDIGCompCnt = 0;
618   if (MFI->hasWorkItemIDZ())
619     TIDIGCompCnt = 2;
620   else if (MFI->hasWorkItemIDY())
621     TIDIGCompCnt = 1;
622 
623   ProgInfo.ComputePGMRSrc2 =
624       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
625       S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
626       S_00B84C_TRAP_HANDLER(STM.isTrapHandlerEnabled()) |
627       S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
628       S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
629       S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
630       S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
631       S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
632       S_00B84C_EXCP_EN_MSB(0) |
633       S_00B84C_LDS_SIZE(ProgInfo.LDSBlocks) |
634       S_00B84C_EXCP_EN(0);
635 }
636 
637 static unsigned getRsrcReg(CallingConv::ID CallConv) {
638   switch (CallConv) {
639   default: LLVM_FALLTHROUGH;
640   case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
641   case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
642   case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
643   case CallingConv::AMDGPU_VS: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
644   }
645 }
646 
647 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
648                                          const SIProgramInfo &KernelInfo) {
649   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
650   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
651   unsigned RsrcReg = getRsrcReg(MF.getFunction()->getCallingConv());
652 
653   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
654     OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
655 
656     OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc1, 4);
657 
658     OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
659     OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc2, 4);
660 
661     OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
662     OutStreamer->EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4);
663 
664     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
665     // 0" comment but I don't see a corresponding field in the register spec.
666   } else {
667     OutStreamer->EmitIntValue(RsrcReg, 4);
668     OutStreamer->EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
669                               S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4);
670     if (STM.isVGPRSpillingEnabled(*MF.getFunction())) {
671       OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
672       OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(KernelInfo.ScratchBlocks), 4);
673     }
674   }
675 
676   if (MF.getFunction()->getCallingConv() == CallingConv::AMDGPU_PS) {
677     OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
678     OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4);
679     OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
680     OutStreamer->EmitIntValue(MFI->getPSInputEnable(), 4);
681     OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
682     OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4);
683   }
684 
685   OutStreamer->EmitIntValue(R_SPILLED_SGPRS, 4);
686   OutStreamer->EmitIntValue(MFI->getNumSpilledSGPRs(), 4);
687   OutStreamer->EmitIntValue(R_SPILLED_VGPRS, 4);
688   OutStreamer->EmitIntValue(MFI->getNumSpilledVGPRs(), 4);
689 }
690 
691 // This is supposed to be log2(Size)
692 static amd_element_byte_size_t getElementByteSizeValue(unsigned Size) {
693   switch (Size) {
694   case 4:
695     return AMD_ELEMENT_4_BYTES;
696   case 8:
697     return AMD_ELEMENT_8_BYTES;
698   case 16:
699     return AMD_ELEMENT_16_BYTES;
700   default:
701     llvm_unreachable("invalid private_element_size");
702   }
703 }
704 
705 void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out,
706                                         const SIProgramInfo &KernelInfo,
707                                         const MachineFunction &MF) const {
708   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
709   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
710 
711   AMDGPU::initDefaultAMDKernelCodeT(Out, STM.getFeatureBits());
712 
713   Out.compute_pgm_resource_registers =
714       KernelInfo.ComputePGMRSrc1 |
715       (KernelInfo.ComputePGMRSrc2 << 32);
716   Out.code_properties = AMD_CODE_PROPERTY_IS_PTR64;
717 
718   AMD_HSA_BITS_SET(Out.code_properties,
719                    AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE,
720                    getElementByteSizeValue(STM.getMaxPrivateElementSize()));
721 
722   if (MFI->hasPrivateSegmentBuffer()) {
723     Out.code_properties |=
724       AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
725   }
726 
727   if (MFI->hasDispatchPtr())
728     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
729 
730   if (MFI->hasQueuePtr())
731     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
732 
733   if (MFI->hasKernargSegmentPtr())
734     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
735 
736   if (MFI->hasDispatchID())
737     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
738 
739   if (MFI->hasFlatScratchInit())
740     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
741 
742   if (MFI->hasGridWorkgroupCountX()) {
743     Out.code_properties |=
744       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X;
745   }
746 
747   if (MFI->hasGridWorkgroupCountY()) {
748     Out.code_properties |=
749       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y;
750   }
751 
752   if (MFI->hasGridWorkgroupCountZ()) {
753     Out.code_properties |=
754       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z;
755   }
756 
757   if (MFI->hasDispatchPtr())
758     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
759 
760   if (STM.debuggerSupported())
761     Out.code_properties |= AMD_CODE_PROPERTY_IS_DEBUG_SUPPORTED;
762 
763   if (STM.isXNACKEnabled())
764     Out.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED;
765 
766   // FIXME: Should use getKernArgSize
767   Out.kernarg_segment_byte_size =
768     STM.getKernArgSegmentSize(MF, MFI->getABIArgOffset());
769   Out.wavefront_sgpr_count = KernelInfo.NumSGPR;
770   Out.workitem_vgpr_count = KernelInfo.NumVGPR;
771   Out.workitem_private_segment_byte_size = KernelInfo.ScratchSize;
772   Out.workgroup_group_segment_byte_size = KernelInfo.LDSSize;
773   Out.reserved_vgpr_first = KernelInfo.ReservedVGPRFirst;
774   Out.reserved_vgpr_count = KernelInfo.ReservedVGPRCount;
775 
776   // These alignment values are specified in powers of two, so alignment =
777   // 2^n.  The minimum alignment is 2^4 = 16.
778   Out.kernarg_segment_alignment = std::max((size_t)4,
779       countTrailingZeros(MFI->getMaxKernArgAlign()));
780 
781   if (STM.debuggerEmitPrologue()) {
782     Out.debug_wavefront_private_segment_offset_sgpr =
783       KernelInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR;
784     Out.debug_private_segment_buffer_sgpr =
785       KernelInfo.DebuggerPrivateSegmentBufferSGPR;
786   }
787 }
788 
789 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
790                                        unsigned AsmVariant,
791                                        const char *ExtraCode, raw_ostream &O) {
792   if (ExtraCode && ExtraCode[0]) {
793     if (ExtraCode[1] != 0)
794       return true; // Unknown modifier.
795 
796     switch (ExtraCode[0]) {
797     default:
798       // See if this is a generic print operand
799       return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
800     case 'r':
801       break;
802     }
803   }
804 
805   AMDGPUInstPrinter::printRegOperand(MI->getOperand(OpNo).getReg(), O,
806                    *TM.getSubtargetImpl(*MF->getFunction())->getRegisterInfo());
807   return false;
808 }
809