1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU assembly printer --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 ///
11 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
12 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
13 /// an MCObjectStreamer it outputs binary code.
14 //
15 //===----------------------------------------------------------------------===//
16 //
17 
18 #include "AMDGPUAsmPrinter.h"
19 #include "AMDGPU.h"
20 #include "AMDGPUSubtarget.h"
21 #include "AMDGPUTargetMachine.h"
22 #include "MCTargetDesc/AMDGPUInstPrinter.h"
23 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
24 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
25 #include "R600AsmPrinter.h"
26 #include "R600Defines.h"
27 #include "R600MachineFunctionInfo.h"
28 #include "R600RegisterInfo.h"
29 #include "SIDefines.h"
30 #include "SIInstrInfo.h"
31 #include "SIMachineFunctionInfo.h"
32 #include "SIRegisterInfo.h"
33 #include "TargetInfo/AMDGPUTargetInfo.h"
34 #include "Utils/AMDGPUBaseInfo.h"
35 #include "llvm/BinaryFormat/ELF.h"
36 #include "llvm/CodeGen/MachineFrameInfo.h"
37 #include "llvm/IR/DiagnosticInfo.h"
38 #include "llvm/MC/MCAssembler.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCSectionELF.h"
41 #include "llvm/MC/MCStreamer.h"
42 #include "llvm/Support/AMDGPUMetadata.h"
43 #include "llvm/Support/MathExtras.h"
44 #include "llvm/Support/TargetParser.h"
45 #include "llvm/Support/TargetRegistry.h"
46 #include "llvm/Target/TargetLoweringObjectFile.h"
47 
48 using namespace llvm;
49 using namespace llvm::AMDGPU;
50 using namespace llvm::AMDGPU::HSAMD;
51 
52 // This should get the default rounding mode from the kernel. We just set the
53 // default here, but this could change if the OpenCL rounding mode pragmas are
54 // used.
55 //
56 // The denormal mode here should match what is reported by the OpenCL runtime
57 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
58 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
59 //
60 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
61 // precision, and leaves single precision to flush all and does not report
62 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
63 // CL_FP_DENORM for both.
64 //
65 // FIXME: It seems some instructions do not support single precision denormals
66 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
67 // and sin_f32, cos_f32 on most parts).
68 
69 // We want to use these instructions, and using fp32 denormals also causes
70 // instructions to run at the double precision rate for the device so it's
71 // probably best to just report no single precision denormals.
72 static uint32_t getFPMode(AMDGPU::SIModeRegisterDefaults Mode) {
73   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
74          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
75          FP_DENORM_MODE_SP(Mode.fpDenormModeSPValue()) |
76          FP_DENORM_MODE_DP(Mode.fpDenormModeDPValue());
77 }
78 
79 static AsmPrinter *
80 createAMDGPUAsmPrinterPass(TargetMachine &tm,
81                            std::unique_ptr<MCStreamer> &&Streamer) {
82   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
83 }
84 
85 extern "C" void LLVM_EXTERNAL_VISIBILITY LLVMInitializeAMDGPUAsmPrinter() {
86   TargetRegistry::RegisterAsmPrinter(getTheAMDGPUTarget(),
87                                      llvm::createR600AsmPrinterPass);
88   TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(),
89                                      createAMDGPUAsmPrinterPass);
90 }
91 
92 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
93                                    std::unique_ptr<MCStreamer> Streamer)
94   : AsmPrinter(TM, std::move(Streamer)) {
95     if (IsaInfo::hasCodeObjectV3(getGlobalSTI()))
96       HSAMetadataStream.reset(new MetadataStreamerV3());
97     else
98       HSAMetadataStream.reset(new MetadataStreamerV2());
99 }
100 
101 StringRef AMDGPUAsmPrinter::getPassName() const {
102   return "AMDGPU Assembly Printer";
103 }
104 
105 const MCSubtargetInfo *AMDGPUAsmPrinter::getGlobalSTI() const {
106   return TM.getMCSubtargetInfo();
107 }
108 
109 AMDGPUTargetStreamer* AMDGPUAsmPrinter::getTargetStreamer() const {
110   if (!OutStreamer)
111     return nullptr;
112   return static_cast<AMDGPUTargetStreamer*>(OutStreamer->getTargetStreamer());
113 }
114 
115 void AMDGPUAsmPrinter::emitStartOfAsmFile(Module &M) {
116   if (IsaInfo::hasCodeObjectV3(getGlobalSTI())) {
117     std::string ExpectedTarget;
118     raw_string_ostream ExpectedTargetOS(ExpectedTarget);
119     IsaInfo::streamIsaVersion(getGlobalSTI(), ExpectedTargetOS);
120 
121     getTargetStreamer()->EmitDirectiveAMDGCNTarget(ExpectedTarget);
122   }
123 
124   if (TM.getTargetTriple().getOS() != Triple::AMDHSA &&
125       TM.getTargetTriple().getOS() != Triple::AMDPAL)
126     return;
127 
128   if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
129     HSAMetadataStream->begin(M);
130 
131   if (TM.getTargetTriple().getOS() == Triple::AMDPAL)
132     getTargetStreamer()->getPALMetadata()->readFromIR(M);
133 
134   if (IsaInfo::hasCodeObjectV3(getGlobalSTI()))
135     return;
136 
137   // HSA emits NT_AMDGPU_HSA_CODE_OBJECT_VERSION for code objects v2.
138   if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
139     getTargetStreamer()->EmitDirectiveHSACodeObjectVersion(2, 1);
140 
141   // HSA and PAL emit NT_AMDGPU_HSA_ISA for code objects v2.
142   IsaVersion Version = getIsaVersion(getGlobalSTI()->getCPU());
143   getTargetStreamer()->EmitDirectiveHSACodeObjectISA(
144       Version.Major, Version.Minor, Version.Stepping, "AMD", "AMDGPU");
145 }
146 
147 void AMDGPUAsmPrinter::emitEndOfAsmFile(Module &M) {
148   // Following code requires TargetStreamer to be present.
149   if (!getTargetStreamer())
150     return;
151 
152   if (!IsaInfo::hasCodeObjectV3(getGlobalSTI())) {
153     // Emit ISA Version (NT_AMD_AMDGPU_ISA).
154     std::string ISAVersionString;
155     raw_string_ostream ISAVersionStream(ISAVersionString);
156     IsaInfo::streamIsaVersion(getGlobalSTI(), ISAVersionStream);
157     getTargetStreamer()->EmitISAVersion(ISAVersionStream.str());
158   }
159 
160   // Emit HSA Metadata (NT_AMD_AMDGPU_HSA_METADATA).
161   if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
162     HSAMetadataStream->end();
163     bool Success = HSAMetadataStream->emitTo(*getTargetStreamer());
164     (void)Success;
165     assert(Success && "Malformed HSA Metadata");
166   }
167 }
168 
169 bool AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough(
170   const MachineBasicBlock *MBB) const {
171   if (!AsmPrinter::isBlockOnlyReachableByFallthrough(MBB))
172     return false;
173 
174   if (MBB->empty())
175     return true;
176 
177   // If this is a block implementing a long branch, an expression relative to
178   // the start of the block is needed.  to the start of the block.
179   // XXX - Is there a smarter way to check this?
180   return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
181 }
182 
183 void AMDGPUAsmPrinter::emitFunctionBodyStart() {
184   const SIMachineFunctionInfo &MFI = *MF->getInfo<SIMachineFunctionInfo>();
185   if (!MFI.isEntryFunction())
186     return;
187 
188   const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
189   const Function &F = MF->getFunction();
190   if (!STM.hasCodeObjectV3() && STM.isAmdHsaOrMesa(F) &&
191       (F.getCallingConv() == CallingConv::AMDGPU_KERNEL ||
192        F.getCallingConv() == CallingConv::SPIR_KERNEL)) {
193     amd_kernel_code_t KernelCode;
194     getAmdKernelCode(KernelCode, CurrentProgramInfo, *MF);
195     getTargetStreamer()->EmitAMDKernelCodeT(KernelCode);
196   }
197 
198   if (STM.isAmdHsaOS())
199     HSAMetadataStream->emitKernel(*MF, CurrentProgramInfo);
200 }
201 
202 void AMDGPUAsmPrinter::emitFunctionBodyEnd() {
203   const SIMachineFunctionInfo &MFI = *MF->getInfo<SIMachineFunctionInfo>();
204   if (!MFI.isEntryFunction())
205     return;
206 
207   if (!IsaInfo::hasCodeObjectV3(getGlobalSTI()) ||
208       TM.getTargetTriple().getOS() != Triple::AMDHSA)
209     return;
210 
211   auto &Streamer = getTargetStreamer()->getStreamer();
212   auto &Context = Streamer.getContext();
213   auto &ObjectFileInfo = *Context.getObjectFileInfo();
214   auto &ReadOnlySection = *ObjectFileInfo.getReadOnlySection();
215 
216   Streamer.PushSection();
217   Streamer.SwitchSection(&ReadOnlySection);
218 
219   // CP microcode requires the kernel descriptor to be allocated on 64 byte
220   // alignment.
221   Streamer.emitValueToAlignment(64, 0, 1, 0);
222   if (ReadOnlySection.getAlignment() < 64)
223     ReadOnlySection.setAlignment(Align(64));
224 
225   const MCSubtargetInfo &STI = MF->getSubtarget();
226 
227   SmallString<128> KernelName;
228   getNameWithPrefix(KernelName, &MF->getFunction());
229   getTargetStreamer()->EmitAmdhsaKernelDescriptor(
230       STI, KernelName, getAmdhsaKernelDescriptor(*MF, CurrentProgramInfo),
231       CurrentProgramInfo.NumVGPRsForWavesPerEU,
232       CurrentProgramInfo.NumSGPRsForWavesPerEU -
233           IsaInfo::getNumExtraSGPRs(&STI,
234                                     CurrentProgramInfo.VCCUsed,
235                                     CurrentProgramInfo.FlatUsed),
236       CurrentProgramInfo.VCCUsed, CurrentProgramInfo.FlatUsed,
237       hasXNACK(STI));
238 
239   Streamer.PopSection();
240 }
241 
242 void AMDGPUAsmPrinter::emitFunctionEntryLabel() {
243   if (IsaInfo::hasCodeObjectV3(getGlobalSTI()) &&
244       TM.getTargetTriple().getOS() == Triple::AMDHSA) {
245     AsmPrinter::emitFunctionEntryLabel();
246     return;
247   }
248 
249   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
250   const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
251   if (MFI->isEntryFunction() && STM.isAmdHsaOrMesa(MF->getFunction())) {
252     SmallString<128> SymbolName;
253     getNameWithPrefix(SymbolName, &MF->getFunction()),
254     getTargetStreamer()->EmitAMDGPUSymbolType(
255         SymbolName, ELF::STT_AMDGPU_HSA_KERNEL);
256   }
257   if (DumpCodeInstEmitter) {
258     // Disassemble function name label to text.
259     DisasmLines.push_back(MF->getName().str() + ":");
260     DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size());
261     HexLines.push_back("");
262   }
263 
264   AsmPrinter::emitFunctionEntryLabel();
265 }
266 
267 void AMDGPUAsmPrinter::emitBasicBlockStart(const MachineBasicBlock &MBB) {
268   if (DumpCodeInstEmitter && !isBlockOnlyReachableByFallthrough(&MBB)) {
269     // Write a line for the basic block label if it is not only fallthrough.
270     DisasmLines.push_back(
271         (Twine("BB") + Twine(getFunctionNumber())
272          + "_" + Twine(MBB.getNumber()) + ":").str());
273     DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size());
274     HexLines.push_back("");
275   }
276   AsmPrinter::emitBasicBlockStart(MBB);
277 }
278 
279 void AMDGPUAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) {
280   if (GV->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) {
281     if (GV->hasInitializer() && !isa<UndefValue>(GV->getInitializer())) {
282       OutContext.reportError({},
283                              Twine(GV->getName()) +
284                                  ": unsupported initializer for address space");
285       return;
286     }
287 
288     // LDS variables aren't emitted in HSA or PAL yet.
289     const Triple::OSType OS = TM.getTargetTriple().getOS();
290     if (OS == Triple::AMDHSA || OS == Triple::AMDPAL)
291       return;
292 
293     MCSymbol *GVSym = getSymbol(GV);
294 
295     GVSym->redefineIfPossible();
296     if (GVSym->isDefined() || GVSym->isVariable())
297       report_fatal_error("symbol '" + Twine(GVSym->getName()) +
298                          "' is already defined");
299 
300     const DataLayout &DL = GV->getParent()->getDataLayout();
301     uint64_t Size = DL.getTypeAllocSize(GV->getValueType());
302     unsigned Align = GV->getAlignment();
303     if (!Align)
304       Align = 4;
305 
306     emitVisibility(GVSym, GV->getVisibility(), !GV->isDeclaration());
307     emitLinkage(GV, GVSym);
308     if (auto TS = getTargetStreamer())
309       TS->emitAMDGPULDS(GVSym, Size, Align);
310     return;
311   }
312 
313   AsmPrinter::emitGlobalVariable(GV);
314 }
315 
316 bool AMDGPUAsmPrinter::doFinalization(Module &M) {
317   CallGraphResourceInfo.clear();
318 
319   // Pad with s_code_end to help tools and guard against instruction prefetch
320   // causing stale data in caches. Arguably this should be done by the linker,
321   // which is why this isn't done for Mesa.
322   const MCSubtargetInfo &STI = *getGlobalSTI();
323   if (AMDGPU::isGFX10(STI) &&
324       (STI.getTargetTriple().getOS() == Triple::AMDHSA ||
325        STI.getTargetTriple().getOS() == Triple::AMDPAL)) {
326     OutStreamer->SwitchSection(getObjFileLowering().getTextSection());
327     getTargetStreamer()->EmitCodeEnd();
328   }
329 
330   return AsmPrinter::doFinalization(M);
331 }
332 
333 // Print comments that apply to both callable functions and entry points.
334 void AMDGPUAsmPrinter::emitCommonFunctionComments(
335   uint32_t NumVGPR,
336   Optional<uint32_t> NumAGPR,
337   uint32_t TotalNumVGPR,
338   uint32_t NumSGPR,
339   uint64_t ScratchSize,
340   uint64_t CodeSize,
341   const AMDGPUMachineFunction *MFI) {
342   OutStreamer->emitRawComment(" codeLenInByte = " + Twine(CodeSize), false);
343   OutStreamer->emitRawComment(" NumSgprs: " + Twine(NumSGPR), false);
344   OutStreamer->emitRawComment(" NumVgprs: " + Twine(NumVGPR), false);
345   if (NumAGPR) {
346     OutStreamer->emitRawComment(" NumAgprs: " + Twine(*NumAGPR), false);
347     OutStreamer->emitRawComment(" TotalNumVgprs: " + Twine(TotalNumVGPR),
348                                 false);
349   }
350   OutStreamer->emitRawComment(" ScratchSize: " + Twine(ScratchSize), false);
351   OutStreamer->emitRawComment(" MemoryBound: " + Twine(MFI->isMemoryBound()),
352                               false);
353 }
354 
355 uint16_t AMDGPUAsmPrinter::getAmdhsaKernelCodeProperties(
356     const MachineFunction &MF) const {
357   const SIMachineFunctionInfo &MFI = *MF.getInfo<SIMachineFunctionInfo>();
358   uint16_t KernelCodeProperties = 0;
359 
360   if (MFI.hasPrivateSegmentBuffer()) {
361     KernelCodeProperties |=
362         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
363   }
364   if (MFI.hasDispatchPtr()) {
365     KernelCodeProperties |=
366         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
367   }
368   if (MFI.hasQueuePtr()) {
369     KernelCodeProperties |=
370         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
371   }
372   if (MFI.hasKernargSegmentPtr()) {
373     KernelCodeProperties |=
374         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
375   }
376   if (MFI.hasDispatchID()) {
377     KernelCodeProperties |=
378         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
379   }
380   if (MFI.hasFlatScratchInit()) {
381     KernelCodeProperties |=
382         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
383   }
384   if (MF.getSubtarget<GCNSubtarget>().isWave32()) {
385     KernelCodeProperties |=
386         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32;
387   }
388 
389   return KernelCodeProperties;
390 }
391 
392 amdhsa::kernel_descriptor_t AMDGPUAsmPrinter::getAmdhsaKernelDescriptor(
393     const MachineFunction &MF,
394     const SIProgramInfo &PI) const {
395   amdhsa::kernel_descriptor_t KernelDescriptor;
396   memset(&KernelDescriptor, 0x0, sizeof(KernelDescriptor));
397 
398   assert(isUInt<32>(PI.ScratchSize));
399   assert(isUInt<32>(PI.ComputePGMRSrc1));
400   assert(isUInt<32>(PI.ComputePGMRSrc2));
401 
402   KernelDescriptor.group_segment_fixed_size = PI.LDSSize;
403   KernelDescriptor.private_segment_fixed_size = PI.ScratchSize;
404   KernelDescriptor.compute_pgm_rsrc1 = PI.ComputePGMRSrc1;
405   KernelDescriptor.compute_pgm_rsrc2 = PI.ComputePGMRSrc2;
406   KernelDescriptor.kernel_code_properties = getAmdhsaKernelCodeProperties(MF);
407 
408   return KernelDescriptor;
409 }
410 
411 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
412   CurrentProgramInfo = SIProgramInfo();
413 
414   const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
415 
416   // The starting address of all shader programs must be 256 bytes aligned.
417   // Regular functions just need the basic required instruction alignment.
418   MF.setAlignment(MFI->isEntryFunction() ? Align(256) : Align(4));
419 
420   SetupMachineFunction(MF);
421 
422   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
423   MCContext &Context = getObjFileLowering().getContext();
424   // FIXME: This should be an explicit check for Mesa.
425   if (!STM.isAmdHsaOS() && !STM.isAmdPalOS()) {
426     MCSectionELF *ConfigSection =
427         Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
428     OutStreamer->SwitchSection(ConfigSection);
429   }
430 
431   if (MFI->isEntryFunction()) {
432     getSIProgramInfo(CurrentProgramInfo, MF);
433   } else {
434     auto I = CallGraphResourceInfo.insert(
435       std::make_pair(&MF.getFunction(), SIFunctionResourceInfo()));
436     SIFunctionResourceInfo &Info = I.first->second;
437     assert(I.second && "should only be called once per function");
438     Info = analyzeResourceUsage(MF);
439   }
440 
441   if (STM.isAmdPalOS())
442     EmitPALMetadata(MF, CurrentProgramInfo);
443   else if (!STM.isAmdHsaOS()) {
444     EmitProgramInfoSI(MF, CurrentProgramInfo);
445   }
446 
447   DumpCodeInstEmitter = nullptr;
448   if (STM.dumpCode()) {
449     // For -dumpcode, get the assembler out of the streamer, even if it does
450     // not really want to let us have it. This only works with -filetype=obj.
451     bool SaveFlag = OutStreamer->getUseAssemblerInfoForParsing();
452     OutStreamer->setUseAssemblerInfoForParsing(true);
453     MCAssembler *Assembler = OutStreamer->getAssemblerPtr();
454     OutStreamer->setUseAssemblerInfoForParsing(SaveFlag);
455     if (Assembler)
456       DumpCodeInstEmitter = Assembler->getEmitterPtr();
457   }
458 
459   DisasmLines.clear();
460   HexLines.clear();
461   DisasmLineMaxLen = 0;
462 
463   emitFunctionBody();
464 
465   if (isVerbose()) {
466     MCSectionELF *CommentSection =
467         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
468     OutStreamer->SwitchSection(CommentSection);
469 
470     if (!MFI->isEntryFunction()) {
471       OutStreamer->emitRawComment(" Function info:", false);
472       SIFunctionResourceInfo &Info = CallGraphResourceInfo[&MF.getFunction()];
473       emitCommonFunctionComments(
474         Info.NumVGPR,
475         STM.hasMAIInsts() ? Info.NumAGPR : Optional<uint32_t>(),
476         Info.getTotalNumVGPRs(STM),
477         Info.getTotalNumSGPRs(MF.getSubtarget<GCNSubtarget>()),
478         Info.PrivateSegmentSize,
479         getFunctionCodeSize(MF), MFI);
480       return false;
481     }
482 
483     OutStreamer->emitRawComment(" Kernel info:", false);
484     emitCommonFunctionComments(CurrentProgramInfo.NumArchVGPR,
485                                STM.hasMAIInsts()
486                                  ? CurrentProgramInfo.NumAccVGPR
487                                  : Optional<uint32_t>(),
488                                CurrentProgramInfo.NumVGPR,
489                                CurrentProgramInfo.NumSGPR,
490                                CurrentProgramInfo.ScratchSize,
491                                getFunctionCodeSize(MF), MFI);
492 
493     OutStreamer->emitRawComment(
494       " FloatMode: " + Twine(CurrentProgramInfo.FloatMode), false);
495     OutStreamer->emitRawComment(
496       " IeeeMode: " + Twine(CurrentProgramInfo.IEEEMode), false);
497     OutStreamer->emitRawComment(
498       " LDSByteSize: " + Twine(CurrentProgramInfo.LDSSize) +
499       " bytes/workgroup (compile time only)", false);
500 
501     OutStreamer->emitRawComment(
502       " SGPRBlocks: " + Twine(CurrentProgramInfo.SGPRBlocks), false);
503     OutStreamer->emitRawComment(
504       " VGPRBlocks: " + Twine(CurrentProgramInfo.VGPRBlocks), false);
505 
506     OutStreamer->emitRawComment(
507       " NumSGPRsForWavesPerEU: " +
508       Twine(CurrentProgramInfo.NumSGPRsForWavesPerEU), false);
509     OutStreamer->emitRawComment(
510       " NumVGPRsForWavesPerEU: " +
511       Twine(CurrentProgramInfo.NumVGPRsForWavesPerEU), false);
512 
513     OutStreamer->emitRawComment(
514       " Occupancy: " +
515       Twine(CurrentProgramInfo.Occupancy), false);
516 
517     OutStreamer->emitRawComment(
518       " WaveLimiterHint : " + Twine(MFI->needsWaveLimiter()), false);
519 
520     OutStreamer->emitRawComment(
521       " COMPUTE_PGM_RSRC2:USER_SGPR: " +
522       Twine(G_00B84C_USER_SGPR(CurrentProgramInfo.ComputePGMRSrc2)), false);
523     OutStreamer->emitRawComment(
524       " COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
525       Twine(G_00B84C_TRAP_HANDLER(CurrentProgramInfo.ComputePGMRSrc2)), false);
526     OutStreamer->emitRawComment(
527       " COMPUTE_PGM_RSRC2:TGID_X_EN: " +
528       Twine(G_00B84C_TGID_X_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
529     OutStreamer->emitRawComment(
530       " COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
531       Twine(G_00B84C_TGID_Y_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
532     OutStreamer->emitRawComment(
533       " COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
534       Twine(G_00B84C_TGID_Z_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
535     OutStreamer->emitRawComment(
536       " COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
537       Twine(G_00B84C_TIDIG_COMP_CNT(CurrentProgramInfo.ComputePGMRSrc2)),
538       false);
539   }
540 
541   if (DumpCodeInstEmitter) {
542 
543     OutStreamer->SwitchSection(
544         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
545 
546     for (size_t i = 0; i < DisasmLines.size(); ++i) {
547       std::string Comment = "\n";
548       if (!HexLines[i].empty()) {
549         Comment = std::string(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
550         Comment += " ; " + HexLines[i] + "\n";
551       }
552 
553       OutStreamer->emitBytes(StringRef(DisasmLines[i]));
554       OutStreamer->emitBytes(StringRef(Comment));
555     }
556   }
557 
558   return false;
559 }
560 
561 uint64_t AMDGPUAsmPrinter::getFunctionCodeSize(const MachineFunction &MF) const {
562   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
563   const SIInstrInfo *TII = STM.getInstrInfo();
564 
565   uint64_t CodeSize = 0;
566 
567   for (const MachineBasicBlock &MBB : MF) {
568     for (const MachineInstr &MI : MBB) {
569       // TODO: CodeSize should account for multiple functions.
570 
571       // TODO: Should we count size of debug info?
572       if (MI.isDebugInstr())
573         continue;
574 
575       CodeSize += TII->getInstSizeInBytes(MI);
576     }
577   }
578 
579   return CodeSize;
580 }
581 
582 static bool hasAnyNonFlatUseOfReg(const MachineRegisterInfo &MRI,
583                                   const SIInstrInfo &TII,
584                                   unsigned Reg) {
585   for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) {
586     if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent()))
587       return true;
588   }
589 
590   return false;
591 }
592 
593 int32_t AMDGPUAsmPrinter::SIFunctionResourceInfo::getTotalNumSGPRs(
594   const GCNSubtarget &ST) const {
595   return NumExplicitSGPR + IsaInfo::getNumExtraSGPRs(&ST,
596                                                      UsesVCC, UsesFlatScratch);
597 }
598 
599 int32_t AMDGPUAsmPrinter::SIFunctionResourceInfo::getTotalNumVGPRs(
600   const GCNSubtarget &ST) const {
601   return std::max(NumVGPR, NumAGPR);
602 }
603 
604 AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
605   const MachineFunction &MF) const {
606   SIFunctionResourceInfo Info;
607 
608   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
609   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
610   const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
611   const MachineRegisterInfo &MRI = MF.getRegInfo();
612   const SIInstrInfo *TII = ST.getInstrInfo();
613   const SIRegisterInfo &TRI = TII->getRegisterInfo();
614 
615   Info.UsesFlatScratch = MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_LO) ||
616                          MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_HI);
617 
618   // Even if FLAT_SCRATCH is implicitly used, it has no effect if flat
619   // instructions aren't used to access the scratch buffer. Inline assembly may
620   // need it though.
621   //
622   // If we only have implicit uses of flat_scr on flat instructions, it is not
623   // really needed.
624   if (Info.UsesFlatScratch && !MFI->hasFlatScratchInit() &&
625       (!hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR) &&
626        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_LO) &&
627        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_HI))) {
628     Info.UsesFlatScratch = false;
629   }
630 
631   Info.HasDynamicallySizedStack = FrameInfo.hasVarSizedObjects();
632   Info.PrivateSegmentSize = FrameInfo.getStackSize();
633   if (MFI->isStackRealigned())
634     Info.PrivateSegmentSize += FrameInfo.getMaxAlignment();
635 
636 
637   Info.UsesVCC = MRI.isPhysRegUsed(AMDGPU::VCC_LO) ||
638                  MRI.isPhysRegUsed(AMDGPU::VCC_HI);
639 
640   // If there are no calls, MachineRegisterInfo can tell us the used register
641   // count easily.
642   // A tail call isn't considered a call for MachineFrameInfo's purposes.
643   if (!FrameInfo.hasCalls() && !FrameInfo.hasTailCall()) {
644     MCPhysReg HighestVGPRReg = AMDGPU::NoRegister;
645     for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) {
646       if (MRI.isPhysRegUsed(Reg)) {
647         HighestVGPRReg = Reg;
648         break;
649       }
650     }
651 
652     if (ST.hasMAIInsts()) {
653       MCPhysReg HighestAGPRReg = AMDGPU::NoRegister;
654       for (MCPhysReg Reg : reverse(AMDGPU::AGPR_32RegClass.getRegisters())) {
655         if (MRI.isPhysRegUsed(Reg)) {
656           HighestAGPRReg = Reg;
657           break;
658         }
659       }
660       Info.NumAGPR = HighestAGPRReg == AMDGPU::NoRegister ? 0 :
661         TRI.getHWRegIndex(HighestAGPRReg) + 1;
662     }
663 
664     MCPhysReg HighestSGPRReg = AMDGPU::NoRegister;
665     for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) {
666       if (MRI.isPhysRegUsed(Reg)) {
667         HighestSGPRReg = Reg;
668         break;
669       }
670     }
671 
672     // We found the maximum register index. They start at 0, so add one to get the
673     // number of registers.
674     Info.NumVGPR = HighestVGPRReg == AMDGPU::NoRegister ? 0 :
675       TRI.getHWRegIndex(HighestVGPRReg) + 1;
676     Info.NumExplicitSGPR = HighestSGPRReg == AMDGPU::NoRegister ? 0 :
677       TRI.getHWRegIndex(HighestSGPRReg) + 1;
678 
679     return Info;
680   }
681 
682   int32_t MaxVGPR = -1;
683   int32_t MaxAGPR = -1;
684   int32_t MaxSGPR = -1;
685   uint64_t CalleeFrameSize = 0;
686 
687   for (const MachineBasicBlock &MBB : MF) {
688     for (const MachineInstr &MI : MBB) {
689       // TODO: Check regmasks? Do they occur anywhere except calls?
690       for (const MachineOperand &MO : MI.operands()) {
691         unsigned Width = 0;
692         bool IsSGPR = false;
693         bool IsAGPR = false;
694 
695         if (!MO.isReg())
696           continue;
697 
698         Register Reg = MO.getReg();
699         switch (Reg) {
700         case AMDGPU::EXEC:
701         case AMDGPU::EXEC_LO:
702         case AMDGPU::EXEC_HI:
703         case AMDGPU::SCC:
704         case AMDGPU::M0:
705         case AMDGPU::SRC_SHARED_BASE:
706         case AMDGPU::SRC_SHARED_LIMIT:
707         case AMDGPU::SRC_PRIVATE_BASE:
708         case AMDGPU::SRC_PRIVATE_LIMIT:
709         case AMDGPU::SGPR_NULL:
710           continue;
711 
712         case AMDGPU::SRC_POPS_EXITING_WAVE_ID:
713           llvm_unreachable("src_pops_exiting_wave_id should not be used");
714 
715         case AMDGPU::NoRegister:
716           assert(MI.isDebugInstr());
717           continue;
718 
719         case AMDGPU::VCC:
720         case AMDGPU::VCC_LO:
721         case AMDGPU::VCC_HI:
722           Info.UsesVCC = true;
723           continue;
724 
725         case AMDGPU::FLAT_SCR:
726         case AMDGPU::FLAT_SCR_LO:
727         case AMDGPU::FLAT_SCR_HI:
728           continue;
729 
730         case AMDGPU::XNACK_MASK:
731         case AMDGPU::XNACK_MASK_LO:
732         case AMDGPU::XNACK_MASK_HI:
733           llvm_unreachable("xnack_mask registers should not be used");
734 
735         case AMDGPU::LDS_DIRECT:
736           llvm_unreachable("lds_direct register should not be used");
737 
738         case AMDGPU::TBA:
739         case AMDGPU::TBA_LO:
740         case AMDGPU::TBA_HI:
741         case AMDGPU::TMA:
742         case AMDGPU::TMA_LO:
743         case AMDGPU::TMA_HI:
744           llvm_unreachable("trap handler registers should not be used");
745 
746         case AMDGPU::SRC_VCCZ:
747           llvm_unreachable("src_vccz register should not be used");
748 
749         case AMDGPU::SRC_EXECZ:
750           llvm_unreachable("src_execz register should not be used");
751 
752         case AMDGPU::SRC_SCC:
753           llvm_unreachable("src_scc register should not be used");
754 
755         default:
756           break;
757         }
758 
759         if (AMDGPU::SReg_32RegClass.contains(Reg)) {
760           assert(!AMDGPU::TTMP_32RegClass.contains(Reg) &&
761                  "trap handler registers should not be used");
762           IsSGPR = true;
763           Width = 1;
764         } else if (AMDGPU::VGPR_32RegClass.contains(Reg)) {
765           IsSGPR = false;
766           Width = 1;
767         } else if (AMDGPU::AGPR_32RegClass.contains(Reg)) {
768           IsSGPR = false;
769           IsAGPR = true;
770           Width = 1;
771         } else if (AMDGPU::SReg_64RegClass.contains(Reg)) {
772           assert(!AMDGPU::TTMP_64RegClass.contains(Reg) &&
773                  "trap handler registers should not be used");
774           IsSGPR = true;
775           Width = 2;
776         } else if (AMDGPU::VReg_64RegClass.contains(Reg)) {
777           IsSGPR = false;
778           Width = 2;
779         } else if (AMDGPU::AReg_64RegClass.contains(Reg)) {
780           IsSGPR = false;
781           IsAGPR = true;
782           Width = 2;
783         } else if (AMDGPU::VReg_96RegClass.contains(Reg)) {
784           IsSGPR = false;
785           Width = 3;
786         } else if (AMDGPU::SReg_96RegClass.contains(Reg)) {
787           IsSGPR = true;
788           Width = 3;
789         } else if (AMDGPU::SReg_128RegClass.contains(Reg)) {
790           assert(!AMDGPU::TTMP_128RegClass.contains(Reg) &&
791             "trap handler registers should not be used");
792           IsSGPR = true;
793           Width = 4;
794         } else if (AMDGPU::VReg_128RegClass.contains(Reg)) {
795           IsSGPR = false;
796           Width = 4;
797         } else if (AMDGPU::AReg_128RegClass.contains(Reg)) {
798           IsSGPR = false;
799           IsAGPR = true;
800           Width = 4;
801         } else if (AMDGPU::VReg_160RegClass.contains(Reg)) {
802           IsSGPR = false;
803           Width = 5;
804         } else if (AMDGPU::SReg_160RegClass.contains(Reg)) {
805           IsSGPR = true;
806           Width = 5;
807         } else if (AMDGPU::SReg_256RegClass.contains(Reg)) {
808           assert(!AMDGPU::TTMP_256RegClass.contains(Reg) &&
809             "trap handler registers should not be used");
810           IsSGPR = true;
811           Width = 8;
812         } else if (AMDGPU::VReg_256RegClass.contains(Reg)) {
813           IsSGPR = false;
814           Width = 8;
815         } else if (AMDGPU::SReg_512RegClass.contains(Reg)) {
816           assert(!AMDGPU::TTMP_512RegClass.contains(Reg) &&
817             "trap handler registers should not be used");
818           IsSGPR = true;
819           Width = 16;
820         } else if (AMDGPU::VReg_512RegClass.contains(Reg)) {
821           IsSGPR = false;
822           Width = 16;
823         } else if (AMDGPU::AReg_512RegClass.contains(Reg)) {
824           IsSGPR = false;
825           IsAGPR = true;
826           Width = 16;
827         } else if (AMDGPU::SReg_1024RegClass.contains(Reg)) {
828           IsSGPR = true;
829           Width = 32;
830         } else if (AMDGPU::VReg_1024RegClass.contains(Reg)) {
831           IsSGPR = false;
832           Width = 32;
833         } else if (AMDGPU::AReg_1024RegClass.contains(Reg)) {
834           IsSGPR = false;
835           IsAGPR = true;
836           Width = 32;
837         } else {
838           llvm_unreachable("Unknown register class");
839         }
840         unsigned HWReg = TRI.getHWRegIndex(Reg);
841         int MaxUsed = HWReg + Width - 1;
842         if (IsSGPR) {
843           MaxSGPR = MaxUsed > MaxSGPR ? MaxUsed : MaxSGPR;
844         } else if (IsAGPR) {
845           MaxAGPR = MaxUsed > MaxAGPR ? MaxUsed : MaxAGPR;
846         } else {
847           MaxVGPR = MaxUsed > MaxVGPR ? MaxUsed : MaxVGPR;
848         }
849       }
850 
851       if (MI.isCall()) {
852         // Pseudo used just to encode the underlying global. Is there a better
853         // way to track this?
854 
855         const MachineOperand *CalleeOp
856           = TII->getNamedOperand(MI, AMDGPU::OpName::callee);
857         const Function *Callee = cast<Function>(CalleeOp->getGlobal());
858         if (Callee->isDeclaration()) {
859           // If this is a call to an external function, we can't do much. Make
860           // conservative guesses.
861 
862           // 48 SGPRs - vcc, - flat_scr, -xnack
863           int MaxSGPRGuess =
864             47 - IsaInfo::getNumExtraSGPRs(&ST, true, ST.hasFlatAddressSpace());
865           MaxSGPR = std::max(MaxSGPR, MaxSGPRGuess);
866           MaxVGPR = std::max(MaxVGPR, 23);
867           MaxAGPR = std::max(MaxAGPR, 23);
868 
869           CalleeFrameSize = std::max(CalleeFrameSize, UINT64_C(16384));
870           Info.UsesVCC = true;
871           Info.UsesFlatScratch = ST.hasFlatAddressSpace();
872           Info.HasDynamicallySizedStack = true;
873         } else {
874           // We force CodeGen to run in SCC order, so the callee's register
875           // usage etc. should be the cumulative usage of all callees.
876 
877           auto I = CallGraphResourceInfo.find(Callee);
878           if (I == CallGraphResourceInfo.end()) {
879             // Avoid crashing on undefined behavior with an illegal call to a
880             // kernel. If a callsite's calling convention doesn't match the
881             // function's, it's undefined behavior. If the callsite calling
882             // convention does match, that would have errored earlier.
883             // FIXME: The verifier shouldn't allow this.
884             if (AMDGPU::isEntryFunctionCC(Callee->getCallingConv()))
885               report_fatal_error("invalid call to entry function");
886 
887             llvm_unreachable("callee should have been handled before caller");
888           }
889 
890           MaxSGPR = std::max(I->second.NumExplicitSGPR - 1, MaxSGPR);
891           MaxVGPR = std::max(I->second.NumVGPR - 1, MaxVGPR);
892           MaxAGPR = std::max(I->second.NumAGPR - 1, MaxAGPR);
893           CalleeFrameSize
894             = std::max(I->second.PrivateSegmentSize, CalleeFrameSize);
895           Info.UsesVCC |= I->second.UsesVCC;
896           Info.UsesFlatScratch |= I->second.UsesFlatScratch;
897           Info.HasDynamicallySizedStack |= I->second.HasDynamicallySizedStack;
898           Info.HasRecursion |= I->second.HasRecursion;
899         }
900 
901         if (!Callee->doesNotRecurse())
902           Info.HasRecursion = true;
903       }
904     }
905   }
906 
907   Info.NumExplicitSGPR = MaxSGPR + 1;
908   Info.NumVGPR = MaxVGPR + 1;
909   Info.NumAGPR = MaxAGPR + 1;
910   Info.PrivateSegmentSize += CalleeFrameSize;
911 
912   return Info;
913 }
914 
915 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
916                                         const MachineFunction &MF) {
917   SIFunctionResourceInfo Info = analyzeResourceUsage(MF);
918   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
919 
920   ProgInfo.NumArchVGPR = Info.NumVGPR;
921   ProgInfo.NumAccVGPR = Info.NumAGPR;
922   ProgInfo.NumVGPR = Info.getTotalNumVGPRs(STM);
923   ProgInfo.NumSGPR = Info.NumExplicitSGPR;
924   ProgInfo.ScratchSize = Info.PrivateSegmentSize;
925   ProgInfo.VCCUsed = Info.UsesVCC;
926   ProgInfo.FlatUsed = Info.UsesFlatScratch;
927   ProgInfo.DynamicCallStack = Info.HasDynamicallySizedStack || Info.HasRecursion;
928 
929   if (!isUInt<32>(ProgInfo.ScratchSize)) {
930     DiagnosticInfoStackSize DiagStackSize(MF.getFunction(),
931                                           ProgInfo.ScratchSize, DS_Error);
932     MF.getFunction().getContext().diagnose(DiagStackSize);
933   }
934 
935   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
936 
937   // TODO(scott.linder): The calculations related to SGPR/VGPR blocks are
938   // duplicated in part in AMDGPUAsmParser::calculateGPRBlocks, and could be
939   // unified.
940   unsigned ExtraSGPRs = IsaInfo::getNumExtraSGPRs(
941       &STM, ProgInfo.VCCUsed, ProgInfo.FlatUsed);
942 
943   // Check the addressable register limit before we add ExtraSGPRs.
944   if (STM.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
945       !STM.hasSGPRInitBug()) {
946     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
947     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
948       // This can happen due to a compiler bug or when using inline asm.
949       LLVMContext &Ctx = MF.getFunction().getContext();
950       DiagnosticInfoResourceLimit Diag(MF.getFunction(),
951                                        "addressable scalar registers",
952                                        ProgInfo.NumSGPR, DS_Error,
953                                        DK_ResourceLimit,
954                                        MaxAddressableNumSGPRs);
955       Ctx.diagnose(Diag);
956       ProgInfo.NumSGPR = MaxAddressableNumSGPRs - 1;
957     }
958   }
959 
960   // Account for extra SGPRs and VGPRs reserved for debugger use.
961   ProgInfo.NumSGPR += ExtraSGPRs;
962 
963   // Ensure there are enough SGPRs and VGPRs for wave dispatch, where wave
964   // dispatch registers are function args.
965   unsigned WaveDispatchNumSGPR = 0, WaveDispatchNumVGPR = 0;
966   for (auto &Arg : MF.getFunction().args()) {
967     unsigned NumRegs = (Arg.getType()->getPrimitiveSizeInBits() + 31) / 32;
968     if (Arg.hasAttribute(Attribute::InReg))
969       WaveDispatchNumSGPR += NumRegs;
970     else
971       WaveDispatchNumVGPR += NumRegs;
972   }
973   ProgInfo.NumSGPR = std::max(ProgInfo.NumSGPR, WaveDispatchNumSGPR);
974   ProgInfo.NumVGPR = std::max(ProgInfo.NumVGPR, WaveDispatchNumVGPR);
975 
976   // Adjust number of registers used to meet default/requested minimum/maximum
977   // number of waves per execution unit request.
978   ProgInfo.NumSGPRsForWavesPerEU = std::max(
979     std::max(ProgInfo.NumSGPR, 1u), STM.getMinNumSGPRs(MFI->getMaxWavesPerEU()));
980   ProgInfo.NumVGPRsForWavesPerEU = std::max(
981     std::max(ProgInfo.NumVGPR, 1u), STM.getMinNumVGPRs(MFI->getMaxWavesPerEU()));
982 
983   if (STM.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ||
984       STM.hasSGPRInitBug()) {
985     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
986     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
987       // This can happen due to a compiler bug or when using inline asm to use
988       // the registers which are usually reserved for vcc etc.
989       LLVMContext &Ctx = MF.getFunction().getContext();
990       DiagnosticInfoResourceLimit Diag(MF.getFunction(),
991                                        "scalar registers",
992                                        ProgInfo.NumSGPR, DS_Error,
993                                        DK_ResourceLimit,
994                                        MaxAddressableNumSGPRs);
995       Ctx.diagnose(Diag);
996       ProgInfo.NumSGPR = MaxAddressableNumSGPRs;
997       ProgInfo.NumSGPRsForWavesPerEU = MaxAddressableNumSGPRs;
998     }
999   }
1000 
1001   if (STM.hasSGPRInitBug()) {
1002     ProgInfo.NumSGPR =
1003         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
1004     ProgInfo.NumSGPRsForWavesPerEU =
1005         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
1006   }
1007 
1008   if (MFI->getNumUserSGPRs() > STM.getMaxNumUserSGPRs()) {
1009     LLVMContext &Ctx = MF.getFunction().getContext();
1010     DiagnosticInfoResourceLimit Diag(MF.getFunction(), "user SGPRs",
1011                                      MFI->getNumUserSGPRs(), DS_Error);
1012     Ctx.diagnose(Diag);
1013   }
1014 
1015   if (MFI->getLDSSize() > static_cast<unsigned>(STM.getLocalMemorySize())) {
1016     LLVMContext &Ctx = MF.getFunction().getContext();
1017     DiagnosticInfoResourceLimit Diag(MF.getFunction(), "local memory",
1018                                      MFI->getLDSSize(), DS_Error);
1019     Ctx.diagnose(Diag);
1020   }
1021 
1022   ProgInfo.SGPRBlocks = IsaInfo::getNumSGPRBlocks(
1023       &STM, ProgInfo.NumSGPRsForWavesPerEU);
1024   ProgInfo.VGPRBlocks = IsaInfo::getNumVGPRBlocks(
1025       &STM, ProgInfo.NumVGPRsForWavesPerEU);
1026 
1027   const SIModeRegisterDefaults Mode = MFI->getMode();
1028 
1029   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
1030   // register.
1031   ProgInfo.FloatMode = getFPMode(Mode);
1032 
1033   ProgInfo.IEEEMode = Mode.IEEE;
1034 
1035   // Make clamp modifier on NaN input returns 0.
1036   ProgInfo.DX10Clamp = Mode.DX10Clamp;
1037 
1038   unsigned LDSAlignShift;
1039   if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
1040     // LDS is allocated in 64 dword blocks.
1041     LDSAlignShift = 8;
1042   } else {
1043     // LDS is allocated in 128 dword blocks.
1044     LDSAlignShift = 9;
1045   }
1046 
1047   unsigned LDSSpillSize =
1048     MFI->getLDSWaveSpillSize() * MFI->getMaxFlatWorkGroupSize();
1049 
1050   ProgInfo.LDSSize = MFI->getLDSSize() + LDSSpillSize;
1051   ProgInfo.LDSBlocks =
1052       alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
1053 
1054   // Scratch is allocated in 256 dword blocks.
1055   unsigned ScratchAlignShift = 10;
1056   // We need to program the hardware with the amount of scratch memory that
1057   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
1058   // scratch memory used per thread.
1059   ProgInfo.ScratchBlocks =
1060       alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
1061               1ULL << ScratchAlignShift) >>
1062       ScratchAlignShift;
1063 
1064   if (getIsaVersion(getGlobalSTI()->getCPU()).Major >= 10) {
1065     ProgInfo.WgpMode = STM.isCuModeEnabled() ? 0 : 1;
1066     ProgInfo.MemOrdered = 1;
1067   }
1068 
1069   ProgInfo.ComputePGMRSrc1 =
1070       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
1071       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
1072       S_00B848_PRIORITY(ProgInfo.Priority) |
1073       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
1074       S_00B848_PRIV(ProgInfo.Priv) |
1075       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
1076       S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
1077       S_00B848_IEEE_MODE(ProgInfo.IEEEMode) |
1078       S_00B848_WGP_MODE(ProgInfo.WgpMode) |
1079       S_00B848_MEM_ORDERED(ProgInfo.MemOrdered);
1080 
1081   // 0 = X, 1 = XY, 2 = XYZ
1082   unsigned TIDIGCompCnt = 0;
1083   if (MFI->hasWorkItemIDZ())
1084     TIDIGCompCnt = 2;
1085   else if (MFI->hasWorkItemIDY())
1086     TIDIGCompCnt = 1;
1087 
1088   ProgInfo.ComputePGMRSrc2 =
1089       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
1090       S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
1091       // For AMDHSA, TRAP_HANDLER must be zero, as it is populated by the CP.
1092       S_00B84C_TRAP_HANDLER(STM.isAmdHsaOS() ? 0 : STM.isTrapHandlerEnabled()) |
1093       S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
1094       S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
1095       S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
1096       S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
1097       S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
1098       S_00B84C_EXCP_EN_MSB(0) |
1099       // For AMDHSA, LDS_SIZE must be zero, as it is populated by the CP.
1100       S_00B84C_LDS_SIZE(STM.isAmdHsaOS() ? 0 : ProgInfo.LDSBlocks) |
1101       S_00B84C_EXCP_EN(0);
1102 
1103   ProgInfo.Occupancy = STM.computeOccupancy(MF, ProgInfo.LDSSize,
1104                                             ProgInfo.NumSGPRsForWavesPerEU,
1105                                             ProgInfo.NumVGPRsForWavesPerEU);
1106 }
1107 
1108 static unsigned getRsrcReg(CallingConv::ID CallConv) {
1109   switch (CallConv) {
1110   default: LLVM_FALLTHROUGH;
1111   case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
1112   case CallingConv::AMDGPU_LS: return R_00B528_SPI_SHADER_PGM_RSRC1_LS;
1113   case CallingConv::AMDGPU_HS: return R_00B428_SPI_SHADER_PGM_RSRC1_HS;
1114   case CallingConv::AMDGPU_ES: return R_00B328_SPI_SHADER_PGM_RSRC1_ES;
1115   case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
1116   case CallingConv::AMDGPU_VS: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
1117   case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
1118   }
1119 }
1120 
1121 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
1122                                          const SIProgramInfo &CurrentProgramInfo) {
1123   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1124   unsigned RsrcReg = getRsrcReg(MF.getFunction().getCallingConv());
1125 
1126   if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
1127     OutStreamer->emitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
1128 
1129     OutStreamer->emitIntValue(CurrentProgramInfo.ComputePGMRSrc1, 4);
1130 
1131     OutStreamer->emitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
1132     OutStreamer->emitIntValue(CurrentProgramInfo.ComputePGMRSrc2, 4);
1133 
1134     OutStreamer->emitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
1135     OutStreamer->emitIntValue(S_00B860_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
1136 
1137     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
1138     // 0" comment but I don't see a corresponding field in the register spec.
1139   } else {
1140     OutStreamer->emitIntValue(RsrcReg, 4);
1141     OutStreamer->emitIntValue(S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
1142                               S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks), 4);
1143     OutStreamer->emitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
1144     OutStreamer->emitIntValue(
1145         S_0286E8_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
1146   }
1147 
1148   if (MF.getFunction().getCallingConv() == CallingConv::AMDGPU_PS) {
1149     OutStreamer->emitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
1150     OutStreamer->emitIntValue(S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks), 4);
1151     OutStreamer->emitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
1152     OutStreamer->emitIntValue(MFI->getPSInputEnable(), 4);
1153     OutStreamer->emitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
1154     OutStreamer->emitIntValue(MFI->getPSInputAddr(), 4);
1155   }
1156 
1157   OutStreamer->emitIntValue(R_SPILLED_SGPRS, 4);
1158   OutStreamer->emitIntValue(MFI->getNumSpilledSGPRs(), 4);
1159   OutStreamer->emitIntValue(R_SPILLED_VGPRS, 4);
1160   OutStreamer->emitIntValue(MFI->getNumSpilledVGPRs(), 4);
1161 }
1162 
1163 // This is the equivalent of EmitProgramInfoSI above, but for when the OS type
1164 // is AMDPAL.  It stores each compute/SPI register setting and other PAL
1165 // metadata items into the PALMD::Metadata, combining with any provided by the
1166 // frontend as LLVM metadata. Once all functions are written, the PAL metadata
1167 // is then written as a single block in the .note section.
1168 void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
1169        const SIProgramInfo &CurrentProgramInfo) {
1170   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1171   auto CC = MF.getFunction().getCallingConv();
1172   auto MD = getTargetStreamer()->getPALMetadata();
1173 
1174   MD->setEntryPoint(CC, MF.getFunction().getName());
1175   MD->setNumUsedVgprs(CC, CurrentProgramInfo.NumVGPRsForWavesPerEU);
1176   MD->setNumUsedSgprs(CC, CurrentProgramInfo.NumSGPRsForWavesPerEU);
1177   if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
1178     MD->setRsrc1(CC, CurrentProgramInfo.ComputePGMRSrc1);
1179     MD->setRsrc2(CC, CurrentProgramInfo.ComputePGMRSrc2);
1180   } else {
1181     MD->setRsrc1(CC, S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
1182         S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks));
1183     if (CurrentProgramInfo.ScratchBlocks > 0)
1184       MD->setRsrc2(CC, S_00B84C_SCRATCH_EN(1));
1185   }
1186   // ScratchSize is in bytes, 16 aligned.
1187   MD->setScratchSize(CC, alignTo(CurrentProgramInfo.ScratchSize, 16));
1188   if (MF.getFunction().getCallingConv() == CallingConv::AMDGPU_PS) {
1189     MD->setRsrc2(CC, S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks));
1190     MD->setSpiPsInputEna(MFI->getPSInputEnable());
1191     MD->setSpiPsInputAddr(MFI->getPSInputAddr());
1192   }
1193 
1194   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
1195   if (STM.isWave32())
1196     MD->setWave32(MF.getFunction().getCallingConv());
1197 }
1198 
1199 // This is supposed to be log2(Size)
1200 static amd_element_byte_size_t getElementByteSizeValue(unsigned Size) {
1201   switch (Size) {
1202   case 4:
1203     return AMD_ELEMENT_4_BYTES;
1204   case 8:
1205     return AMD_ELEMENT_8_BYTES;
1206   case 16:
1207     return AMD_ELEMENT_16_BYTES;
1208   default:
1209     llvm_unreachable("invalid private_element_size");
1210   }
1211 }
1212 
1213 void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out,
1214                                         const SIProgramInfo &CurrentProgramInfo,
1215                                         const MachineFunction &MF) const {
1216   const Function &F = MF.getFunction();
1217   assert(F.getCallingConv() == CallingConv::AMDGPU_KERNEL ||
1218          F.getCallingConv() == CallingConv::SPIR_KERNEL);
1219 
1220   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1221   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
1222 
1223   AMDGPU::initDefaultAMDKernelCodeT(Out, &STM);
1224 
1225   Out.compute_pgm_resource_registers =
1226       CurrentProgramInfo.ComputePGMRSrc1 |
1227       (CurrentProgramInfo.ComputePGMRSrc2 << 32);
1228   Out.code_properties |= AMD_CODE_PROPERTY_IS_PTR64;
1229 
1230   if (CurrentProgramInfo.DynamicCallStack)
1231     Out.code_properties |= AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK;
1232 
1233   AMD_HSA_BITS_SET(Out.code_properties,
1234                    AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE,
1235                    getElementByteSizeValue(STM.getMaxPrivateElementSize()));
1236 
1237   if (MFI->hasPrivateSegmentBuffer()) {
1238     Out.code_properties |=
1239       AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
1240   }
1241 
1242   if (MFI->hasDispatchPtr())
1243     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
1244 
1245   if (MFI->hasQueuePtr())
1246     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
1247 
1248   if (MFI->hasKernargSegmentPtr())
1249     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
1250 
1251   if (MFI->hasDispatchID())
1252     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
1253 
1254   if (MFI->hasFlatScratchInit())
1255     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
1256 
1257   if (MFI->hasDispatchPtr())
1258     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
1259 
1260   if (STM.isXNACKEnabled())
1261     Out.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED;
1262 
1263   Align MaxKernArgAlign;
1264   Out.kernarg_segment_byte_size = STM.getKernArgSegmentSize(F, MaxKernArgAlign);
1265   Out.wavefront_sgpr_count = CurrentProgramInfo.NumSGPR;
1266   Out.workitem_vgpr_count = CurrentProgramInfo.NumVGPR;
1267   Out.workitem_private_segment_byte_size = CurrentProgramInfo.ScratchSize;
1268   Out.workgroup_group_segment_byte_size = CurrentProgramInfo.LDSSize;
1269 
1270   // kernarg_segment_alignment is specified as log of the alignment.
1271   // The minimum alignment is 16.
1272   Out.kernarg_segment_alignment = Log2(std::max(Align(16), MaxKernArgAlign));
1273 }
1274 
1275 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
1276                                        const char *ExtraCode, raw_ostream &O) {
1277   // First try the generic code, which knows about modifiers like 'c' and 'n'.
1278   if (!AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, O))
1279     return false;
1280 
1281   if (ExtraCode && ExtraCode[0]) {
1282     if (ExtraCode[1] != 0)
1283       return true; // Unknown modifier.
1284 
1285     switch (ExtraCode[0]) {
1286     case 'r':
1287       break;
1288     default:
1289       return true;
1290     }
1291   }
1292 
1293   // TODO: Should be able to support other operand types like globals.
1294   const MachineOperand &MO = MI->getOperand(OpNo);
1295   if (MO.isReg()) {
1296     AMDGPUInstPrinter::printRegOperand(MO.getReg(), O,
1297                                        *MF->getSubtarget().getRegisterInfo());
1298     return false;
1299   }
1300 
1301   return true;
1302 }
1303