1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
15 //
16 //===----------------------------------------------------------------------===//
17 //
18 
19 #include "AMDGPUAsmPrinter.h"
20 #include "AMDGPU.h"
21 #include "AMDGPUSubtarget.h"
22 #include "AMDGPUTargetMachine.h"
23 #include "InstPrinter/AMDGPUInstPrinter.h"
24 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
25 #include "R600Defines.h"
26 #include "R600MachineFunctionInfo.h"
27 #include "R600RegisterInfo.h"
28 #include "SIDefines.h"
29 #include "SIInstrInfo.h"
30 #include "SIMachineFunctionInfo.h"
31 #include "SIRegisterInfo.h"
32 #include "Utils/AMDGPUBaseInfo.h"
33 #include "llvm/BinaryFormat/ELF.h"
34 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/IR/DiagnosticInfo.h"
36 #include "llvm/MC/MCContext.h"
37 #include "llvm/MC/MCSectionELF.h"
38 #include "llvm/MC/MCStreamer.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Target/TargetLoweringObjectFile.h"
42 
43 using namespace llvm;
44 
45 // TODO: This should get the default rounding mode from the kernel. We just set
46 // the default here, but this could change if the OpenCL rounding mode pragmas
47 // are used.
48 //
49 // The denormal mode here should match what is reported by the OpenCL runtime
50 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
51 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
52 //
53 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
54 // precision, and leaves single precision to flush all and does not report
55 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
56 // CL_FP_DENORM for both.
57 //
58 // FIXME: It seems some instructions do not support single precision denormals
59 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
60 // and sin_f32, cos_f32 on most parts).
61 
62 // We want to use these instructions, and using fp32 denormals also causes
63 // instructions to run at the double precision rate for the device so it's
64 // probably best to just report no single precision denormals.
65 static uint32_t getFPMode(const MachineFunction &F) {
66   const SISubtarget& ST = F.getSubtarget<SISubtarget>();
67   // TODO: Is there any real use for the flush in only / flush out only modes?
68 
69   uint32_t FP32Denormals =
70     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
71 
72   uint32_t FP64Denormals =
73     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
74 
75   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
76          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
77          FP_DENORM_MODE_SP(FP32Denormals) |
78          FP_DENORM_MODE_DP(FP64Denormals);
79 }
80 
81 static AsmPrinter *
82 createAMDGPUAsmPrinterPass(TargetMachine &tm,
83                            std::unique_ptr<MCStreamer> &&Streamer) {
84   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
85 }
86 
87 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
88   TargetRegistry::RegisterAsmPrinter(getTheAMDGPUTarget(),
89                                      createAMDGPUAsmPrinterPass);
90   TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(),
91                                      createAMDGPUAsmPrinterPass);
92 }
93 
94 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
95                                    std::unique_ptr<MCStreamer> Streamer)
96   : AsmPrinter(TM, std::move(Streamer)) {
97     AMDGPUASI = static_cast<AMDGPUTargetMachine*>(&TM)->getAMDGPUAS();
98   }
99 
100 StringRef AMDGPUAsmPrinter::getPassName() const {
101   return "AMDGPU Assembly Printer";
102 }
103 
104 const MCSubtargetInfo* AMDGPUAsmPrinter::getSTI() const {
105   return TM.getMCSubtargetInfo();
106 }
107 
108 AMDGPUTargetStreamer& AMDGPUAsmPrinter::getTargetStreamer() const {
109   return static_cast<AMDGPUTargetStreamer&>(*OutStreamer->getTargetStreamer());
110 }
111 
112 void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) {
113   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
114     return;
115 
116   AMDGPU::IsaInfo::IsaVersion ISA =
117       AMDGPU::IsaInfo::getIsaVersion(getSTI()->getFeatureBits());
118 
119   getTargetStreamer().EmitDirectiveHSACodeObjectVersion(2, 1);
120   getTargetStreamer().EmitDirectiveHSACodeObjectISA(
121       ISA.Major, ISA.Minor, ISA.Stepping, "AMD", "AMDGPU");
122   getTargetStreamer().EmitStartOfCodeObjectMetadata(M);
123 }
124 
125 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
126   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
127     return;
128 
129   getTargetStreamer().EmitEndOfCodeObjectMetadata();
130 }
131 
132 bool AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough(
133   const MachineBasicBlock *MBB) const {
134   if (!AsmPrinter::isBlockOnlyReachableByFallthrough(MBB))
135     return false;
136 
137   if (MBB->empty())
138     return true;
139 
140   // If this is a block implementing a long branch, an expression relative to
141   // the start of the block is needed.  to the start of the block.
142   // XXX - Is there a smarter way to check this?
143   return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
144 }
145 
146 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
147   const AMDGPUMachineFunction *MFI = MF->getInfo<AMDGPUMachineFunction>();
148   if (!MFI->isEntryFunction())
149     return;
150 
151   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
152   amd_kernel_code_t KernelCode;
153   if (STM.isAmdCodeObjectV2(*MF)) {
154     getAmdKernelCode(KernelCode, CurrentProgramInfo, *MF);
155 
156     OutStreamer->SwitchSection(getObjFileLowering().getTextSection());
157     getTargetStreamer().EmitAMDKernelCodeT(KernelCode);
158   }
159 
160   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
161     return;
162   getTargetStreamer().EmitKernelCodeObjectMetadata(*MF->getFunction(),
163                                                    KernelCode);
164 }
165 
166 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
167   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
168   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
169   if (MFI->isEntryFunction() && STM.isAmdCodeObjectV2(*MF)) {
170     SmallString<128> SymbolName;
171     getNameWithPrefix(SymbolName, MF->getFunction()),
172     getTargetStreamer().EmitAMDGPUSymbolType(
173         SymbolName, ELF::STT_AMDGPU_HSA_KERNEL);
174   }
175 
176   AsmPrinter::EmitFunctionEntryLabel();
177 }
178 
179 void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
180 
181   // Group segment variables aren't emitted in HSA.
182   if (AMDGPU::isGroupSegment(GV, AMDGPUASI))
183     return;
184 
185   AsmPrinter::EmitGlobalVariable(GV);
186 }
187 
188 bool AMDGPUAsmPrinter::doFinalization(Module &M) {
189   CallGraphResourceInfo.clear();
190   return AsmPrinter::doFinalization(M);
191 }
192 
193 // Print comments that apply to both callable functions and entry points.
194 void AMDGPUAsmPrinter::emitCommonFunctionComments(
195   uint32_t NumVGPR,
196   uint32_t NumSGPR,
197   uint32_t ScratchSize,
198   uint64_t CodeSize) {
199   OutStreamer->emitRawComment(" codeLenInByte = " + Twine(CodeSize), false);
200   OutStreamer->emitRawComment(" NumSgprs: " + Twine(NumSGPR), false);
201   OutStreamer->emitRawComment(" NumVgprs: " + Twine(NumVGPR), false);
202   OutStreamer->emitRawComment(" ScratchSize: " + Twine(ScratchSize), false);
203 }
204 
205 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
206   CurrentProgramInfo = SIProgramInfo();
207 
208   const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
209 
210   // The starting address of all shader programs must be 256 bytes aligned.
211   // Regular functions just need the basic required instruction alignment.
212   MF.setAlignment(MFI->isEntryFunction() ? 8 : 2);
213 
214   SetupMachineFunction(MF);
215 
216   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
217   MCContext &Context = getObjFileLowering().getContext();
218   if (!STM.isAmdHsaOS()) {
219     MCSectionELF *ConfigSection =
220         Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
221     OutStreamer->SwitchSection(ConfigSection);
222   }
223 
224   if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
225     if (MFI->isEntryFunction()) {
226       getSIProgramInfo(CurrentProgramInfo, MF);
227     } else {
228       auto I = CallGraphResourceInfo.insert(
229         std::make_pair(MF.getFunction(), SIFunctionResourceInfo()));
230       SIFunctionResourceInfo &Info = I.first->second;
231       assert(I.second && "should only be called once per function");
232       Info = analyzeResourceUsage(MF);
233     }
234 
235     if (!STM.isAmdHsaOS()) {
236       EmitProgramInfoSI(MF, CurrentProgramInfo);
237     }
238   } else {
239     EmitProgramInfoR600(MF);
240   }
241 
242   DisasmLines.clear();
243   HexLines.clear();
244   DisasmLineMaxLen = 0;
245 
246   EmitFunctionBody();
247 
248   if (isVerbose()) {
249     MCSectionELF *CommentSection =
250         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
251     OutStreamer->SwitchSection(CommentSection);
252 
253     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
254       if (!MFI->isEntryFunction()) {
255         OutStreamer->emitRawComment(" Function info:", false);
256         SIFunctionResourceInfo &Info = CallGraphResourceInfo[MF.getFunction()];
257         emitCommonFunctionComments(
258           Info.NumVGPR,
259           Info.getTotalNumSGPRs(MF.getSubtarget<SISubtarget>()),
260           Info.PrivateSegmentSize,
261           getFunctionCodeSize(MF));
262         return false;
263       }
264 
265       OutStreamer->emitRawComment(" Kernel info:", false);
266       emitCommonFunctionComments(CurrentProgramInfo.NumVGPR,
267                                  CurrentProgramInfo.NumSGPR,
268                                  CurrentProgramInfo.ScratchSize,
269                                  getFunctionCodeSize(MF));
270 
271       OutStreamer->emitRawComment(
272         " FloatMode: " + Twine(CurrentProgramInfo.FloatMode), false);
273       OutStreamer->emitRawComment(
274         " IeeeMode: " + Twine(CurrentProgramInfo.IEEEMode), false);
275       OutStreamer->emitRawComment(
276         " LDSByteSize: " + Twine(CurrentProgramInfo.LDSSize) +
277         " bytes/workgroup (compile time only)", false);
278 
279       OutStreamer->emitRawComment(
280         " SGPRBlocks: " + Twine(CurrentProgramInfo.SGPRBlocks), false);
281       OutStreamer->emitRawComment(
282         " VGPRBlocks: " + Twine(CurrentProgramInfo.VGPRBlocks), false);
283 
284       OutStreamer->emitRawComment(
285         " NumSGPRsForWavesPerEU: " +
286         Twine(CurrentProgramInfo.NumSGPRsForWavesPerEU), false);
287       OutStreamer->emitRawComment(
288         " NumVGPRsForWavesPerEU: " +
289         Twine(CurrentProgramInfo.NumVGPRsForWavesPerEU), false);
290 
291       OutStreamer->emitRawComment(
292         " ReservedVGPRFirst: " + Twine(CurrentProgramInfo.ReservedVGPRFirst),
293         false);
294       OutStreamer->emitRawComment(
295         " ReservedVGPRCount: " + Twine(CurrentProgramInfo.ReservedVGPRCount),
296         false);
297 
298       if (MF.getSubtarget<SISubtarget>().debuggerEmitPrologue()) {
299         OutStreamer->emitRawComment(
300           " DebuggerWavefrontPrivateSegmentOffsetSGPR: s" +
301           Twine(CurrentProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR), false);
302         OutStreamer->emitRawComment(
303           " DebuggerPrivateSegmentBufferSGPR: s" +
304           Twine(CurrentProgramInfo.DebuggerPrivateSegmentBufferSGPR), false);
305       }
306 
307       OutStreamer->emitRawComment(
308         " COMPUTE_PGM_RSRC2:USER_SGPR: " +
309         Twine(G_00B84C_USER_SGPR(CurrentProgramInfo.ComputePGMRSrc2)), false);
310       OutStreamer->emitRawComment(
311         " COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
312         Twine(G_00B84C_TRAP_HANDLER(CurrentProgramInfo.ComputePGMRSrc2)), false);
313       OutStreamer->emitRawComment(
314         " COMPUTE_PGM_RSRC2:TGID_X_EN: " +
315         Twine(G_00B84C_TGID_X_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
316       OutStreamer->emitRawComment(
317         " COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
318         Twine(G_00B84C_TGID_Y_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
319       OutStreamer->emitRawComment(
320         " COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
321         Twine(G_00B84C_TGID_Z_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
322       OutStreamer->emitRawComment(
323         " COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
324         Twine(G_00B84C_TIDIG_COMP_CNT(CurrentProgramInfo.ComputePGMRSrc2)),
325         false);
326     } else {
327       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
328       OutStreamer->emitRawComment(
329         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->CFStackSize)));
330     }
331   }
332 
333   if (STM.dumpCode()) {
334 
335     OutStreamer->SwitchSection(
336         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
337 
338     for (size_t i = 0; i < DisasmLines.size(); ++i) {
339       std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
340       Comment += " ; " + HexLines[i] + "\n";
341 
342       OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
343       OutStreamer->EmitBytes(StringRef(Comment));
344     }
345   }
346 
347   return false;
348 }
349 
350 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
351   unsigned MaxGPR = 0;
352   bool killPixel = false;
353   const R600Subtarget &STM = MF.getSubtarget<R600Subtarget>();
354   const R600RegisterInfo *RI = STM.getRegisterInfo();
355   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
356 
357   for (const MachineBasicBlock &MBB : MF) {
358     for (const MachineInstr &MI : MBB) {
359       if (MI.getOpcode() == AMDGPU::KILLGT)
360         killPixel = true;
361       unsigned numOperands = MI.getNumOperands();
362       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
363         const MachineOperand &MO = MI.getOperand(op_idx);
364         if (!MO.isReg())
365           continue;
366         unsigned HWReg = RI->getHWRegIndex(MO.getReg());
367 
368         // Register with value > 127 aren't GPR
369         if (HWReg > 127)
370           continue;
371         MaxGPR = std::max(MaxGPR, HWReg);
372       }
373     }
374   }
375 
376   unsigned RsrcReg;
377   if (STM.getGeneration() >= R600Subtarget::EVERGREEN) {
378     // Evergreen / Northern Islands
379     switch (MF.getFunction()->getCallingConv()) {
380     default: LLVM_FALLTHROUGH;
381     case CallingConv::AMDGPU_CS: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
382     case CallingConv::AMDGPU_GS: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
383     case CallingConv::AMDGPU_PS: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
384     case CallingConv::AMDGPU_VS: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
385     }
386   } else {
387     // R600 / R700
388     switch (MF.getFunction()->getCallingConv()) {
389     default: LLVM_FALLTHROUGH;
390     case CallingConv::AMDGPU_GS: LLVM_FALLTHROUGH;
391     case CallingConv::AMDGPU_CS: LLVM_FALLTHROUGH;
392     case CallingConv::AMDGPU_VS: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
393     case CallingConv::AMDGPU_PS: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
394     }
395   }
396 
397   OutStreamer->EmitIntValue(RsrcReg, 4);
398   OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
399                            S_STACK_SIZE(MFI->CFStackSize), 4);
400   OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
401   OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
402 
403   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
404     OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
405     OutStreamer->EmitIntValue(alignTo(MFI->getLDSSize(), 4) >> 2, 4);
406   }
407 }
408 
409 uint64_t AMDGPUAsmPrinter::getFunctionCodeSize(const MachineFunction &MF) const {
410   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
411   const SIInstrInfo *TII = STM.getInstrInfo();
412 
413   uint64_t CodeSize = 0;
414 
415   for (const MachineBasicBlock &MBB : MF) {
416     for (const MachineInstr &MI : MBB) {
417       // TODO: CodeSize should account for multiple functions.
418 
419       // TODO: Should we count size of debug info?
420       if (MI.isDebugValue())
421         continue;
422 
423       CodeSize += TII->getInstSizeInBytes(MI);
424     }
425   }
426 
427   return CodeSize;
428 }
429 
430 static bool hasAnyNonFlatUseOfReg(const MachineRegisterInfo &MRI,
431                                   const SIInstrInfo &TII,
432                                   unsigned Reg) {
433   for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) {
434     if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent()))
435       return true;
436   }
437 
438   return false;
439 }
440 
441 static unsigned getNumExtraSGPRs(const SISubtarget &ST,
442                                  bool VCCUsed,
443                                  bool FlatScrUsed) {
444   unsigned ExtraSGPRs = 0;
445   if (VCCUsed)
446     ExtraSGPRs = 2;
447 
448   if (ST.getGeneration() < SISubtarget::VOLCANIC_ISLANDS) {
449     if (FlatScrUsed)
450       ExtraSGPRs = 4;
451   } else {
452     if (ST.isXNACKEnabled())
453       ExtraSGPRs = 4;
454 
455     if (FlatScrUsed)
456       ExtraSGPRs = 6;
457   }
458 
459   return ExtraSGPRs;
460 }
461 
462 int32_t AMDGPUAsmPrinter::SIFunctionResourceInfo::getTotalNumSGPRs(
463   const SISubtarget &ST) const {
464   return NumExplicitSGPR + getNumExtraSGPRs(ST, UsesVCC, UsesFlatScratch);
465 }
466 
467 AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
468   const MachineFunction &MF) const {
469   SIFunctionResourceInfo Info;
470 
471   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
472   const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
473   const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
474   const MachineRegisterInfo &MRI = MF.getRegInfo();
475   const SIInstrInfo *TII = ST.getInstrInfo();
476   const SIRegisterInfo &TRI = TII->getRegisterInfo();
477 
478   Info.UsesFlatScratch = MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_LO) ||
479                          MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_HI);
480 
481   // Even if FLAT_SCRATCH is implicitly used, it has no effect if flat
482   // instructions aren't used to access the scratch buffer. Inline assembly may
483   // need it though.
484   //
485   // If we only have implicit uses of flat_scr on flat instructions, it is not
486   // really needed.
487   if (Info.UsesFlatScratch && !MFI->hasFlatScratchInit() &&
488       (!hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR) &&
489        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_LO) &&
490        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_HI))) {
491     Info.UsesFlatScratch = false;
492   }
493 
494   Info.HasDynamicallySizedStack = FrameInfo.hasVarSizedObjects();
495   Info.PrivateSegmentSize = FrameInfo.getStackSize();
496 
497 
498   Info.UsesVCC = MRI.isPhysRegUsed(AMDGPU::VCC_LO) ||
499                  MRI.isPhysRegUsed(AMDGPU::VCC_HI);
500 
501   // If there are no calls, MachineRegisterInfo can tell us the used register
502   // count easily.
503   if (!FrameInfo.hasCalls()) {
504     MCPhysReg HighestVGPRReg = AMDGPU::NoRegister;
505     for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) {
506       if (MRI.isPhysRegUsed(Reg)) {
507         HighestVGPRReg = Reg;
508         break;
509       }
510     }
511 
512     MCPhysReg HighestSGPRReg = AMDGPU::NoRegister;
513     for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) {
514       if (MRI.isPhysRegUsed(Reg)) {
515         HighestSGPRReg = Reg;
516         break;
517       }
518     }
519 
520     // We found the maximum register index. They start at 0, so add one to get the
521     // number of registers.
522     Info.NumVGPR = HighestVGPRReg == AMDGPU::NoRegister ? 0 :
523       TRI.getHWRegIndex(HighestVGPRReg) + 1;
524     Info.NumExplicitSGPR = HighestSGPRReg == AMDGPU::NoRegister ? 0 :
525       TRI.getHWRegIndex(HighestSGPRReg) + 1;
526 
527     return Info;
528   }
529 
530   int32_t MaxVGPR = -1;
531   int32_t MaxSGPR = -1;
532   uint32_t CalleeFrameSize = 0;
533 
534   for (const MachineBasicBlock &MBB : MF) {
535     for (const MachineInstr &MI : MBB) {
536       // TODO: Check regmasks? Do they occur anywhere except calls?
537       for (const MachineOperand &MO : MI.operands()) {
538         unsigned Width = 0;
539         bool IsSGPR = false;
540 
541         if (!MO.isReg())
542           continue;
543 
544         unsigned Reg = MO.getReg();
545         switch (Reg) {
546         case AMDGPU::EXEC:
547         case AMDGPU::EXEC_LO:
548         case AMDGPU::EXEC_HI:
549         case AMDGPU::SCC:
550         case AMDGPU::M0:
551         case AMDGPU::SRC_SHARED_BASE:
552         case AMDGPU::SRC_SHARED_LIMIT:
553         case AMDGPU::SRC_PRIVATE_BASE:
554         case AMDGPU::SRC_PRIVATE_LIMIT:
555           continue;
556 
557         case AMDGPU::NoRegister:
558           assert(MI.isDebugValue());
559           continue;
560 
561         case AMDGPU::VCC:
562         case AMDGPU::VCC_LO:
563         case AMDGPU::VCC_HI:
564           Info.UsesVCC = true;
565           continue;
566 
567         case AMDGPU::FLAT_SCR:
568         case AMDGPU::FLAT_SCR_LO:
569         case AMDGPU::FLAT_SCR_HI:
570           continue;
571 
572         case AMDGPU::TBA:
573         case AMDGPU::TBA_LO:
574         case AMDGPU::TBA_HI:
575         case AMDGPU::TMA:
576         case AMDGPU::TMA_LO:
577         case AMDGPU::TMA_HI:
578           llvm_unreachable("trap handler registers should not be used");
579 
580         default:
581           break;
582         }
583 
584         if (AMDGPU::SReg_32RegClass.contains(Reg)) {
585           assert(!AMDGPU::TTMP_32RegClass.contains(Reg) &&
586                  "trap handler registers should not be used");
587           IsSGPR = true;
588           Width = 1;
589         } else if (AMDGPU::VGPR_32RegClass.contains(Reg)) {
590           IsSGPR = false;
591           Width = 1;
592         } else if (AMDGPU::SReg_64RegClass.contains(Reg)) {
593           assert(!AMDGPU::TTMP_64RegClass.contains(Reg) &&
594                  "trap handler registers should not be used");
595           IsSGPR = true;
596           Width = 2;
597         } else if (AMDGPU::VReg_64RegClass.contains(Reg)) {
598           IsSGPR = false;
599           Width = 2;
600         } else if (AMDGPU::VReg_96RegClass.contains(Reg)) {
601           IsSGPR = false;
602           Width = 3;
603         } else if (AMDGPU::SReg_128RegClass.contains(Reg)) {
604           IsSGPR = true;
605           Width = 4;
606         } else if (AMDGPU::VReg_128RegClass.contains(Reg)) {
607           IsSGPR = false;
608           Width = 4;
609         } else if (AMDGPU::SReg_256RegClass.contains(Reg)) {
610           IsSGPR = true;
611           Width = 8;
612         } else if (AMDGPU::VReg_256RegClass.contains(Reg)) {
613           IsSGPR = false;
614           Width = 8;
615         } else if (AMDGPU::SReg_512RegClass.contains(Reg)) {
616           IsSGPR = true;
617           Width = 16;
618         } else if (AMDGPU::VReg_512RegClass.contains(Reg)) {
619           IsSGPR = false;
620           Width = 16;
621         } else {
622           llvm_unreachable("Unknown register class");
623         }
624         unsigned HWReg = TRI.getHWRegIndex(Reg);
625         int MaxUsed = HWReg + Width - 1;
626         if (IsSGPR) {
627           MaxSGPR = MaxUsed > MaxSGPR ? MaxUsed : MaxSGPR;
628         } else {
629           MaxVGPR = MaxUsed > MaxVGPR ? MaxUsed : MaxVGPR;
630         }
631       }
632 
633       if (MI.isCall()) {
634         // Pseudo used just to encode the underlying global. Is there a better
635         // way to track this?
636 
637         const MachineOperand *CalleeOp
638           = TII->getNamedOperand(MI, AMDGPU::OpName::callee);
639         const Function *Callee = cast<Function>(CalleeOp->getGlobal());
640         if (Callee->isDeclaration()) {
641           // If this is a call to an external function, we can't do much. Make
642           // conservative guesses.
643 
644           // 48 SGPRs - vcc, - flat_scr, -xnack
645           int MaxSGPRGuess = 47 - getNumExtraSGPRs(ST, true,
646                                                    ST.hasFlatAddressSpace());
647           MaxSGPR = std::max(MaxSGPR, MaxSGPRGuess);
648           MaxVGPR = std::max(MaxVGPR, 23);
649 
650           CalleeFrameSize = std::max(CalleeFrameSize, 16384u);
651           Info.UsesVCC = true;
652           Info.UsesFlatScratch = ST.hasFlatAddressSpace();
653           Info.HasDynamicallySizedStack = true;
654         } else {
655           // We force CodeGen to run in SCC order, so the callee's register
656           // usage etc. should be the cumulative usage of all callees.
657           auto I = CallGraphResourceInfo.find(Callee);
658           assert(I != CallGraphResourceInfo.end() &&
659                  "callee should have been handled before caller");
660 
661           MaxSGPR = std::max(I->second.NumExplicitSGPR - 1, MaxSGPR);
662           MaxVGPR = std::max(I->second.NumVGPR - 1, MaxVGPR);
663           CalleeFrameSize
664             = std::max(I->second.PrivateSegmentSize, CalleeFrameSize);
665           Info.UsesVCC |= I->second.UsesVCC;
666           Info.UsesFlatScratch |= I->second.UsesFlatScratch;
667           Info.HasDynamicallySizedStack |= I->second.HasDynamicallySizedStack;
668           Info.HasRecursion |= I->second.HasRecursion;
669         }
670 
671         if (!Callee->doesNotRecurse())
672           Info.HasRecursion = true;
673       }
674     }
675   }
676 
677   Info.NumExplicitSGPR = MaxSGPR + 1;
678   Info.NumVGPR = MaxVGPR + 1;
679   Info.PrivateSegmentSize += CalleeFrameSize;
680 
681   return Info;
682 }
683 
684 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
685                                         const MachineFunction &MF) {
686   SIFunctionResourceInfo Info = analyzeResourceUsage(MF);
687 
688   ProgInfo.NumVGPR = Info.NumVGPR;
689   ProgInfo.NumSGPR = Info.NumExplicitSGPR;
690   ProgInfo.ScratchSize = Info.PrivateSegmentSize;
691   ProgInfo.VCCUsed = Info.UsesVCC;
692   ProgInfo.FlatUsed = Info.UsesFlatScratch;
693   ProgInfo.DynamicCallStack = Info.HasDynamicallySizedStack || Info.HasRecursion;
694 
695   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
696   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
697   const SIInstrInfo *TII = STM.getInstrInfo();
698   const SIRegisterInfo *RI = &TII->getRegisterInfo();
699 
700   unsigned ExtraSGPRs = getNumExtraSGPRs(STM,
701                                          ProgInfo.VCCUsed,
702                                          ProgInfo.FlatUsed);
703   unsigned ExtraVGPRs = STM.getReservedNumVGPRs(MF);
704 
705   // Check the addressable register limit before we add ExtraSGPRs.
706   if (STM.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
707       !STM.hasSGPRInitBug()) {
708     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
709     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
710       // This can happen due to a compiler bug or when using inline asm.
711       LLVMContext &Ctx = MF.getFunction()->getContext();
712       DiagnosticInfoResourceLimit Diag(*MF.getFunction(),
713                                        "addressable scalar registers",
714                                        ProgInfo.NumSGPR, DS_Error,
715                                        DK_ResourceLimit,
716                                        MaxAddressableNumSGPRs);
717       Ctx.diagnose(Diag);
718       ProgInfo.NumSGPR = MaxAddressableNumSGPRs - 1;
719     }
720   }
721 
722   // Account for extra SGPRs and VGPRs reserved for debugger use.
723   ProgInfo.NumSGPR += ExtraSGPRs;
724   ProgInfo.NumVGPR += ExtraVGPRs;
725 
726   // Adjust number of registers used to meet default/requested minimum/maximum
727   // number of waves per execution unit request.
728   ProgInfo.NumSGPRsForWavesPerEU = std::max(
729     std::max(ProgInfo.NumSGPR, 1u), STM.getMinNumSGPRs(MFI->getMaxWavesPerEU()));
730   ProgInfo.NumVGPRsForWavesPerEU = std::max(
731     std::max(ProgInfo.NumVGPR, 1u), STM.getMinNumVGPRs(MFI->getMaxWavesPerEU()));
732 
733   if (STM.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ||
734       STM.hasSGPRInitBug()) {
735     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
736     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
737       // This can happen due to a compiler bug or when using inline asm to use
738       // the registers which are usually reserved for vcc etc.
739       LLVMContext &Ctx = MF.getFunction()->getContext();
740       DiagnosticInfoResourceLimit Diag(*MF.getFunction(),
741                                        "scalar registers",
742                                        ProgInfo.NumSGPR, DS_Error,
743                                        DK_ResourceLimit,
744                                        MaxAddressableNumSGPRs);
745       Ctx.diagnose(Diag);
746       ProgInfo.NumSGPR = MaxAddressableNumSGPRs;
747       ProgInfo.NumSGPRsForWavesPerEU = MaxAddressableNumSGPRs;
748     }
749   }
750 
751   if (STM.hasSGPRInitBug()) {
752     ProgInfo.NumSGPR =
753         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
754     ProgInfo.NumSGPRsForWavesPerEU =
755         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
756   }
757 
758   if (MFI->getNumUserSGPRs() > STM.getMaxNumUserSGPRs()) {
759     LLVMContext &Ctx = MF.getFunction()->getContext();
760     DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "user SGPRs",
761                                      MFI->getNumUserSGPRs(), DS_Error);
762     Ctx.diagnose(Diag);
763   }
764 
765   if (MFI->getLDSSize() > static_cast<unsigned>(STM.getLocalMemorySize())) {
766     LLVMContext &Ctx = MF.getFunction()->getContext();
767     DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "local memory",
768                                      MFI->getLDSSize(), DS_Error);
769     Ctx.diagnose(Diag);
770   }
771 
772   // SGPRBlocks is actual number of SGPR blocks minus 1.
773   ProgInfo.SGPRBlocks = alignTo(ProgInfo.NumSGPRsForWavesPerEU,
774                                 STM.getSGPREncodingGranule());
775   ProgInfo.SGPRBlocks = ProgInfo.SGPRBlocks / STM.getSGPREncodingGranule() - 1;
776 
777   // VGPRBlocks is actual number of VGPR blocks minus 1.
778   ProgInfo.VGPRBlocks = alignTo(ProgInfo.NumVGPRsForWavesPerEU,
779                                 STM.getVGPREncodingGranule());
780   ProgInfo.VGPRBlocks = ProgInfo.VGPRBlocks / STM.getVGPREncodingGranule() - 1;
781 
782   // Record first reserved VGPR and number of reserved VGPRs.
783   ProgInfo.ReservedVGPRFirst = STM.debuggerReserveRegs() ? ProgInfo.NumVGPR : 0;
784   ProgInfo.ReservedVGPRCount = STM.getReservedNumVGPRs(MF);
785 
786   // Update DebuggerWavefrontPrivateSegmentOffsetSGPR and
787   // DebuggerPrivateSegmentBufferSGPR fields if "amdgpu-debugger-emit-prologue"
788   // attribute was requested.
789   if (STM.debuggerEmitPrologue()) {
790     ProgInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR =
791       RI->getHWRegIndex(MFI->getScratchWaveOffsetReg());
792     ProgInfo.DebuggerPrivateSegmentBufferSGPR =
793       RI->getHWRegIndex(MFI->getScratchRSrcReg());
794   }
795 
796   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
797   // register.
798   ProgInfo.FloatMode = getFPMode(MF);
799 
800   ProgInfo.IEEEMode = STM.enableIEEEBit(MF);
801 
802   // Make clamp modifier on NaN input returns 0.
803   ProgInfo.DX10Clamp = STM.enableDX10Clamp();
804 
805   unsigned LDSAlignShift;
806   if (STM.getGeneration() < SISubtarget::SEA_ISLANDS) {
807     // LDS is allocated in 64 dword blocks.
808     LDSAlignShift = 8;
809   } else {
810     // LDS is allocated in 128 dword blocks.
811     LDSAlignShift = 9;
812   }
813 
814   unsigned LDSSpillSize =
815     MFI->getLDSWaveSpillSize() * MFI->getMaxFlatWorkGroupSize();
816 
817   ProgInfo.LDSSize = MFI->getLDSSize() + LDSSpillSize;
818   ProgInfo.LDSBlocks =
819       alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
820 
821   // Scratch is allocated in 256 dword blocks.
822   unsigned ScratchAlignShift = 10;
823   // We need to program the hardware with the amount of scratch memory that
824   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
825   // scratch memory used per thread.
826   ProgInfo.ScratchBlocks =
827       alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
828               1ULL << ScratchAlignShift) >>
829       ScratchAlignShift;
830 
831   ProgInfo.ComputePGMRSrc1 =
832       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
833       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
834       S_00B848_PRIORITY(ProgInfo.Priority) |
835       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
836       S_00B848_PRIV(ProgInfo.Priv) |
837       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
838       S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
839       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
840 
841   // 0 = X, 1 = XY, 2 = XYZ
842   unsigned TIDIGCompCnt = 0;
843   if (MFI->hasWorkItemIDZ())
844     TIDIGCompCnt = 2;
845   else if (MFI->hasWorkItemIDY())
846     TIDIGCompCnt = 1;
847 
848   ProgInfo.ComputePGMRSrc2 =
849       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
850       S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
851       S_00B84C_TRAP_HANDLER(STM.isTrapHandlerEnabled()) |
852       S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
853       S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
854       S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
855       S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
856       S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
857       S_00B84C_EXCP_EN_MSB(0) |
858       // For AMDHSA, LDS_SIZE must be zero, as it is populated by the CP.
859       S_00B84C_LDS_SIZE(STM.isAmdHsaOS() ? 0 : ProgInfo.LDSBlocks) |
860       S_00B84C_EXCP_EN(0);
861 }
862 
863 static unsigned getRsrcReg(CallingConv::ID CallConv) {
864   switch (CallConv) {
865   default: LLVM_FALLTHROUGH;
866   case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
867   case CallingConv::AMDGPU_HS: return R_00B428_SPI_SHADER_PGM_RSRC1_HS;
868   case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
869   case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
870   case CallingConv::AMDGPU_VS: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
871   }
872 }
873 
874 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
875                                          const SIProgramInfo &CurrentProgramInfo) {
876   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
877   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
878   unsigned RsrcReg = getRsrcReg(MF.getFunction()->getCallingConv());
879 
880   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
881     OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
882 
883     OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc1, 4);
884 
885     OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
886     OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc2, 4);
887 
888     OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
889     OutStreamer->EmitIntValue(S_00B860_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
890 
891     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
892     // 0" comment but I don't see a corresponding field in the register spec.
893   } else {
894     OutStreamer->EmitIntValue(RsrcReg, 4);
895     OutStreamer->EmitIntValue(S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
896                               S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks), 4);
897     if (STM.isVGPRSpillingEnabled(*MF.getFunction())) {
898       OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
899       OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
900     }
901   }
902 
903   if (MF.getFunction()->getCallingConv() == CallingConv::AMDGPU_PS) {
904     OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
905     OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks), 4);
906     OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
907     OutStreamer->EmitIntValue(MFI->getPSInputEnable(), 4);
908     OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
909     OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4);
910   }
911 
912   OutStreamer->EmitIntValue(R_SPILLED_SGPRS, 4);
913   OutStreamer->EmitIntValue(MFI->getNumSpilledSGPRs(), 4);
914   OutStreamer->EmitIntValue(R_SPILLED_VGPRS, 4);
915   OutStreamer->EmitIntValue(MFI->getNumSpilledVGPRs(), 4);
916 }
917 
918 // This is supposed to be log2(Size)
919 static amd_element_byte_size_t getElementByteSizeValue(unsigned Size) {
920   switch (Size) {
921   case 4:
922     return AMD_ELEMENT_4_BYTES;
923   case 8:
924     return AMD_ELEMENT_8_BYTES;
925   case 16:
926     return AMD_ELEMENT_16_BYTES;
927   default:
928     llvm_unreachable("invalid private_element_size");
929   }
930 }
931 
932 void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out,
933                                         const SIProgramInfo &CurrentProgramInfo,
934                                         const MachineFunction &MF) const {
935   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
936   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
937 
938   AMDGPU::initDefaultAMDKernelCodeT(Out, STM.getFeatureBits());
939 
940   Out.compute_pgm_resource_registers =
941       CurrentProgramInfo.ComputePGMRSrc1 |
942       (CurrentProgramInfo.ComputePGMRSrc2 << 32);
943   Out.code_properties = AMD_CODE_PROPERTY_IS_PTR64;
944 
945   if (CurrentProgramInfo.DynamicCallStack)
946     Out.code_properties |= AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK;
947 
948   AMD_HSA_BITS_SET(Out.code_properties,
949                    AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE,
950                    getElementByteSizeValue(STM.getMaxPrivateElementSize()));
951 
952   if (MFI->hasPrivateSegmentBuffer()) {
953     Out.code_properties |=
954       AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
955   }
956 
957   if (MFI->hasDispatchPtr())
958     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
959 
960   if (MFI->hasQueuePtr())
961     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
962 
963   if (MFI->hasKernargSegmentPtr())
964     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
965 
966   if (MFI->hasDispatchID())
967     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
968 
969   if (MFI->hasFlatScratchInit())
970     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
971 
972   if (MFI->hasGridWorkgroupCountX()) {
973     Out.code_properties |=
974       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X;
975   }
976 
977   if (MFI->hasGridWorkgroupCountY()) {
978     Out.code_properties |=
979       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y;
980   }
981 
982   if (MFI->hasGridWorkgroupCountZ()) {
983     Out.code_properties |=
984       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z;
985   }
986 
987   if (MFI->hasDispatchPtr())
988     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
989 
990   if (STM.debuggerSupported())
991     Out.code_properties |= AMD_CODE_PROPERTY_IS_DEBUG_SUPPORTED;
992 
993   if (STM.isXNACKEnabled())
994     Out.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED;
995 
996   // FIXME: Should use getKernArgSize
997   Out.kernarg_segment_byte_size =
998     STM.getKernArgSegmentSize(MF, MFI->getABIArgOffset());
999   Out.wavefront_sgpr_count = CurrentProgramInfo.NumSGPR;
1000   Out.workitem_vgpr_count = CurrentProgramInfo.NumVGPR;
1001   Out.workitem_private_segment_byte_size = CurrentProgramInfo.ScratchSize;
1002   Out.workgroup_group_segment_byte_size = CurrentProgramInfo.LDSSize;
1003   Out.reserved_vgpr_first = CurrentProgramInfo.ReservedVGPRFirst;
1004   Out.reserved_vgpr_count = CurrentProgramInfo.ReservedVGPRCount;
1005 
1006   // These alignment values are specified in powers of two, so alignment =
1007   // 2^n.  The minimum alignment is 2^4 = 16.
1008   Out.kernarg_segment_alignment = std::max((size_t)4,
1009       countTrailingZeros(MFI->getMaxKernArgAlign()));
1010 
1011   if (STM.debuggerEmitPrologue()) {
1012     Out.debug_wavefront_private_segment_offset_sgpr =
1013       CurrentProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR;
1014     Out.debug_private_segment_buffer_sgpr =
1015       CurrentProgramInfo.DebuggerPrivateSegmentBufferSGPR;
1016   }
1017 }
1018 
1019 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
1020                                        unsigned AsmVariant,
1021                                        const char *ExtraCode, raw_ostream &O) {
1022   // First try the generic code, which knows about modifiers like 'c' and 'n'.
1023   if (!AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O))
1024     return false;
1025 
1026   if (ExtraCode && ExtraCode[0]) {
1027     if (ExtraCode[1] != 0)
1028       return true; // Unknown modifier.
1029 
1030     switch (ExtraCode[0]) {
1031     case 'r':
1032       break;
1033     default:
1034       return true;
1035     }
1036   }
1037 
1038   // TODO: Should be able to support other operand types like globals.
1039   const MachineOperand &MO = MI->getOperand(OpNo);
1040   if (MO.isReg()) {
1041     AMDGPUInstPrinter::printRegOperand(MO.getReg(), O,
1042                                        *MF->getSubtarget().getRegisterInfo());
1043     return false;
1044   }
1045 
1046   return true;
1047 }
1048