1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
15 //
16 //===----------------------------------------------------------------------===//
17 //
18 
19 #include "AMDGPUAsmPrinter.h"
20 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
21 #include "InstPrinter/AMDGPUInstPrinter.h"
22 #include "Utils/AMDGPUBaseInfo.h"
23 #include "AMDGPU.h"
24 #include "AMDKernelCodeT.h"
25 #include "AMDGPUSubtarget.h"
26 #include "R600Defines.h"
27 #include "R600MachineFunctionInfo.h"
28 #include "R600RegisterInfo.h"
29 #include "SIDefines.h"
30 #include "SIMachineFunctionInfo.h"
31 #include "SIRegisterInfo.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/MC/MCContext.h"
34 #include "llvm/MC/MCSectionELF.h"
35 #include "llvm/MC/MCStreamer.h"
36 #include "llvm/Support/ELF.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/TargetRegistry.h"
39 #include "llvm/Target/TargetLoweringObjectFile.h"
40 
41 using namespace llvm;
42 
43 // TODO: This should get the default rounding mode from the kernel. We just set
44 // the default here, but this could change if the OpenCL rounding mode pragmas
45 // are used.
46 //
47 // The denormal mode here should match what is reported by the OpenCL runtime
48 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
49 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
50 //
51 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
52 // precision, and leaves single precision to flush all and does not report
53 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
54 // CL_FP_DENORM for both.
55 //
56 // FIXME: It seems some instructions do not support single precision denormals
57 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
58 // and sin_f32, cos_f32 on most parts).
59 
60 // We want to use these instructions, and using fp32 denormals also causes
61 // instructions to run at the double precision rate for the device so it's
62 // probably best to just report no single precision denormals.
63 static uint32_t getFPMode(const MachineFunction &F) {
64   const AMDGPUSubtarget& ST = F.getSubtarget<AMDGPUSubtarget>();
65   // TODO: Is there any real use for the flush in only / flush out only modes?
66 
67   uint32_t FP32Denormals =
68     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
69 
70   uint32_t FP64Denormals =
71     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
72 
73   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
74          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
75          FP_DENORM_MODE_SP(FP32Denormals) |
76          FP_DENORM_MODE_DP(FP64Denormals);
77 }
78 
79 static AsmPrinter *
80 createAMDGPUAsmPrinterPass(TargetMachine &tm,
81                            std::unique_ptr<MCStreamer> &&Streamer) {
82   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
83 }
84 
85 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
86   TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
87   TargetRegistry::RegisterAsmPrinter(TheGCNTarget, createAMDGPUAsmPrinterPass);
88 }
89 
90 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
91                                    std::unique_ptr<MCStreamer> Streamer)
92     : AsmPrinter(TM, std::move(Streamer)) {}
93 
94 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
95   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
96   SIProgramInfo KernelInfo;
97   if (STM.isAmdHsaOS()) {
98     getSIProgramInfo(KernelInfo, *MF);
99     EmitAmdKernelCodeT(*MF, KernelInfo);
100   }
101 }
102 
103 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
104 
105   // This label is used to mark the end of the .text section.
106   const TargetLoweringObjectFile &TLOF = getObjFileLowering();
107   OutStreamer->SwitchSection(TLOF.getTextSection());
108   MCSymbol *EndOfTextLabel =
109       OutContext.getOrCreateSymbol(StringRef(END_OF_TEXT_LABEL_NAME));
110   OutStreamer->EmitLabel(EndOfTextLabel);
111 }
112 
113 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
114 
115   // The starting address of all shader programs must be 256 bytes aligned.
116   MF.setAlignment(8);
117 
118   SetupMachineFunction(MF);
119 
120   MCContext &Context = getObjFileLowering().getContext();
121   MCSectionELF *ConfigSection =
122       Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
123   OutStreamer->SwitchSection(ConfigSection);
124 
125   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
126   SIProgramInfo KernelInfo;
127   if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
128     getSIProgramInfo(KernelInfo, MF);
129     if (!STM.isAmdHsaOS()) {
130       EmitProgramInfoSI(MF, KernelInfo);
131     }
132     // Emit directives
133     AMDGPUTargetStreamer *TS =
134         static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
135     TS->EmitDirectiveHSACodeObjectVersion(1, 0);
136     AMDGPU::IsaVersion ISA = STM.getIsaVersion();
137     TS->EmitDirectiveHSACodeObjectISA(ISA.Major, ISA.Minor, ISA.Stepping,
138                                       "AMD", "AMDGPU");
139   } else {
140     EmitProgramInfoR600(MF);
141   }
142 
143   DisasmLines.clear();
144   HexLines.clear();
145   DisasmLineMaxLen = 0;
146 
147   EmitFunctionBody();
148 
149   if (isVerbose()) {
150     MCSectionELF *CommentSection =
151         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
152     OutStreamer->SwitchSection(CommentSection);
153 
154     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
155       OutStreamer->emitRawComment(" Kernel info:", false);
156       OutStreamer->emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
157                                   false);
158       OutStreamer->emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
159                                   false);
160       OutStreamer->emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
161                                   false);
162       OutStreamer->emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
163                                   false);
164       OutStreamer->emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
165                                   false);
166       OutStreamer->emitRawComment(" ScratchSize: " + Twine(KernelInfo.ScratchSize),
167                                   false);
168     } else {
169       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
170       OutStreamer->emitRawComment(
171         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
172     }
173   }
174 
175   if (STM.dumpCode()) {
176 
177     OutStreamer->SwitchSection(
178         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
179 
180     for (size_t i = 0; i < DisasmLines.size(); ++i) {
181       std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
182       Comment += " ; " + HexLines[i] + "\n";
183 
184       OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
185       OutStreamer->EmitBytes(StringRef(Comment));
186     }
187   }
188 
189   return false;
190 }
191 
192 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
193   unsigned MaxGPR = 0;
194   bool killPixel = false;
195   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
196   const R600RegisterInfo *RI =
197       static_cast<const R600RegisterInfo *>(STM.getRegisterInfo());
198   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
199 
200   for (const MachineBasicBlock &MBB : MF) {
201     for (const MachineInstr &MI : MBB) {
202       if (MI.getOpcode() == AMDGPU::KILLGT)
203         killPixel = true;
204       unsigned numOperands = MI.getNumOperands();
205       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
206         const MachineOperand &MO = MI.getOperand(op_idx);
207         if (!MO.isReg())
208           continue;
209         unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
210 
211         // Register with value > 127 aren't GPR
212         if (HWReg > 127)
213           continue;
214         MaxGPR = std::max(MaxGPR, HWReg);
215       }
216     }
217   }
218 
219   unsigned RsrcReg;
220   if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
221     // Evergreen / Northern Islands
222     switch (MFI->getShaderType()) {
223     default: // Fall through
224     case ShaderType::COMPUTE:  RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
225     case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
226     case ShaderType::PIXEL:    RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
227     case ShaderType::VERTEX:   RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
228     }
229   } else {
230     // R600 / R700
231     switch (MFI->getShaderType()) {
232     default: // Fall through
233     case ShaderType::GEOMETRY: // Fall through
234     case ShaderType::COMPUTE:  // Fall through
235     case ShaderType::VERTEX:   RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
236     case ShaderType::PIXEL:    RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
237     }
238   }
239 
240   OutStreamer->EmitIntValue(RsrcReg, 4);
241   OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
242                            S_STACK_SIZE(MFI->StackSize), 4);
243   OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
244   OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
245 
246   if (MFI->getShaderType() == ShaderType::COMPUTE) {
247     OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
248     OutStreamer->EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
249   }
250 }
251 
252 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
253                                         const MachineFunction &MF) const {
254   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
255   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
256   uint64_t CodeSize = 0;
257   unsigned MaxSGPR = 0;
258   unsigned MaxVGPR = 0;
259   bool VCCUsed = false;
260   bool FlatUsed = false;
261   const SIRegisterInfo *RI =
262       static_cast<const SIRegisterInfo *>(STM.getRegisterInfo());
263 
264   for (const MachineBasicBlock &MBB : MF) {
265     for (const MachineInstr &MI : MBB) {
266       // TODO: CodeSize should account for multiple functions.
267 
268       // TODO: Should we count size of debug info?
269       if (MI.isDebugValue())
270         continue;
271 
272       // FIXME: This is reporting 0 for many instructions.
273       CodeSize += MI.getDesc().Size;
274 
275       unsigned numOperands = MI.getNumOperands();
276       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
277         const MachineOperand &MO = MI.getOperand(op_idx);
278         unsigned width = 0;
279         bool isSGPR = false;
280 
281         if (!MO.isReg()) {
282           continue;
283         }
284         unsigned reg = MO.getReg();
285         if (reg == AMDGPU::VCC || reg == AMDGPU::VCC_LO ||
286             reg == AMDGPU::VCC_HI) {
287           VCCUsed = true;
288           continue;
289         } else if (reg == AMDGPU::FLAT_SCR ||
290                    reg == AMDGPU::FLAT_SCR_LO ||
291                    reg == AMDGPU::FLAT_SCR_HI) {
292           FlatUsed = true;
293           continue;
294         }
295 
296         switch (reg) {
297         default: break;
298         case AMDGPU::SCC:
299         case AMDGPU::EXEC:
300         case AMDGPU::M0:
301           continue;
302         }
303 
304         if (AMDGPU::SReg_32RegClass.contains(reg)) {
305           isSGPR = true;
306           width = 1;
307         } else if (AMDGPU::VGPR_32RegClass.contains(reg)) {
308           isSGPR = false;
309           width = 1;
310         } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
311           isSGPR = true;
312           width = 2;
313         } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
314           isSGPR = false;
315           width = 2;
316         } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
317           isSGPR = false;
318           width = 3;
319         } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
320           isSGPR = true;
321           width = 4;
322         } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
323           isSGPR = false;
324           width = 4;
325         } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
326           isSGPR = true;
327           width = 8;
328         } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
329           isSGPR = false;
330           width = 8;
331         } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
332           isSGPR = true;
333           width = 16;
334         } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
335           isSGPR = false;
336           width = 16;
337         } else {
338           llvm_unreachable("Unknown register class");
339         }
340         unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
341         unsigned maxUsed = hwReg + width - 1;
342         if (isSGPR) {
343           MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
344         } else {
345           MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
346         }
347       }
348     }
349   }
350 
351   if (VCCUsed)
352     MaxSGPR += 2;
353 
354   if (FlatUsed)
355     MaxSGPR += 2;
356 
357   // We found the maximum register index. They start at 0, so add one to get the
358   // number of registers.
359   ProgInfo.NumVGPR = MaxVGPR + 1;
360   ProgInfo.NumSGPR = MaxSGPR + 1;
361 
362   if (STM.hasSGPRInitBug()) {
363     if (ProgInfo.NumSGPR > AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG) {
364       LLVMContext &Ctx = MF.getFunction()->getContext();
365       Ctx.emitError("too many SGPRs used with the SGPR init bug");
366     }
367 
368     ProgInfo.NumSGPR = AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG;
369   }
370 
371   ProgInfo.VGPRBlocks = (ProgInfo.NumVGPR - 1) / 4;
372   ProgInfo.SGPRBlocks = (ProgInfo.NumSGPR - 1) / 8;
373   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
374   // register.
375   ProgInfo.FloatMode = getFPMode(MF);
376 
377   // XXX: Not quite sure what this does, but sc seems to unset this.
378   ProgInfo.IEEEMode = 0;
379 
380   // Do not clamp NAN to 0.
381   ProgInfo.DX10Clamp = 0;
382 
383   const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
384   ProgInfo.ScratchSize = FrameInfo->estimateStackSize(MF);
385 
386   ProgInfo.FlatUsed = FlatUsed;
387   ProgInfo.VCCUsed = VCCUsed;
388   ProgInfo.CodeLen = CodeSize;
389 
390   unsigned LDSAlignShift;
391   if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
392     // LDS is allocated in 64 dword blocks.
393     LDSAlignShift = 8;
394   } else {
395     // LDS is allocated in 128 dword blocks.
396     LDSAlignShift = 9;
397   }
398 
399   unsigned LDSSpillSize = MFI->LDSWaveSpillSize *
400                           MFI->getMaximumWorkGroupSize(MF);
401 
402   ProgInfo.LDSSize = MFI->LDSSize + LDSSpillSize;
403   ProgInfo.LDSBlocks =
404      RoundUpToAlignment(ProgInfo.LDSSize, 1 << LDSAlignShift) >> LDSAlignShift;
405 
406   // Scratch is allocated in 256 dword blocks.
407   unsigned ScratchAlignShift = 10;
408   // We need to program the hardware with the amount of scratch memory that
409   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
410   // scratch memory used per thread.
411   ProgInfo.ScratchBlocks =
412     RoundUpToAlignment(ProgInfo.ScratchSize * STM.getWavefrontSize(),
413                        1 << ScratchAlignShift) >> ScratchAlignShift;
414 
415   ProgInfo.ComputePGMRSrc1 =
416       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
417       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
418       S_00B848_PRIORITY(ProgInfo.Priority) |
419       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
420       S_00B848_PRIV(ProgInfo.Priv) |
421       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
422       S_00B848_IEEE_MODE(ProgInfo.DebugMode) |
423       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
424 
425   ProgInfo.ComputePGMRSrc2 =
426       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
427       S_00B84C_USER_SGPR(MFI->NumUserSGPRs) |
428       S_00B84C_TGID_X_EN(1) |
429       S_00B84C_TGID_Y_EN(1) |
430       S_00B84C_TGID_Z_EN(1) |
431       S_00B84C_TG_SIZE_EN(1) |
432       S_00B84C_TIDIG_COMP_CNT(2) |
433       S_00B84C_LDS_SIZE(ProgInfo.LDSBlocks);
434 }
435 
436 static unsigned getRsrcReg(unsigned ShaderType) {
437   switch (ShaderType) {
438   default: // Fall through
439   case ShaderType::COMPUTE:  return R_00B848_COMPUTE_PGM_RSRC1;
440   case ShaderType::GEOMETRY: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
441   case ShaderType::PIXEL:    return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
442   case ShaderType::VERTEX:   return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
443   }
444 }
445 
446 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
447                                          const SIProgramInfo &KernelInfo) {
448   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
449   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
450   unsigned RsrcReg = getRsrcReg(MFI->getShaderType());
451 
452   if (MFI->getShaderType() == ShaderType::COMPUTE) {
453     OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
454 
455     OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc1, 4);
456 
457     OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
458     OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc2, 4);
459 
460     OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
461     OutStreamer->EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4);
462 
463     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
464     // 0" comment but I don't see a corresponding field in the register spec.
465   } else {
466     OutStreamer->EmitIntValue(RsrcReg, 4);
467     OutStreamer->EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
468                               S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4);
469     if (STM.isVGPRSpillingEnabled(MFI)) {
470       OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
471       OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(KernelInfo.ScratchBlocks), 4);
472     }
473   }
474 
475   if (MFI->getShaderType() == ShaderType::PIXEL) {
476     OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
477     OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4);
478     OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
479     OutStreamer->EmitIntValue(MFI->PSInputAddr, 4);
480   }
481 }
482 
483 void AMDGPUAsmPrinter::EmitAmdKernelCodeT(const MachineFunction &MF,
484                                          const SIProgramInfo &KernelInfo) const {
485   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
486   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
487   amd_kernel_code_t header;
488 
489   AMDGPU::initDefaultAMDKernelCodeT(header, STM.getFeatureBits());
490 
491   header.compute_pgm_resource_registers =
492       KernelInfo.ComputePGMRSrc1 |
493       (KernelInfo.ComputePGMRSrc2 << 32);
494   header.code_properties =
495       AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR |
496       AMD_CODE_PROPERTY_IS_PTR64;
497 
498   header.kernarg_segment_byte_size = MFI->ABIArgOffset;
499   header.wavefront_sgpr_count = KernelInfo.NumSGPR;
500   header.workitem_vgpr_count = KernelInfo.NumVGPR;
501 
502   AMDGPUTargetStreamer *TS =
503       static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
504   TS->EmitAMDKernelCodeT(header);
505 }
506 
507 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
508                                        unsigned AsmVariant,
509                                        const char *ExtraCode, raw_ostream &O) {
510   if (ExtraCode && ExtraCode[0]) {
511     if (ExtraCode[1] != 0)
512       return true; // Unknown modifier.
513 
514     switch (ExtraCode[0]) {
515     default:
516       // See if this is a generic print operand
517       return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
518     case 'r':
519       break;
520     }
521   }
522 
523   AMDGPUInstPrinter::printRegOperand(MI->getOperand(OpNo).getReg(), O,
524                    *TM.getSubtargetImpl(*MF->getFunction())->getRegisterInfo());
525   return false;
526 }
527