1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
15 //
16 //===----------------------------------------------------------------------===//
17 //
18 
19 #include "AMDGPUAsmPrinter.h"
20 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
21 #include "InstPrinter/AMDGPUInstPrinter.h"
22 #include "Utils/AMDGPUBaseInfo.h"
23 #include "AMDGPU.h"
24 #include "AMDKernelCodeT.h"
25 #include "AMDGPUSubtarget.h"
26 #include "R600Defines.h"
27 #include "R600MachineFunctionInfo.h"
28 #include "R600RegisterInfo.h"
29 #include "SIDefines.h"
30 #include "SIMachineFunctionInfo.h"
31 #include "SIRegisterInfo.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/MC/MCContext.h"
34 #include "llvm/MC/MCSectionELF.h"
35 #include "llvm/MC/MCStreamer.h"
36 #include "llvm/Support/ELF.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/TargetRegistry.h"
39 #include "llvm/Target/TargetLoweringObjectFile.h"
40 
41 using namespace llvm;
42 
43 // TODO: This should get the default rounding mode from the kernel. We just set
44 // the default here, but this could change if the OpenCL rounding mode pragmas
45 // are used.
46 //
47 // The denormal mode here should match what is reported by the OpenCL runtime
48 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
49 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
50 //
51 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
52 // precision, and leaves single precision to flush all and does not report
53 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
54 // CL_FP_DENORM for both.
55 //
56 // FIXME: It seems some instructions do not support single precision denormals
57 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
58 // and sin_f32, cos_f32 on most parts).
59 
60 // We want to use these instructions, and using fp32 denormals also causes
61 // instructions to run at the double precision rate for the device so it's
62 // probably best to just report no single precision denormals.
63 static uint32_t getFPMode(const MachineFunction &F) {
64   const AMDGPUSubtarget& ST = F.getSubtarget<AMDGPUSubtarget>();
65   // TODO: Is there any real use for the flush in only / flush out only modes?
66 
67   uint32_t FP32Denormals =
68     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
69 
70   uint32_t FP64Denormals =
71     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
72 
73   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
74          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
75          FP_DENORM_MODE_SP(FP32Denormals) |
76          FP_DENORM_MODE_DP(FP64Denormals);
77 }
78 
79 static AsmPrinter *
80 createAMDGPUAsmPrinterPass(TargetMachine &tm,
81                            std::unique_ptr<MCStreamer> &&Streamer) {
82   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
83 }
84 
85 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
86   TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
87   TargetRegistry::RegisterAsmPrinter(TheGCNTarget, createAMDGPUAsmPrinterPass);
88 }
89 
90 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
91                                    std::unique_ptr<MCStreamer> Streamer)
92     : AsmPrinter(TM, std::move(Streamer)) {}
93 
94 void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) {
95   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
96     return;
97 
98   // Need to construct an MCSubtargetInfo here in case we have no functions
99   // in the module.
100   std::unique_ptr<MCSubtargetInfo> STI(TM.getTarget().createMCSubtargetInfo(
101         TM.getTargetTriple().str(), TM.getTargetCPU(),
102         TM.getTargetFeatureString()));
103 
104   AMDGPUTargetStreamer *TS =
105       static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
106 
107   TS->EmitDirectiveHSACodeObjectVersion(1, 0);
108   AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI->getFeatureBits());
109   TS->EmitDirectiveHSACodeObjectISA(ISA.Major, ISA.Minor, ISA.Stepping,
110                                     "AMD", "AMDGPU");
111 }
112 
113 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
114   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
115   SIProgramInfo KernelInfo;
116   if (STM.isAmdHsaOS()) {
117     getSIProgramInfo(KernelInfo, *MF);
118     EmitAmdKernelCodeT(*MF, KernelInfo);
119   }
120 }
121 
122 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
123   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
124   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
125   if (MFI->isKernel() && STM.isAmdHsaOS()) {
126     AMDGPUTargetStreamer *TS =
127         static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
128     TS->EmitAMDGPUSymbolType(CurrentFnSym->getName(),
129                              ELF::STT_AMDGPU_HSA_KERNEL);
130   }
131 
132   AsmPrinter::EmitFunctionEntryLabel();
133 }
134 
135 static bool isModuleLinkage(const GlobalValue *GV) {
136   switch (GV->getLinkage()) {
137   case GlobalValue::LinkOnceODRLinkage:
138   case GlobalValue::LinkOnceAnyLinkage:
139   case GlobalValue::InternalLinkage:
140   case GlobalValue::CommonLinkage:
141    return true;
142   case GlobalValue::ExternalLinkage:
143    return false;
144   default: llvm_unreachable("unknown linkage type");
145   }
146 }
147 
148 void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
149 
150   if (TM.getTargetTriple().getOS() != Triple::AMDHSA) {
151     AsmPrinter::EmitGlobalVariable(GV);
152     return;
153   }
154 
155   if (GV->isDeclaration() || GV->getLinkage() == GlobalValue::PrivateLinkage) {
156     AsmPrinter::EmitGlobalVariable(GV);
157     return;
158   }
159 
160   // Group segment variables aren't emitted in HSA.
161   if (AMDGPU::isGroupSegment(GV))
162     return;
163 
164   AMDGPUTargetStreamer *TS =
165       static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
166   if (isModuleLinkage(GV)) {
167     TS->EmitAMDGPUHsaModuleScopeGlobal(GV->getName());
168   } else {
169     TS->EmitAMDGPUHsaProgramScopeGlobal(GV->getName());
170   }
171 
172   MCSymbolELF *GVSym = cast<MCSymbolELF>(getSymbol(GV));
173   const DataLayout &DL = getDataLayout();
174 
175   // Emit the size
176   uint64_t Size = DL.getTypeAllocSize(GV->getType()->getElementType());
177   OutStreamer->emitELFSize(GVSym, MCConstantExpr::create(Size, OutContext));
178   OutStreamer->PushSection();
179   OutStreamer->SwitchSection(
180       getObjFileLowering().SectionForGlobal(GV, *Mang, TM));
181   const Constant *C = GV->getInitializer();
182   OutStreamer->EmitLabel(GVSym);
183   EmitGlobalConstant(DL, C);
184   OutStreamer->PopSection();
185 }
186 
187 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
188 
189   // The starting address of all shader programs must be 256 bytes aligned.
190   MF.setAlignment(8);
191 
192   SetupMachineFunction(MF);
193 
194   MCContext &Context = getObjFileLowering().getContext();
195   MCSectionELF *ConfigSection =
196       Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
197   OutStreamer->SwitchSection(ConfigSection);
198 
199   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
200   SIProgramInfo KernelInfo;
201   if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
202     getSIProgramInfo(KernelInfo, MF);
203     if (!STM.isAmdHsaOS()) {
204       EmitProgramInfoSI(MF, KernelInfo);
205     }
206   } else {
207     EmitProgramInfoR600(MF);
208   }
209 
210   DisasmLines.clear();
211   HexLines.clear();
212   DisasmLineMaxLen = 0;
213 
214   EmitFunctionBody();
215 
216   if (isVerbose()) {
217     MCSectionELF *CommentSection =
218         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
219     OutStreamer->SwitchSection(CommentSection);
220 
221     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
222       OutStreamer->emitRawComment(" Kernel info:", false);
223       OutStreamer->emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
224                                   false);
225       OutStreamer->emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
226                                   false);
227       OutStreamer->emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
228                                   false);
229       OutStreamer->emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
230                                   false);
231       OutStreamer->emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
232                                   false);
233       OutStreamer->emitRawComment(" ScratchSize: " + Twine(KernelInfo.ScratchSize),
234                                   false);
235 
236       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:USER_SGPR: " +
237                                   Twine(G_00B84C_USER_SGPR(KernelInfo.ComputePGMRSrc2)),
238                                   false);
239       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_X_EN: " +
240                                   Twine(G_00B84C_TGID_X_EN(KernelInfo.ComputePGMRSrc2)),
241                                   false);
242       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
243                                   Twine(G_00B84C_TGID_Y_EN(KernelInfo.ComputePGMRSrc2)),
244                                   false);
245       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
246                                   Twine(G_00B84C_TGID_Z_EN(KernelInfo.ComputePGMRSrc2)),
247                                   false);
248       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
249                                   Twine(G_00B84C_TIDIG_COMP_CNT(KernelInfo.ComputePGMRSrc2)),
250                                   false);
251 
252     } else {
253       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
254       OutStreamer->emitRawComment(
255         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
256     }
257   }
258 
259   if (STM.dumpCode()) {
260 
261     OutStreamer->SwitchSection(
262         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
263 
264     for (size_t i = 0; i < DisasmLines.size(); ++i) {
265       std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
266       Comment += " ; " + HexLines[i] + "\n";
267 
268       OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
269       OutStreamer->EmitBytes(StringRef(Comment));
270     }
271   }
272 
273   return false;
274 }
275 
276 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
277   unsigned MaxGPR = 0;
278   bool killPixel = false;
279   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
280   const R600RegisterInfo *RI =
281       static_cast<const R600RegisterInfo *>(STM.getRegisterInfo());
282   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
283 
284   for (const MachineBasicBlock &MBB : MF) {
285     for (const MachineInstr &MI : MBB) {
286       if (MI.getOpcode() == AMDGPU::KILLGT)
287         killPixel = true;
288       unsigned numOperands = MI.getNumOperands();
289       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
290         const MachineOperand &MO = MI.getOperand(op_idx);
291         if (!MO.isReg())
292           continue;
293         unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
294 
295         // Register with value > 127 aren't GPR
296         if (HWReg > 127)
297           continue;
298         MaxGPR = std::max(MaxGPR, HWReg);
299       }
300     }
301   }
302 
303   unsigned RsrcReg;
304   if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
305     // Evergreen / Northern Islands
306     switch (MF.getFunction()->getCallingConv()) {
307     default: // Fall through
308     case CallingConv::AMDGPU_CS: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
309     case CallingConv::AMDGPU_GS: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
310     case CallingConv::AMDGPU_PS: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
311     case CallingConv::AMDGPU_VS: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
312     }
313   } else {
314     // R600 / R700
315     switch (MF.getFunction()->getCallingConv()) {
316     default: // Fall through
317     case CallingConv::AMDGPU_GS: // Fall through
318     case CallingConv::AMDGPU_CS: // Fall through
319     case CallingConv::AMDGPU_VS: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
320     case CallingConv::AMDGPU_PS: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
321     }
322   }
323 
324   OutStreamer->EmitIntValue(RsrcReg, 4);
325   OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
326                            S_STACK_SIZE(MFI->StackSize), 4);
327   OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
328   OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
329 
330   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
331     OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
332     OutStreamer->EmitIntValue(alignTo(MFI->LDSSize, 4) >> 2, 4);
333   }
334 }
335 
336 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
337                                         const MachineFunction &MF) const {
338   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
339   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
340   uint64_t CodeSize = 0;
341   unsigned MaxSGPR = 0;
342   unsigned MaxVGPR = 0;
343   bool VCCUsed = false;
344   bool FlatUsed = false;
345   const SIRegisterInfo *RI =
346       static_cast<const SIRegisterInfo *>(STM.getRegisterInfo());
347 
348   for (const MachineBasicBlock &MBB : MF) {
349     for (const MachineInstr &MI : MBB) {
350       // TODO: CodeSize should account for multiple functions.
351 
352       // TODO: Should we count size of debug info?
353       if (MI.isDebugValue())
354         continue;
355 
356       // FIXME: This is reporting 0 for many instructions.
357       CodeSize += MI.getDesc().Size;
358 
359       unsigned numOperands = MI.getNumOperands();
360       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
361         const MachineOperand &MO = MI.getOperand(op_idx);
362         unsigned width = 0;
363         bool isSGPR = false;
364 
365         if (!MO.isReg())
366           continue;
367 
368         unsigned reg = MO.getReg();
369         switch (reg) {
370         case AMDGPU::EXEC:
371         case AMDGPU::SCC:
372         case AMDGPU::M0:
373           continue;
374 
375         case AMDGPU::VCC:
376         case AMDGPU::VCC_LO:
377         case AMDGPU::VCC_HI:
378           VCCUsed = true;
379           continue;
380 
381         case AMDGPU::FLAT_SCR:
382         case AMDGPU::FLAT_SCR_LO:
383         case AMDGPU::FLAT_SCR_HI:
384           FlatUsed = true;
385           continue;
386 
387         default:
388           break;
389         }
390 
391         if (AMDGPU::SReg_32RegClass.contains(reg)) {
392           isSGPR = true;
393           width = 1;
394         } else if (AMDGPU::VGPR_32RegClass.contains(reg)) {
395           isSGPR = false;
396           width = 1;
397         } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
398           isSGPR = true;
399           width = 2;
400         } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
401           isSGPR = false;
402           width = 2;
403         } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
404           isSGPR = false;
405           width = 3;
406         } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
407           isSGPR = true;
408           width = 4;
409         } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
410           isSGPR = false;
411           width = 4;
412         } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
413           isSGPR = true;
414           width = 8;
415         } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
416           isSGPR = false;
417           width = 8;
418         } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
419           isSGPR = true;
420           width = 16;
421         } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
422           isSGPR = false;
423           width = 16;
424         } else {
425           llvm_unreachable("Unknown register class");
426         }
427         unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
428         unsigned maxUsed = hwReg + width - 1;
429         if (isSGPR) {
430           MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
431         } else {
432           MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
433         }
434       }
435     }
436   }
437 
438   unsigned ExtraSGPRs = 0;
439 
440   if (VCCUsed)
441     ExtraSGPRs = 2;
442 
443   if (STM.getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS) {
444     if (FlatUsed)
445       ExtraSGPRs = 4;
446   } else {
447     if (STM.isXNACKEnabled())
448       ExtraSGPRs = 4;
449 
450     if (FlatUsed)
451       ExtraSGPRs = 6;
452   }
453 
454   MaxSGPR += ExtraSGPRs;
455 
456   // We found the maximum register index. They start at 0, so add one to get the
457   // number of registers.
458   ProgInfo.NumVGPR = MaxVGPR + 1;
459   ProgInfo.NumSGPR = MaxSGPR + 1;
460 
461   if (STM.hasSGPRInitBug()) {
462     if (ProgInfo.NumSGPR > AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG) {
463       LLVMContext &Ctx = MF.getFunction()->getContext();
464       Ctx.emitError("too many SGPRs used with the SGPR init bug");
465     }
466 
467     ProgInfo.NumSGPR = AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG;
468   }
469 
470   if (MFI->NumUserSGPRs > STM.getMaxNumUserSGPRs()) {
471     LLVMContext &Ctx = MF.getFunction()->getContext();
472     Ctx.emitError("too many user SGPRs used");
473   }
474 
475   ProgInfo.VGPRBlocks = (ProgInfo.NumVGPR - 1) / 4;
476   ProgInfo.SGPRBlocks = (ProgInfo.NumSGPR - 1) / 8;
477   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
478   // register.
479   ProgInfo.FloatMode = getFPMode(MF);
480 
481   ProgInfo.IEEEMode = 0;
482 
483   // Make clamp modifier on NaN input returns 0.
484   ProgInfo.DX10Clamp = 1;
485 
486   const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
487   ProgInfo.ScratchSize = FrameInfo->getStackSize();
488 
489   ProgInfo.FlatUsed = FlatUsed;
490   ProgInfo.VCCUsed = VCCUsed;
491   ProgInfo.CodeLen = CodeSize;
492 
493   unsigned LDSAlignShift;
494   if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
495     // LDS is allocated in 64 dword blocks.
496     LDSAlignShift = 8;
497   } else {
498     // LDS is allocated in 128 dword blocks.
499     LDSAlignShift = 9;
500   }
501 
502   unsigned LDSSpillSize = MFI->LDSWaveSpillSize *
503                           MFI->getMaximumWorkGroupSize(MF);
504 
505   ProgInfo.LDSSize = MFI->LDSSize + LDSSpillSize;
506   ProgInfo.LDSBlocks =
507       alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
508 
509   // Scratch is allocated in 256 dword blocks.
510   unsigned ScratchAlignShift = 10;
511   // We need to program the hardware with the amount of scratch memory that
512   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
513   // scratch memory used per thread.
514   ProgInfo.ScratchBlocks =
515       alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
516               1ULL << ScratchAlignShift) >>
517       ScratchAlignShift;
518 
519   ProgInfo.ComputePGMRSrc1 =
520       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
521       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
522       S_00B848_PRIORITY(ProgInfo.Priority) |
523       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
524       S_00B848_PRIV(ProgInfo.Priv) |
525       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
526       S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
527       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
528 
529   // 0 = X, 1 = XY, 2 = XYZ
530   unsigned TIDIGCompCnt = 0;
531   if (MFI->hasWorkItemIDZ())
532     TIDIGCompCnt = 2;
533   else if (MFI->hasWorkItemIDY())
534     TIDIGCompCnt = 1;
535 
536   ProgInfo.ComputePGMRSrc2 =
537       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
538       S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
539       S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
540       S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
541       S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
542       S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
543       S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
544       S_00B84C_EXCP_EN_MSB(0) |
545       S_00B84C_LDS_SIZE(ProgInfo.LDSBlocks) |
546       S_00B84C_EXCP_EN(0);
547 }
548 
549 static unsigned getRsrcReg(CallingConv::ID CallConv) {
550   switch (CallConv) {
551   default: // Fall through
552   case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
553   case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
554   case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
555   case CallingConv::AMDGPU_VS: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
556   }
557 }
558 
559 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
560                                          const SIProgramInfo &KernelInfo) {
561   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
562   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
563   unsigned RsrcReg = getRsrcReg(MF.getFunction()->getCallingConv());
564 
565   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
566     OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
567 
568     OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc1, 4);
569 
570     OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
571     OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc2, 4);
572 
573     OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
574     OutStreamer->EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4);
575 
576     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
577     // 0" comment but I don't see a corresponding field in the register spec.
578   } else {
579     OutStreamer->EmitIntValue(RsrcReg, 4);
580     OutStreamer->EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
581                               S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4);
582     if (STM.isVGPRSpillingEnabled(*MF.getFunction())) {
583       OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
584       OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(KernelInfo.ScratchBlocks), 4);
585     }
586   }
587 
588   if (MF.getFunction()->getCallingConv() == CallingConv::AMDGPU_PS) {
589     OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
590     OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4);
591     OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
592     OutStreamer->EmitIntValue(MFI->PSInputEna, 4);
593     OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
594     OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4);
595   }
596 }
597 
598 // This is supposed to be log2(Size)
599 static amd_element_byte_size_t getElementByteSizeValue(unsigned Size) {
600   switch (Size) {
601   case 4:
602     return AMD_ELEMENT_4_BYTES;
603   case 8:
604     return AMD_ELEMENT_8_BYTES;
605   case 16:
606     return AMD_ELEMENT_16_BYTES;
607   default:
608     llvm_unreachable("invalid private_element_size");
609   }
610 }
611 
612 void AMDGPUAsmPrinter::EmitAmdKernelCodeT(const MachineFunction &MF,
613                                          const SIProgramInfo &KernelInfo) const {
614   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
615   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
616   amd_kernel_code_t header;
617 
618   AMDGPU::initDefaultAMDKernelCodeT(header, STM.getFeatureBits());
619 
620   header.compute_pgm_resource_registers =
621       KernelInfo.ComputePGMRSrc1 |
622       (KernelInfo.ComputePGMRSrc2 << 32);
623   header.code_properties = AMD_CODE_PROPERTY_IS_PTR64;
624 
625 
626   AMD_HSA_BITS_SET(header.code_properties,
627                    AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE,
628                    getElementByteSizeValue(STM.getMaxPrivateElementSize()));
629 
630   if (MFI->hasPrivateSegmentBuffer()) {
631     header.code_properties |=
632       AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
633   }
634 
635   if (MFI->hasDispatchPtr())
636     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
637 
638   if (MFI->hasQueuePtr())
639     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
640 
641   if (MFI->hasKernargSegmentPtr())
642     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
643 
644   if (MFI->hasDispatchID())
645     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
646 
647   if (MFI->hasFlatScratchInit())
648     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
649 
650   // TODO: Private segment size
651 
652   if (MFI->hasGridWorkgroupCountX()) {
653     header.code_properties |=
654       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X;
655   }
656 
657   if (MFI->hasGridWorkgroupCountY()) {
658     header.code_properties |=
659       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y;
660   }
661 
662   if (MFI->hasGridWorkgroupCountZ()) {
663     header.code_properties |=
664       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z;
665   }
666 
667   if (MFI->hasDispatchPtr())
668     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
669 
670   if (STM.isXNACKEnabled())
671     header.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED;
672 
673   header.kernarg_segment_byte_size = MFI->ABIArgOffset;
674   header.wavefront_sgpr_count = KernelInfo.NumSGPR;
675   header.workitem_vgpr_count = KernelInfo.NumVGPR;
676   header.workitem_private_segment_byte_size = KernelInfo.ScratchSize;
677   header.workgroup_group_segment_byte_size = KernelInfo.LDSSize;
678 
679   AMDGPUTargetStreamer *TS =
680       static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
681   TS->EmitAMDKernelCodeT(header);
682 }
683 
684 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
685                                        unsigned AsmVariant,
686                                        const char *ExtraCode, raw_ostream &O) {
687   if (ExtraCode && ExtraCode[0]) {
688     if (ExtraCode[1] != 0)
689       return true; // Unknown modifier.
690 
691     switch (ExtraCode[0]) {
692     default:
693       // See if this is a generic print operand
694       return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
695     case 'r':
696       break;
697     }
698   }
699 
700   AMDGPUInstPrinter::printRegOperand(MI->getOperand(OpNo).getReg(), O,
701                    *TM.getSubtargetImpl(*MF->getFunction())->getRegisterInfo());
702   return false;
703 }
704