1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
15 //
16 //===----------------------------------------------------------------------===//
17 //
18 
19 #include "AMDGPUAsmPrinter.h"
20 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
21 #include "InstPrinter/AMDGPUInstPrinter.h"
22 #include "Utils/AMDGPUBaseInfo.h"
23 #include "AMDGPU.h"
24 #include "AMDKernelCodeT.h"
25 #include "AMDGPUSubtarget.h"
26 #include "R600Defines.h"
27 #include "R600MachineFunctionInfo.h"
28 #include "R600RegisterInfo.h"
29 #include "SIDefines.h"
30 #include "SIMachineFunctionInfo.h"
31 #include "SIInstrInfo.h"
32 #include "SIRegisterInfo.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/IR/DiagnosticInfo.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCSectionELF.h"
37 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/Support/ELF.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Target/TargetLoweringObjectFile.h"
42 
43 using namespace llvm;
44 
45 // TODO: This should get the default rounding mode from the kernel. We just set
46 // the default here, but this could change if the OpenCL rounding mode pragmas
47 // are used.
48 //
49 // The denormal mode here should match what is reported by the OpenCL runtime
50 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
51 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
52 //
53 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
54 // precision, and leaves single precision to flush all and does not report
55 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
56 // CL_FP_DENORM for both.
57 //
58 // FIXME: It seems some instructions do not support single precision denormals
59 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
60 // and sin_f32, cos_f32 on most parts).
61 
62 // We want to use these instructions, and using fp32 denormals also causes
63 // instructions to run at the double precision rate for the device so it's
64 // probably best to just report no single precision denormals.
65 static uint32_t getFPMode(const MachineFunction &F) {
66   const SISubtarget& ST = F.getSubtarget<SISubtarget>();
67   // TODO: Is there any real use for the flush in only / flush out only modes?
68 
69   uint32_t FP32Denormals =
70     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
71 
72   uint32_t FP64Denormals =
73     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
74 
75   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
76          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
77          FP_DENORM_MODE_SP(FP32Denormals) |
78          FP_DENORM_MODE_DP(FP64Denormals);
79 }
80 
81 static AsmPrinter *
82 createAMDGPUAsmPrinterPass(TargetMachine &tm,
83                            std::unique_ptr<MCStreamer> &&Streamer) {
84   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
85 }
86 
87 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
88   TargetRegistry::RegisterAsmPrinter(getTheAMDGPUTarget(),
89                                      createAMDGPUAsmPrinterPass);
90   TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(),
91                                      createAMDGPUAsmPrinterPass);
92 }
93 
94 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
95                                    std::unique_ptr<MCStreamer> Streamer)
96   : AsmPrinter(TM, std::move(Streamer)) {}
97 
98 StringRef AMDGPUAsmPrinter::getPassName() const {
99   return "AMDGPU Assembly Printer";
100 }
101 
102 void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) {
103   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
104     return;
105 
106   AMDGPUTargetStreamer *TS =
107       static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
108 
109   TS->EmitDirectiveHSACodeObjectVersion(2, 1);
110 
111   const MCSubtargetInfo *STI = TM.getMCSubtargetInfo();
112   AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI->getFeatureBits());
113   TS->EmitDirectiveHSACodeObjectISA(ISA.Major, ISA.Minor, ISA.Stepping,
114                                     "AMD", "AMDGPU");
115 
116   // Emit runtime metadata.
117   TS->EmitRuntimeMetadata(M);
118 }
119 
120 bool AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough(
121   const MachineBasicBlock *MBB) const {
122   if (!AsmPrinter::isBlockOnlyReachableByFallthrough(MBB))
123     return false;
124 
125   if (MBB->empty())
126     return true;
127 
128   // If this is a block implementing a long branch, an expression relative to
129   // the start of the block is needed.  to the start of the block.
130   // XXX - Is there a smarter way to check this?
131   return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
132 }
133 
134 
135 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
136   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
137   SIProgramInfo KernelInfo;
138   if (STM.isAmdCodeObjectV2(*MF)) {
139     getSIProgramInfo(KernelInfo, *MF);
140     EmitAmdKernelCodeT(*MF, KernelInfo);
141   }
142 }
143 
144 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
145   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
146   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
147   if (MFI->isKernel() && STM.isAmdCodeObjectV2(*MF)) {
148     AMDGPUTargetStreamer *TS =
149         static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
150     SmallString<128> SymbolName;
151     getNameWithPrefix(SymbolName, MF->getFunction()),
152     TS->EmitAMDGPUSymbolType(SymbolName, ELF::STT_AMDGPU_HSA_KERNEL);
153   }
154 
155   AsmPrinter::EmitFunctionEntryLabel();
156 }
157 
158 void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
159 
160   // Group segment variables aren't emitted in HSA.
161   if (AMDGPU::isGroupSegment(GV))
162     return;
163 
164   AsmPrinter::EmitGlobalVariable(GV);
165 }
166 
167 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
168 
169   // The starting address of all shader programs must be 256 bytes aligned.
170   MF.setAlignment(8);
171 
172   SetupMachineFunction(MF);
173 
174   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
175   MCContext &Context = getObjFileLowering().getContext();
176   if (!STM.isAmdHsaOS()) {
177     MCSectionELF *ConfigSection =
178         Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
179     OutStreamer->SwitchSection(ConfigSection);
180   }
181 
182   SIProgramInfo KernelInfo;
183   if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
184     getSIProgramInfo(KernelInfo, MF);
185     if (!STM.isAmdHsaOS()) {
186       EmitProgramInfoSI(MF, KernelInfo);
187     }
188   } else {
189     EmitProgramInfoR600(MF);
190   }
191 
192   DisasmLines.clear();
193   HexLines.clear();
194   DisasmLineMaxLen = 0;
195 
196   EmitFunctionBody();
197 
198   if (isVerbose()) {
199     MCSectionELF *CommentSection =
200         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
201     OutStreamer->SwitchSection(CommentSection);
202 
203     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
204       OutStreamer->emitRawComment(" Kernel info:", false);
205       OutStreamer->emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
206                                   false);
207       OutStreamer->emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
208                                   false);
209       OutStreamer->emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
210                                   false);
211       OutStreamer->emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
212                                   false);
213       OutStreamer->emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
214                                   false);
215       OutStreamer->emitRawComment(" ScratchSize: " + Twine(KernelInfo.ScratchSize),
216                                   false);
217       OutStreamer->emitRawComment(" LDSByteSize: " + Twine(KernelInfo.LDSSize) +
218                                   " bytes/workgroup (compile time only)", false);
219 
220       OutStreamer->emitRawComment(" SGPRBlocks: " +
221                                   Twine(KernelInfo.SGPRBlocks), false);
222       OutStreamer->emitRawComment(" VGPRBlocks: " +
223                                   Twine(KernelInfo.VGPRBlocks), false);
224 
225       OutStreamer->emitRawComment(" NumSGPRsForWavesPerEU: " +
226                                   Twine(KernelInfo.NumSGPRsForWavesPerEU), false);
227       OutStreamer->emitRawComment(" NumVGPRsForWavesPerEU: " +
228                                   Twine(KernelInfo.NumVGPRsForWavesPerEU), false);
229 
230       OutStreamer->emitRawComment(" ReservedVGPRFirst: " + Twine(KernelInfo.ReservedVGPRFirst),
231                                   false);
232       OutStreamer->emitRawComment(" ReservedVGPRCount: " + Twine(KernelInfo.ReservedVGPRCount),
233                                   false);
234 
235       if (MF.getSubtarget<SISubtarget>().debuggerEmitPrologue()) {
236         OutStreamer->emitRawComment(" DebuggerWavefrontPrivateSegmentOffsetSGPR: s" +
237                                     Twine(KernelInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR), false);
238         OutStreamer->emitRawComment(" DebuggerPrivateSegmentBufferSGPR: s" +
239                                     Twine(KernelInfo.DebuggerPrivateSegmentBufferSGPR), false);
240       }
241 
242       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:USER_SGPR: " +
243                                   Twine(G_00B84C_USER_SGPR(KernelInfo.ComputePGMRSrc2)),
244                                   false);
245       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_X_EN: " +
246                                   Twine(G_00B84C_TGID_X_EN(KernelInfo.ComputePGMRSrc2)),
247                                   false);
248       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
249                                   Twine(G_00B84C_TGID_Y_EN(KernelInfo.ComputePGMRSrc2)),
250                                   false);
251       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
252                                   Twine(G_00B84C_TGID_Z_EN(KernelInfo.ComputePGMRSrc2)),
253                                   false);
254       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
255                                   Twine(G_00B84C_TIDIG_COMP_CNT(KernelInfo.ComputePGMRSrc2)),
256                                   false);
257 
258     } else {
259       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
260       OutStreamer->emitRawComment(
261         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->CFStackSize)));
262     }
263   }
264 
265   if (STM.dumpCode()) {
266 
267     OutStreamer->SwitchSection(
268         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
269 
270     for (size_t i = 0; i < DisasmLines.size(); ++i) {
271       std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
272       Comment += " ; " + HexLines[i] + "\n";
273 
274       OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
275       OutStreamer->EmitBytes(StringRef(Comment));
276     }
277   }
278 
279   return false;
280 }
281 
282 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
283   unsigned MaxGPR = 0;
284   bool killPixel = false;
285   const R600Subtarget &STM = MF.getSubtarget<R600Subtarget>();
286   const R600RegisterInfo *RI = STM.getRegisterInfo();
287   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
288 
289   for (const MachineBasicBlock &MBB : MF) {
290     for (const MachineInstr &MI : MBB) {
291       if (MI.getOpcode() == AMDGPU::KILLGT)
292         killPixel = true;
293       unsigned numOperands = MI.getNumOperands();
294       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
295         const MachineOperand &MO = MI.getOperand(op_idx);
296         if (!MO.isReg())
297           continue;
298         unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
299 
300         // Register with value > 127 aren't GPR
301         if (HWReg > 127)
302           continue;
303         MaxGPR = std::max(MaxGPR, HWReg);
304       }
305     }
306   }
307 
308   unsigned RsrcReg;
309   if (STM.getGeneration() >= R600Subtarget::EVERGREEN) {
310     // Evergreen / Northern Islands
311     switch (MF.getFunction()->getCallingConv()) {
312     default: LLVM_FALLTHROUGH;
313     case CallingConv::AMDGPU_CS: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
314     case CallingConv::AMDGPU_GS: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
315     case CallingConv::AMDGPU_PS: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
316     case CallingConv::AMDGPU_VS: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
317     }
318   } else {
319     // R600 / R700
320     switch (MF.getFunction()->getCallingConv()) {
321     default: LLVM_FALLTHROUGH;
322     case CallingConv::AMDGPU_GS: LLVM_FALLTHROUGH;
323     case CallingConv::AMDGPU_CS: LLVM_FALLTHROUGH;
324     case CallingConv::AMDGPU_VS: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
325     case CallingConv::AMDGPU_PS: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
326     }
327   }
328 
329   OutStreamer->EmitIntValue(RsrcReg, 4);
330   OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
331                            S_STACK_SIZE(MFI->CFStackSize), 4);
332   OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
333   OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
334 
335   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
336     OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
337     OutStreamer->EmitIntValue(alignTo(MFI->getLDSSize(), 4) >> 2, 4);
338   }
339 }
340 
341 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
342                                         const MachineFunction &MF) const {
343   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
344   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
345   uint64_t CodeSize = 0;
346   unsigned MaxSGPR = 0;
347   unsigned MaxVGPR = 0;
348   bool VCCUsed = false;
349   bool FlatUsed = false;
350   const SIRegisterInfo *RI = STM.getRegisterInfo();
351   const SIInstrInfo *TII = STM.getInstrInfo();
352 
353   for (const MachineBasicBlock &MBB : MF) {
354     for (const MachineInstr &MI : MBB) {
355       // TODO: CodeSize should account for multiple functions.
356 
357       // TODO: Should we count size of debug info?
358       if (MI.isDebugValue())
359         continue;
360 
361       if (isVerbose())
362         CodeSize += TII->getInstSizeInBytes(MI);
363 
364       unsigned numOperands = MI.getNumOperands();
365       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
366         const MachineOperand &MO = MI.getOperand(op_idx);
367         unsigned width = 0;
368         bool isSGPR = false;
369 
370         if (!MO.isReg())
371           continue;
372 
373         unsigned reg = MO.getReg();
374         switch (reg) {
375         case AMDGPU::EXEC:
376         case AMDGPU::EXEC_LO:
377         case AMDGPU::EXEC_HI:
378         case AMDGPU::SCC:
379         case AMDGPU::M0:
380           continue;
381 
382         case AMDGPU::VCC:
383         case AMDGPU::VCC_LO:
384         case AMDGPU::VCC_HI:
385           VCCUsed = true;
386           continue;
387 
388         case AMDGPU::FLAT_SCR:
389         case AMDGPU::FLAT_SCR_LO:
390         case AMDGPU::FLAT_SCR_HI:
391           // Even if FLAT_SCRATCH is implicitly used, it has no effect if flat
392           // instructions aren't used to access the scratch buffer.
393           if (MFI->hasFlatScratchInit())
394             FlatUsed = true;
395           continue;
396 
397         case AMDGPU::TBA:
398         case AMDGPU::TBA_LO:
399         case AMDGPU::TBA_HI:
400         case AMDGPU::TMA:
401         case AMDGPU::TMA_LO:
402         case AMDGPU::TMA_HI:
403           llvm_unreachable("trap handler registers should not be used");
404 
405         default:
406           break;
407         }
408 
409         if (AMDGPU::SReg_32RegClass.contains(reg)) {
410           assert(!AMDGPU::TTMP_32RegClass.contains(reg) &&
411                  "trap handler registers should not be used");
412           isSGPR = true;
413           width = 1;
414         } else if (AMDGPU::VGPR_32RegClass.contains(reg)) {
415           isSGPR = false;
416           width = 1;
417         } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
418           assert(!AMDGPU::TTMP_64RegClass.contains(reg) &&
419                  "trap handler registers should not be used");
420           isSGPR = true;
421           width = 2;
422         } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
423           isSGPR = false;
424           width = 2;
425         } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
426           isSGPR = false;
427           width = 3;
428         } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
429           isSGPR = true;
430           width = 4;
431         } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
432           isSGPR = false;
433           width = 4;
434         } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
435           isSGPR = true;
436           width = 8;
437         } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
438           isSGPR = false;
439           width = 8;
440         } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
441           isSGPR = true;
442           width = 16;
443         } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
444           isSGPR = false;
445           width = 16;
446         } else {
447           llvm_unreachable("Unknown register class");
448         }
449         unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
450         unsigned maxUsed = hwReg + width - 1;
451         if (isSGPR) {
452           MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
453         } else {
454           MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
455         }
456       }
457     }
458   }
459 
460   unsigned ExtraSGPRs = 0;
461 
462   if (VCCUsed)
463     ExtraSGPRs = 2;
464 
465   if (STM.getGeneration() < SISubtarget::VOLCANIC_ISLANDS) {
466     if (FlatUsed)
467       ExtraSGPRs = 4;
468   } else {
469     if (STM.isXNACKEnabled())
470       ExtraSGPRs = 4;
471 
472     if (FlatUsed)
473       ExtraSGPRs = 6;
474   }
475 
476   // Record first reserved register and reserved register count fields, and
477   // update max register counts if "amdgpu-debugger-reserve-regs" attribute was
478   // requested.
479   ProgInfo.ReservedVGPRFirst = STM.debuggerReserveRegs() ? MaxVGPR + 1 : 0;
480   ProgInfo.ReservedVGPRCount = RI->getNumDebuggerReservedVGPRs(STM);
481 
482   // Update DebuggerWavefrontPrivateSegmentOffsetSGPR and
483   // DebuggerPrivateSegmentBufferSGPR fields if "amdgpu-debugger-emit-prologue"
484   // attribute was requested.
485   if (STM.debuggerEmitPrologue()) {
486     ProgInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR =
487       RI->getHWRegIndex(MFI->getScratchWaveOffsetReg());
488     ProgInfo.DebuggerPrivateSegmentBufferSGPR =
489       RI->getHWRegIndex(MFI->getScratchRSrcReg());
490   }
491 
492   // Check the addressable register limit before we add ExtraSGPRs.
493   if (STM.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
494       !STM.hasSGPRInitBug()) {
495     unsigned MaxAddressableNumSGPRs = STM.getMaxNumSGPRs();
496     if (MaxSGPR + 1 > MaxAddressableNumSGPRs) {
497       // This can happen due to a compiler bug or when using inline asm.
498       LLVMContext &Ctx = MF.getFunction()->getContext();
499       DiagnosticInfoResourceLimit Diag(*MF.getFunction(),
500                                        "addressable scalar registers",
501                                        MaxSGPR + 1, DS_Error,
502                                        DK_ResourceLimit, MaxAddressableNumSGPRs);
503       Ctx.diagnose(Diag);
504       MaxSGPR = MaxAddressableNumSGPRs - 1;
505     }
506   }
507 
508   // Account for extra SGPRs and VGPRs reserved for debugger use.
509   MaxSGPR += ExtraSGPRs;
510   MaxVGPR += RI->getNumDebuggerReservedVGPRs(STM);
511 
512   // We found the maximum register index. They start at 0, so add one to get the
513   // number of registers.
514   ProgInfo.NumVGPR = MaxVGPR + 1;
515   ProgInfo.NumSGPR = MaxSGPR + 1;
516 
517   // Adjust number of registers used to meet default/requested minimum/maximum
518   // number of waves per execution unit request.
519   ProgInfo.NumSGPRsForWavesPerEU = std::max(
520     ProgInfo.NumSGPR, RI->getMinNumSGPRs(STM, MFI->getMaxWavesPerEU()));
521   ProgInfo.NumVGPRsForWavesPerEU = std::max(
522     ProgInfo.NumVGPR, RI->getMinNumVGPRs(MFI->getMaxWavesPerEU()));
523 
524   if (STM.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ||
525       STM.hasSGPRInitBug()) {
526     unsigned MaxNumSGPRs = STM.getMaxNumSGPRs();
527     if (ProgInfo.NumSGPR > MaxNumSGPRs) {
528       // This can happen due to a compiler bug or when using inline asm to use the
529       // registers which are usually reserved for vcc etc.
530 
531       LLVMContext &Ctx = MF.getFunction()->getContext();
532       DiagnosticInfoResourceLimit Diag(*MF.getFunction(),
533                                        "scalar registers",
534                                        ProgInfo.NumSGPR, DS_Error,
535                                        DK_ResourceLimit, MaxNumSGPRs);
536       Ctx.diagnose(Diag);
537       ProgInfo.NumSGPR = MaxNumSGPRs;
538       ProgInfo.NumSGPRsForWavesPerEU = MaxNumSGPRs;
539     }
540   }
541 
542   if (STM.hasSGPRInitBug()) {
543     ProgInfo.NumSGPR = SISubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG;
544     ProgInfo.NumSGPRsForWavesPerEU = SISubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG;
545   }
546 
547   if (MFI->NumUserSGPRs > STM.getMaxNumUserSGPRs()) {
548     LLVMContext &Ctx = MF.getFunction()->getContext();
549     DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "user SGPRs",
550                                      MFI->NumUserSGPRs, DS_Error);
551     Ctx.diagnose(Diag);
552   }
553 
554   if (MFI->getLDSSize() > static_cast<unsigned>(STM.getLocalMemorySize())) {
555     LLVMContext &Ctx = MF.getFunction()->getContext();
556     DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "local memory",
557                                      MFI->getLDSSize(), DS_Error);
558     Ctx.diagnose(Diag);
559   }
560 
561   // SGPRBlocks is actual number of SGPR blocks minus 1.
562   ProgInfo.SGPRBlocks = alignTo(ProgInfo.NumSGPRsForWavesPerEU,
563                                 RI->getSGPRAllocGranule());
564   ProgInfo.SGPRBlocks = ProgInfo.SGPRBlocks / RI->getSGPRAllocGranule() - 1;
565 
566   // VGPRBlocks is actual number of VGPR blocks minus 1.
567   ProgInfo.VGPRBlocks = alignTo(ProgInfo.NumVGPRsForWavesPerEU,
568                                 RI->getVGPRAllocGranule());
569   ProgInfo.VGPRBlocks = ProgInfo.VGPRBlocks / RI->getVGPRAllocGranule() - 1;
570 
571   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
572   // register.
573   ProgInfo.FloatMode = getFPMode(MF);
574 
575   ProgInfo.IEEEMode = STM.enableIEEEBit(MF);
576 
577   // Make clamp modifier on NaN input returns 0.
578   ProgInfo.DX10Clamp = 1;
579 
580   const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
581   ProgInfo.ScratchSize = FrameInfo.getStackSize();
582 
583   ProgInfo.FlatUsed = FlatUsed;
584   ProgInfo.VCCUsed = VCCUsed;
585   ProgInfo.CodeLen = CodeSize;
586 
587   unsigned LDSAlignShift;
588   if (STM.getGeneration() < SISubtarget::SEA_ISLANDS) {
589     // LDS is allocated in 64 dword blocks.
590     LDSAlignShift = 8;
591   } else {
592     // LDS is allocated in 128 dword blocks.
593     LDSAlignShift = 9;
594   }
595 
596   unsigned LDSSpillSize =
597     MFI->LDSWaveSpillSize * MFI->getMaxFlatWorkGroupSize();
598 
599   ProgInfo.LDSSize = MFI->getLDSSize() + LDSSpillSize;
600   ProgInfo.LDSBlocks =
601       alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
602 
603   // Scratch is allocated in 256 dword blocks.
604   unsigned ScratchAlignShift = 10;
605   // We need to program the hardware with the amount of scratch memory that
606   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
607   // scratch memory used per thread.
608   ProgInfo.ScratchBlocks =
609       alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
610               1ULL << ScratchAlignShift) >>
611       ScratchAlignShift;
612 
613   ProgInfo.ComputePGMRSrc1 =
614       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
615       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
616       S_00B848_PRIORITY(ProgInfo.Priority) |
617       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
618       S_00B848_PRIV(ProgInfo.Priv) |
619       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
620       S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
621       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
622 
623   // 0 = X, 1 = XY, 2 = XYZ
624   unsigned TIDIGCompCnt = 0;
625   if (MFI->hasWorkItemIDZ())
626     TIDIGCompCnt = 2;
627   else if (MFI->hasWorkItemIDY())
628     TIDIGCompCnt = 1;
629 
630   ProgInfo.ComputePGMRSrc2 =
631       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
632       S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
633       S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
634       S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
635       S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
636       S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
637       S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
638       S_00B84C_EXCP_EN_MSB(0) |
639       S_00B84C_LDS_SIZE(ProgInfo.LDSBlocks) |
640       S_00B84C_EXCP_EN(0);
641 }
642 
643 static unsigned getRsrcReg(CallingConv::ID CallConv) {
644   switch (CallConv) {
645   default: LLVM_FALLTHROUGH;
646   case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
647   case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
648   case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
649   case CallingConv::AMDGPU_VS: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
650   }
651 }
652 
653 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
654                                          const SIProgramInfo &KernelInfo) {
655   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
656   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
657   unsigned RsrcReg = getRsrcReg(MF.getFunction()->getCallingConv());
658 
659   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
660     OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
661 
662     OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc1, 4);
663 
664     OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
665     OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc2, 4);
666 
667     OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
668     OutStreamer->EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4);
669 
670     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
671     // 0" comment but I don't see a corresponding field in the register spec.
672   } else {
673     OutStreamer->EmitIntValue(RsrcReg, 4);
674     OutStreamer->EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
675                               S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4);
676     if (STM.isVGPRSpillingEnabled(*MF.getFunction())) {
677       OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
678       OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(KernelInfo.ScratchBlocks), 4);
679     }
680   }
681 
682   if (MF.getFunction()->getCallingConv() == CallingConv::AMDGPU_PS) {
683     OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
684     OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4);
685     OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
686     OutStreamer->EmitIntValue(MFI->PSInputEna, 4);
687     OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
688     OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4);
689   }
690 
691   OutStreamer->EmitIntValue(R_SPILLED_SGPRS, 4);
692   OutStreamer->EmitIntValue(MFI->getNumSpilledSGPRs(), 4);
693   OutStreamer->EmitIntValue(R_SPILLED_VGPRS, 4);
694   OutStreamer->EmitIntValue(MFI->getNumSpilledVGPRs(), 4);
695 }
696 
697 // This is supposed to be log2(Size)
698 static amd_element_byte_size_t getElementByteSizeValue(unsigned Size) {
699   switch (Size) {
700   case 4:
701     return AMD_ELEMENT_4_BYTES;
702   case 8:
703     return AMD_ELEMENT_8_BYTES;
704   case 16:
705     return AMD_ELEMENT_16_BYTES;
706   default:
707     llvm_unreachable("invalid private_element_size");
708   }
709 }
710 
711 void AMDGPUAsmPrinter::EmitAmdKernelCodeT(const MachineFunction &MF,
712                                          const SIProgramInfo &KernelInfo) const {
713   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
714   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
715   amd_kernel_code_t header;
716 
717   AMDGPU::initDefaultAMDKernelCodeT(header, STM.getFeatureBits());
718 
719   header.compute_pgm_resource_registers =
720       KernelInfo.ComputePGMRSrc1 |
721       (KernelInfo.ComputePGMRSrc2 << 32);
722   header.code_properties = AMD_CODE_PROPERTY_IS_PTR64;
723 
724 
725   AMD_HSA_BITS_SET(header.code_properties,
726                    AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE,
727                    getElementByteSizeValue(STM.getMaxPrivateElementSize()));
728 
729   if (MFI->hasPrivateSegmentBuffer()) {
730     header.code_properties |=
731       AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
732   }
733 
734   if (MFI->hasDispatchPtr())
735     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
736 
737   if (MFI->hasQueuePtr())
738     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
739 
740   if (MFI->hasKernargSegmentPtr())
741     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
742 
743   if (MFI->hasDispatchID())
744     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
745 
746   if (MFI->hasFlatScratchInit())
747     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
748 
749   // TODO: Private segment size
750 
751   if (MFI->hasGridWorkgroupCountX()) {
752     header.code_properties |=
753       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X;
754   }
755 
756   if (MFI->hasGridWorkgroupCountY()) {
757     header.code_properties |=
758       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y;
759   }
760 
761   if (MFI->hasGridWorkgroupCountZ()) {
762     header.code_properties |=
763       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z;
764   }
765 
766   if (MFI->hasDispatchPtr())
767     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
768 
769   if (STM.debuggerSupported())
770     header.code_properties |= AMD_CODE_PROPERTY_IS_DEBUG_SUPPORTED;
771 
772   if (STM.isXNACKEnabled())
773     header.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED;
774 
775   // FIXME: Should use getKernArgSize
776   header.kernarg_segment_byte_size =
777     STM.getKernArgSegmentSize(MF, MFI->getABIArgOffset());
778   header.wavefront_sgpr_count = KernelInfo.NumSGPR;
779   header.workitem_vgpr_count = KernelInfo.NumVGPR;
780   header.workitem_private_segment_byte_size = KernelInfo.ScratchSize;
781   header.workgroup_group_segment_byte_size = KernelInfo.LDSSize;
782   header.reserved_vgpr_first = KernelInfo.ReservedVGPRFirst;
783   header.reserved_vgpr_count = KernelInfo.ReservedVGPRCount;
784 
785   // These alignment values are specified in powers of two, so alignment =
786   // 2^n.  The minimum alignment is 2^4 = 16.
787   header.kernarg_segment_alignment = std::max((size_t)4,
788       countTrailingZeros(MFI->getMaxKernArgAlign()));
789 
790   if (STM.debuggerEmitPrologue()) {
791     header.debug_wavefront_private_segment_offset_sgpr =
792       KernelInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR;
793     header.debug_private_segment_buffer_sgpr =
794       KernelInfo.DebuggerPrivateSegmentBufferSGPR;
795   }
796 
797   AMDGPUTargetStreamer *TS =
798       static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
799 
800   OutStreamer->SwitchSection(getObjFileLowering().getTextSection());
801   TS->EmitAMDKernelCodeT(header);
802 }
803 
804 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
805                                        unsigned AsmVariant,
806                                        const char *ExtraCode, raw_ostream &O) {
807   if (ExtraCode && ExtraCode[0]) {
808     if (ExtraCode[1] != 0)
809       return true; // Unknown modifier.
810 
811     switch (ExtraCode[0]) {
812     default:
813       // See if this is a generic print operand
814       return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
815     case 'r':
816       break;
817     }
818   }
819 
820   AMDGPUInstPrinter::printRegOperand(MI->getOperand(OpNo).getReg(), O,
821                    *TM.getSubtargetImpl(*MF->getFunction())->getRegisterInfo());
822   return false;
823 }
824