1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
15 //
16 //===----------------------------------------------------------------------===//
17 //
18 
19 #include "AMDGPUAsmPrinter.h"
20 #include "AMDGPU.h"
21 #include "AMDGPUSubtarget.h"
22 #include "AMDGPUTargetMachine.h"
23 #include "InstPrinter/AMDGPUInstPrinter.h"
24 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
25 #include "R600Defines.h"
26 #include "R600MachineFunctionInfo.h"
27 #include "R600RegisterInfo.h"
28 #include "SIDefines.h"
29 #include "SIInstrInfo.h"
30 #include "SIMachineFunctionInfo.h"
31 #include "SIRegisterInfo.h"
32 #include "Utils/AMDGPUBaseInfo.h"
33 #include "llvm/BinaryFormat/ELF.h"
34 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/IR/DiagnosticInfo.h"
36 #include "llvm/MC/MCContext.h"
37 #include "llvm/MC/MCSectionELF.h"
38 #include "llvm/MC/MCStreamer.h"
39 #include "llvm/Support/AMDGPUMetadata.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Target/TargetLoweringObjectFile.h"
43 
44 using namespace llvm;
45 using namespace llvm::AMDGPU;
46 
47 // TODO: This should get the default rounding mode from the kernel. We just set
48 // the default here, but this could change if the OpenCL rounding mode pragmas
49 // are used.
50 //
51 // The denormal mode here should match what is reported by the OpenCL runtime
52 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
53 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
54 //
55 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
56 // precision, and leaves single precision to flush all and does not report
57 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
58 // CL_FP_DENORM for both.
59 //
60 // FIXME: It seems some instructions do not support single precision denormals
61 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
62 // and sin_f32, cos_f32 on most parts).
63 
64 // We want to use these instructions, and using fp32 denormals also causes
65 // instructions to run at the double precision rate for the device so it's
66 // probably best to just report no single precision denormals.
67 static uint32_t getFPMode(const MachineFunction &F) {
68   const SISubtarget& ST = F.getSubtarget<SISubtarget>();
69   // TODO: Is there any real use for the flush in only / flush out only modes?
70 
71   uint32_t FP32Denormals =
72     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
73 
74   uint32_t FP64Denormals =
75     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
76 
77   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
78          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
79          FP_DENORM_MODE_SP(FP32Denormals) |
80          FP_DENORM_MODE_DP(FP64Denormals);
81 }
82 
83 static AsmPrinter *
84 createAMDGPUAsmPrinterPass(TargetMachine &tm,
85                            std::unique_ptr<MCStreamer> &&Streamer) {
86   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
87 }
88 
89 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
90   TargetRegistry::RegisterAsmPrinter(getTheAMDGPUTarget(),
91                                      createAMDGPUAsmPrinterPass);
92   TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(),
93                                      createAMDGPUAsmPrinterPass);
94 }
95 
96 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
97                                    std::unique_ptr<MCStreamer> Streamer)
98   : AsmPrinter(TM, std::move(Streamer)) {
99     AMDGPUASI = static_cast<AMDGPUTargetMachine*>(&TM)->getAMDGPUAS();
100   }
101 
102 StringRef AMDGPUAsmPrinter::getPassName() const {
103   return "AMDGPU Assembly Printer";
104 }
105 
106 const MCSubtargetInfo* AMDGPUAsmPrinter::getSTI() const {
107   return TM.getMCSubtargetInfo();
108 }
109 
110 AMDGPUTargetStreamer* AMDGPUAsmPrinter::getTargetStreamer() const {
111   if (!OutStreamer)
112     return nullptr;
113   return static_cast<AMDGPUTargetStreamer*>(OutStreamer->getTargetStreamer());
114 }
115 
116 void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) {
117   if (TM.getTargetTriple().getArch() != Triple::amdgcn)
118     return;
119 
120   if (TM.getTargetTriple().getOS() != Triple::AMDHSA &&
121       TM.getTargetTriple().getOS() != Triple::AMDPAL)
122     return;
123 
124   if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
125     HSAMetadataStream.begin(M);
126 
127   if (TM.getTargetTriple().getOS() == Triple::AMDPAL)
128     readPALMetadata(M);
129 
130   // Deprecated notes are not emitted for code object v3.
131   if (IsaInfo::hasCodeObjectV3(getSTI()->getFeatureBits()))
132     return;
133 
134   // HSA emits NT_AMDGPU_HSA_CODE_OBJECT_VERSION for code objects v2.
135   if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
136     getTargetStreamer()->EmitDirectiveHSACodeObjectVersion(2, 1);
137 
138   // HSA and PAL emit NT_AMDGPU_HSA_ISA for code objects v2.
139   IsaInfo::IsaVersion ISA = IsaInfo::getIsaVersion(getSTI()->getFeatureBits());
140   getTargetStreamer()->EmitDirectiveHSACodeObjectISA(
141       ISA.Major, ISA.Minor, ISA.Stepping, "AMD", "AMDGPU");
142 }
143 
144 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
145   if (TM.getTargetTriple().getArch() != Triple::amdgcn)
146     return;
147 
148   // Following code requires TargetStreamer to be present.
149   if (!getTargetStreamer())
150     return;
151 
152   // Emit ISA Version (NT_AMD_AMDGPU_ISA).
153   std::string ISAVersionString;
154   raw_string_ostream ISAVersionStream(ISAVersionString);
155   IsaInfo::streamIsaVersion(getSTI(), ISAVersionStream);
156   getTargetStreamer()->EmitISAVersion(ISAVersionStream.str());
157 
158   // Emit HSA Metadata (NT_AMD_AMDGPU_HSA_METADATA).
159   if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
160     HSAMetadataStream.end();
161     getTargetStreamer()->EmitHSAMetadata(HSAMetadataStream.getHSAMetadata());
162   }
163 
164   // Emit PAL Metadata (NT_AMD_AMDGPU_PAL_METADATA).
165   if (TM.getTargetTriple().getOS() == Triple::AMDPAL) {
166     // Copy the PAL metadata from the map where we collected it into a vector,
167     // then write it as a .note.
168     PALMD::Metadata PALMetadataVector;
169     for (auto i : PALMetadataMap) {
170       PALMetadataVector.push_back(i.first);
171       PALMetadataVector.push_back(i.second);
172     }
173     getTargetStreamer()->EmitPALMetadata(PALMetadataVector);
174   }
175 }
176 
177 bool AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough(
178   const MachineBasicBlock *MBB) const {
179   if (!AsmPrinter::isBlockOnlyReachableByFallthrough(MBB))
180     return false;
181 
182   if (MBB->empty())
183     return true;
184 
185   // If this is a block implementing a long branch, an expression relative to
186   // the start of the block is needed.  to the start of the block.
187   // XXX - Is there a smarter way to check this?
188   return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
189 }
190 
191 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
192   const AMDGPUMachineFunction *MFI = MF->getInfo<AMDGPUMachineFunction>();
193   if (!MFI->isEntryFunction())
194     return;
195 
196   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
197   amd_kernel_code_t KernelCode;
198   if (STM.isAmdCodeObjectV2(*MF)) {
199     getAmdKernelCode(KernelCode, CurrentProgramInfo, *MF);
200 
201     OutStreamer->SwitchSection(getObjFileLowering().getTextSection());
202     getTargetStreamer()->EmitAMDKernelCodeT(KernelCode);
203   }
204 
205   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
206     return;
207 
208   HSAMetadataStream.emitKernel(*MF->getFunction(),
209                                getHSACodeProps(*MF, CurrentProgramInfo),
210                                getHSADebugProps(*MF, CurrentProgramInfo));
211 }
212 
213 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
214   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
215   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
216   if (MFI->isEntryFunction() && STM.isAmdCodeObjectV2(*MF)) {
217     SmallString<128> SymbolName;
218     getNameWithPrefix(SymbolName, MF->getFunction()),
219     getTargetStreamer()->EmitAMDGPUSymbolType(
220         SymbolName, ELF::STT_AMDGPU_HSA_KERNEL);
221   }
222 
223   AsmPrinter::EmitFunctionEntryLabel();
224 }
225 
226 void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
227 
228   // Group segment variables aren't emitted in HSA.
229   if (AMDGPU::isGroupSegment(GV, AMDGPUASI))
230     return;
231 
232   AsmPrinter::EmitGlobalVariable(GV);
233 }
234 
235 bool AMDGPUAsmPrinter::doFinalization(Module &M) {
236   CallGraphResourceInfo.clear();
237   return AsmPrinter::doFinalization(M);
238 }
239 
240 // For the amdpal OS type, read the amdgpu.pal.metadata supplied by the
241 // frontend into our PALMetadataMap, ready for per-function modification.  It
242 // is a NamedMD containing an MDTuple containing a number of MDNodes each of
243 // which is an integer value, and each two integer values forms a key=value
244 // pair that we store as PALMetadataMap[key]=value in the map.
245 void AMDGPUAsmPrinter::readPALMetadata(Module &M) {
246   auto NamedMD = M.getNamedMetadata("amdgpu.pal.metadata");
247   if (!NamedMD || !NamedMD->getNumOperands())
248     return;
249   auto Tuple = dyn_cast<MDTuple>(NamedMD->getOperand(0));
250   if (!Tuple)
251     return;
252   for (unsigned I = 0, E = Tuple->getNumOperands() & -2; I != E; I += 2) {
253     auto Key = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I));
254     auto Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I + 1));
255     if (!Key || !Val)
256       continue;
257     PALMetadataMap[Key->getZExtValue()] = Val->getZExtValue();
258   }
259 }
260 
261 // Print comments that apply to both callable functions and entry points.
262 void AMDGPUAsmPrinter::emitCommonFunctionComments(
263   uint32_t NumVGPR,
264   uint32_t NumSGPR,
265   uint32_t ScratchSize,
266   uint64_t CodeSize) {
267   OutStreamer->emitRawComment(" codeLenInByte = " + Twine(CodeSize), false);
268   OutStreamer->emitRawComment(" NumSgprs: " + Twine(NumSGPR), false);
269   OutStreamer->emitRawComment(" NumVgprs: " + Twine(NumVGPR), false);
270   OutStreamer->emitRawComment(" ScratchSize: " + Twine(ScratchSize), false);
271 }
272 
273 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
274   CurrentProgramInfo = SIProgramInfo();
275 
276   const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
277 
278   // The starting address of all shader programs must be 256 bytes aligned.
279   // Regular functions just need the basic required instruction alignment.
280   MF.setAlignment(MFI->isEntryFunction() ? 8 : 2);
281 
282   SetupMachineFunction(MF);
283 
284   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
285   MCContext &Context = getObjFileLowering().getContext();
286   if (!STM.isAmdHsaOS()) {
287     MCSectionELF *ConfigSection =
288         Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
289     OutStreamer->SwitchSection(ConfigSection);
290   }
291 
292   if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
293     if (MFI->isEntryFunction()) {
294       getSIProgramInfo(CurrentProgramInfo, MF);
295     } else {
296       auto I = CallGraphResourceInfo.insert(
297         std::make_pair(MF.getFunction(), SIFunctionResourceInfo()));
298       SIFunctionResourceInfo &Info = I.first->second;
299       assert(I.second && "should only be called once per function");
300       Info = analyzeResourceUsage(MF);
301     }
302 
303     if (STM.isAmdPalOS())
304       EmitPALMetadata(MF, CurrentProgramInfo);
305     if (!STM.isAmdHsaOS()) {
306       EmitProgramInfoSI(MF, CurrentProgramInfo);
307     }
308   } else {
309     EmitProgramInfoR600(MF);
310   }
311 
312   DisasmLines.clear();
313   HexLines.clear();
314   DisasmLineMaxLen = 0;
315 
316   EmitFunctionBody();
317 
318   if (isVerbose()) {
319     MCSectionELF *CommentSection =
320         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
321     OutStreamer->SwitchSection(CommentSection);
322 
323     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
324       if (!MFI->isEntryFunction()) {
325         OutStreamer->emitRawComment(" Function info:", false);
326         SIFunctionResourceInfo &Info = CallGraphResourceInfo[MF.getFunction()];
327         emitCommonFunctionComments(
328           Info.NumVGPR,
329           Info.getTotalNumSGPRs(MF.getSubtarget<SISubtarget>()),
330           Info.PrivateSegmentSize,
331           getFunctionCodeSize(MF));
332         return false;
333       }
334 
335       OutStreamer->emitRawComment(" Kernel info:", false);
336       emitCommonFunctionComments(CurrentProgramInfo.NumVGPR,
337                                  CurrentProgramInfo.NumSGPR,
338                                  CurrentProgramInfo.ScratchSize,
339                                  getFunctionCodeSize(MF));
340 
341       OutStreamer->emitRawComment(
342         " FloatMode: " + Twine(CurrentProgramInfo.FloatMode), false);
343       OutStreamer->emitRawComment(
344         " IeeeMode: " + Twine(CurrentProgramInfo.IEEEMode), false);
345       OutStreamer->emitRawComment(
346         " LDSByteSize: " + Twine(CurrentProgramInfo.LDSSize) +
347         " bytes/workgroup (compile time only)", false);
348 
349       OutStreamer->emitRawComment(
350         " SGPRBlocks: " + Twine(CurrentProgramInfo.SGPRBlocks), false);
351       OutStreamer->emitRawComment(
352         " VGPRBlocks: " + Twine(CurrentProgramInfo.VGPRBlocks), false);
353 
354       OutStreamer->emitRawComment(
355         " NumSGPRsForWavesPerEU: " +
356         Twine(CurrentProgramInfo.NumSGPRsForWavesPerEU), false);
357       OutStreamer->emitRawComment(
358         " NumVGPRsForWavesPerEU: " +
359         Twine(CurrentProgramInfo.NumVGPRsForWavesPerEU), false);
360 
361       OutStreamer->emitRawComment(
362         " ReservedVGPRFirst: " + Twine(CurrentProgramInfo.ReservedVGPRFirst),
363         false);
364       OutStreamer->emitRawComment(
365         " ReservedVGPRCount: " + Twine(CurrentProgramInfo.ReservedVGPRCount),
366         false);
367 
368       if (MF.getSubtarget<SISubtarget>().debuggerEmitPrologue()) {
369         OutStreamer->emitRawComment(
370           " DebuggerWavefrontPrivateSegmentOffsetSGPR: s" +
371           Twine(CurrentProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR), false);
372         OutStreamer->emitRawComment(
373           " DebuggerPrivateSegmentBufferSGPR: s" +
374           Twine(CurrentProgramInfo.DebuggerPrivateSegmentBufferSGPR), false);
375       }
376 
377       OutStreamer->emitRawComment(
378         " COMPUTE_PGM_RSRC2:USER_SGPR: " +
379         Twine(G_00B84C_USER_SGPR(CurrentProgramInfo.ComputePGMRSrc2)), false);
380       OutStreamer->emitRawComment(
381         " COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
382         Twine(G_00B84C_TRAP_HANDLER(CurrentProgramInfo.ComputePGMRSrc2)), false);
383       OutStreamer->emitRawComment(
384         " COMPUTE_PGM_RSRC2:TGID_X_EN: " +
385         Twine(G_00B84C_TGID_X_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
386       OutStreamer->emitRawComment(
387         " COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
388         Twine(G_00B84C_TGID_Y_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
389       OutStreamer->emitRawComment(
390         " COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
391         Twine(G_00B84C_TGID_Z_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
392       OutStreamer->emitRawComment(
393         " COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
394         Twine(G_00B84C_TIDIG_COMP_CNT(CurrentProgramInfo.ComputePGMRSrc2)),
395         false);
396     } else {
397       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
398       OutStreamer->emitRawComment(
399         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->CFStackSize)));
400     }
401   }
402 
403   if (STM.dumpCode()) {
404 
405     OutStreamer->SwitchSection(
406         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
407 
408     for (size_t i = 0; i < DisasmLines.size(); ++i) {
409       std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
410       Comment += " ; " + HexLines[i] + "\n";
411 
412       OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
413       OutStreamer->EmitBytes(StringRef(Comment));
414     }
415   }
416 
417   return false;
418 }
419 
420 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
421   unsigned MaxGPR = 0;
422   bool killPixel = false;
423   const R600Subtarget &STM = MF.getSubtarget<R600Subtarget>();
424   const R600RegisterInfo *RI = STM.getRegisterInfo();
425   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
426 
427   for (const MachineBasicBlock &MBB : MF) {
428     for (const MachineInstr &MI : MBB) {
429       if (MI.getOpcode() == AMDGPU::KILLGT)
430         killPixel = true;
431       unsigned numOperands = MI.getNumOperands();
432       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
433         const MachineOperand &MO = MI.getOperand(op_idx);
434         if (!MO.isReg())
435           continue;
436         unsigned HWReg = RI->getHWRegIndex(MO.getReg());
437 
438         // Register with value > 127 aren't GPR
439         if (HWReg > 127)
440           continue;
441         MaxGPR = std::max(MaxGPR, HWReg);
442       }
443     }
444   }
445 
446   unsigned RsrcReg;
447   if (STM.getGeneration() >= R600Subtarget::EVERGREEN) {
448     // Evergreen / Northern Islands
449     switch (MF.getFunction()->getCallingConv()) {
450     default: LLVM_FALLTHROUGH;
451     case CallingConv::AMDGPU_CS: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
452     case CallingConv::AMDGPU_GS: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
453     case CallingConv::AMDGPU_PS: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
454     case CallingConv::AMDGPU_VS: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
455     }
456   } else {
457     // R600 / R700
458     switch (MF.getFunction()->getCallingConv()) {
459     default: LLVM_FALLTHROUGH;
460     case CallingConv::AMDGPU_GS: LLVM_FALLTHROUGH;
461     case CallingConv::AMDGPU_CS: LLVM_FALLTHROUGH;
462     case CallingConv::AMDGPU_VS: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
463     case CallingConv::AMDGPU_PS: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
464     }
465   }
466 
467   OutStreamer->EmitIntValue(RsrcReg, 4);
468   OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
469                            S_STACK_SIZE(MFI->CFStackSize), 4);
470   OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
471   OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
472 
473   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
474     OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
475     OutStreamer->EmitIntValue(alignTo(MFI->getLDSSize(), 4) >> 2, 4);
476   }
477 }
478 
479 uint64_t AMDGPUAsmPrinter::getFunctionCodeSize(const MachineFunction &MF) const {
480   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
481   const SIInstrInfo *TII = STM.getInstrInfo();
482 
483   uint64_t CodeSize = 0;
484 
485   for (const MachineBasicBlock &MBB : MF) {
486     for (const MachineInstr &MI : MBB) {
487       // TODO: CodeSize should account for multiple functions.
488 
489       // TODO: Should we count size of debug info?
490       if (MI.isDebugValue())
491         continue;
492 
493       CodeSize += TII->getInstSizeInBytes(MI);
494     }
495   }
496 
497   return CodeSize;
498 }
499 
500 static bool hasAnyNonFlatUseOfReg(const MachineRegisterInfo &MRI,
501                                   const SIInstrInfo &TII,
502                                   unsigned Reg) {
503   for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) {
504     if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent()))
505       return true;
506   }
507 
508   return false;
509 }
510 
511 static unsigned getNumExtraSGPRs(const SISubtarget &ST,
512                                  bool VCCUsed,
513                                  bool FlatScrUsed) {
514   unsigned ExtraSGPRs = 0;
515   if (VCCUsed)
516     ExtraSGPRs = 2;
517 
518   if (ST.getGeneration() < SISubtarget::VOLCANIC_ISLANDS) {
519     if (FlatScrUsed)
520       ExtraSGPRs = 4;
521   } else {
522     if (ST.isXNACKEnabled())
523       ExtraSGPRs = 4;
524 
525     if (FlatScrUsed)
526       ExtraSGPRs = 6;
527   }
528 
529   return ExtraSGPRs;
530 }
531 
532 int32_t AMDGPUAsmPrinter::SIFunctionResourceInfo::getTotalNumSGPRs(
533   const SISubtarget &ST) const {
534   return NumExplicitSGPR + getNumExtraSGPRs(ST, UsesVCC, UsesFlatScratch);
535 }
536 
537 AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
538   const MachineFunction &MF) const {
539   SIFunctionResourceInfo Info;
540 
541   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
542   const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
543   const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
544   const MachineRegisterInfo &MRI = MF.getRegInfo();
545   const SIInstrInfo *TII = ST.getInstrInfo();
546   const SIRegisterInfo &TRI = TII->getRegisterInfo();
547 
548   Info.UsesFlatScratch = MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_LO) ||
549                          MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_HI);
550 
551   // Even if FLAT_SCRATCH is implicitly used, it has no effect if flat
552   // instructions aren't used to access the scratch buffer. Inline assembly may
553   // need it though.
554   //
555   // If we only have implicit uses of flat_scr on flat instructions, it is not
556   // really needed.
557   if (Info.UsesFlatScratch && !MFI->hasFlatScratchInit() &&
558       (!hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR) &&
559        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_LO) &&
560        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_HI))) {
561     Info.UsesFlatScratch = false;
562   }
563 
564   Info.HasDynamicallySizedStack = FrameInfo.hasVarSizedObjects();
565   Info.PrivateSegmentSize = FrameInfo.getStackSize();
566 
567 
568   Info.UsesVCC = MRI.isPhysRegUsed(AMDGPU::VCC_LO) ||
569                  MRI.isPhysRegUsed(AMDGPU::VCC_HI);
570 
571   // If there are no calls, MachineRegisterInfo can tell us the used register
572   // count easily.
573   // A tail call isn't considered a call for MachineFrameInfo's purposes.
574   if (!FrameInfo.hasCalls() && !FrameInfo.hasTailCall()) {
575     MCPhysReg HighestVGPRReg = AMDGPU::NoRegister;
576     for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) {
577       if (MRI.isPhysRegUsed(Reg)) {
578         HighestVGPRReg = Reg;
579         break;
580       }
581     }
582 
583     MCPhysReg HighestSGPRReg = AMDGPU::NoRegister;
584     for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) {
585       if (MRI.isPhysRegUsed(Reg)) {
586         HighestSGPRReg = Reg;
587         break;
588       }
589     }
590 
591     // We found the maximum register index. They start at 0, so add one to get the
592     // number of registers.
593     Info.NumVGPR = HighestVGPRReg == AMDGPU::NoRegister ? 0 :
594       TRI.getHWRegIndex(HighestVGPRReg) + 1;
595     Info.NumExplicitSGPR = HighestSGPRReg == AMDGPU::NoRegister ? 0 :
596       TRI.getHWRegIndex(HighestSGPRReg) + 1;
597 
598     return Info;
599   }
600 
601   int32_t MaxVGPR = -1;
602   int32_t MaxSGPR = -1;
603   uint32_t CalleeFrameSize = 0;
604 
605   for (const MachineBasicBlock &MBB : MF) {
606     for (const MachineInstr &MI : MBB) {
607       // TODO: Check regmasks? Do they occur anywhere except calls?
608       for (const MachineOperand &MO : MI.operands()) {
609         unsigned Width = 0;
610         bool IsSGPR = false;
611 
612         if (!MO.isReg())
613           continue;
614 
615         unsigned Reg = MO.getReg();
616         switch (Reg) {
617         case AMDGPU::EXEC:
618         case AMDGPU::EXEC_LO:
619         case AMDGPU::EXEC_HI:
620         case AMDGPU::SCC:
621         case AMDGPU::M0:
622         case AMDGPU::SRC_SHARED_BASE:
623         case AMDGPU::SRC_SHARED_LIMIT:
624         case AMDGPU::SRC_PRIVATE_BASE:
625         case AMDGPU::SRC_PRIVATE_LIMIT:
626           continue;
627 
628         case AMDGPU::NoRegister:
629           assert(MI.isDebugValue());
630           continue;
631 
632         case AMDGPU::VCC:
633         case AMDGPU::VCC_LO:
634         case AMDGPU::VCC_HI:
635           Info.UsesVCC = true;
636           continue;
637 
638         case AMDGPU::FLAT_SCR:
639         case AMDGPU::FLAT_SCR_LO:
640         case AMDGPU::FLAT_SCR_HI:
641           continue;
642 
643         case AMDGPU::TBA:
644         case AMDGPU::TBA_LO:
645         case AMDGPU::TBA_HI:
646         case AMDGPU::TMA:
647         case AMDGPU::TMA_LO:
648         case AMDGPU::TMA_HI:
649           llvm_unreachable("trap handler registers should not be used");
650 
651         default:
652           break;
653         }
654 
655         if (AMDGPU::SReg_32RegClass.contains(Reg)) {
656           assert(!AMDGPU::TTMP_32RegClass.contains(Reg) &&
657                  "trap handler registers should not be used");
658           IsSGPR = true;
659           Width = 1;
660         } else if (AMDGPU::VGPR_32RegClass.contains(Reg)) {
661           IsSGPR = false;
662           Width = 1;
663         } else if (AMDGPU::SReg_64RegClass.contains(Reg)) {
664           assert(!AMDGPU::TTMP_64RegClass.contains(Reg) &&
665                  "trap handler registers should not be used");
666           IsSGPR = true;
667           Width = 2;
668         } else if (AMDGPU::VReg_64RegClass.contains(Reg)) {
669           IsSGPR = false;
670           Width = 2;
671         } else if (AMDGPU::VReg_96RegClass.contains(Reg)) {
672           IsSGPR = false;
673           Width = 3;
674         } else if (AMDGPU::SReg_128RegClass.contains(Reg)) {
675           IsSGPR = true;
676           Width = 4;
677         } else if (AMDGPU::VReg_128RegClass.contains(Reg)) {
678           IsSGPR = false;
679           Width = 4;
680         } else if (AMDGPU::SReg_256RegClass.contains(Reg)) {
681           IsSGPR = true;
682           Width = 8;
683         } else if (AMDGPU::VReg_256RegClass.contains(Reg)) {
684           IsSGPR = false;
685           Width = 8;
686         } else if (AMDGPU::SReg_512RegClass.contains(Reg)) {
687           IsSGPR = true;
688           Width = 16;
689         } else if (AMDGPU::VReg_512RegClass.contains(Reg)) {
690           IsSGPR = false;
691           Width = 16;
692         } else {
693           llvm_unreachable("Unknown register class");
694         }
695         unsigned HWReg = TRI.getHWRegIndex(Reg);
696         int MaxUsed = HWReg + Width - 1;
697         if (IsSGPR) {
698           MaxSGPR = MaxUsed > MaxSGPR ? MaxUsed : MaxSGPR;
699         } else {
700           MaxVGPR = MaxUsed > MaxVGPR ? MaxUsed : MaxVGPR;
701         }
702       }
703 
704       if (MI.isCall()) {
705         // Pseudo used just to encode the underlying global. Is there a better
706         // way to track this?
707 
708         const MachineOperand *CalleeOp
709           = TII->getNamedOperand(MI, AMDGPU::OpName::callee);
710         const Function *Callee = cast<Function>(CalleeOp->getGlobal());
711         if (Callee->isDeclaration()) {
712           // If this is a call to an external function, we can't do much. Make
713           // conservative guesses.
714 
715           // 48 SGPRs - vcc, - flat_scr, -xnack
716           int MaxSGPRGuess = 47 - getNumExtraSGPRs(ST, true,
717                                                    ST.hasFlatAddressSpace());
718           MaxSGPR = std::max(MaxSGPR, MaxSGPRGuess);
719           MaxVGPR = std::max(MaxVGPR, 23);
720 
721           CalleeFrameSize = std::max(CalleeFrameSize, 16384u);
722           Info.UsesVCC = true;
723           Info.UsesFlatScratch = ST.hasFlatAddressSpace();
724           Info.HasDynamicallySizedStack = true;
725         } else {
726           // We force CodeGen to run in SCC order, so the callee's register
727           // usage etc. should be the cumulative usage of all callees.
728           auto I = CallGraphResourceInfo.find(Callee);
729           assert(I != CallGraphResourceInfo.end() &&
730                  "callee should have been handled before caller");
731 
732           MaxSGPR = std::max(I->second.NumExplicitSGPR - 1, MaxSGPR);
733           MaxVGPR = std::max(I->second.NumVGPR - 1, MaxVGPR);
734           CalleeFrameSize
735             = std::max(I->second.PrivateSegmentSize, CalleeFrameSize);
736           Info.UsesVCC |= I->second.UsesVCC;
737           Info.UsesFlatScratch |= I->second.UsesFlatScratch;
738           Info.HasDynamicallySizedStack |= I->second.HasDynamicallySizedStack;
739           Info.HasRecursion |= I->second.HasRecursion;
740         }
741 
742         if (!Callee->doesNotRecurse())
743           Info.HasRecursion = true;
744       }
745     }
746   }
747 
748   Info.NumExplicitSGPR = MaxSGPR + 1;
749   Info.NumVGPR = MaxVGPR + 1;
750   Info.PrivateSegmentSize += CalleeFrameSize;
751 
752   return Info;
753 }
754 
755 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
756                                         const MachineFunction &MF) {
757   SIFunctionResourceInfo Info = analyzeResourceUsage(MF);
758 
759   ProgInfo.NumVGPR = Info.NumVGPR;
760   ProgInfo.NumSGPR = Info.NumExplicitSGPR;
761   ProgInfo.ScratchSize = Info.PrivateSegmentSize;
762   ProgInfo.VCCUsed = Info.UsesVCC;
763   ProgInfo.FlatUsed = Info.UsesFlatScratch;
764   ProgInfo.DynamicCallStack = Info.HasDynamicallySizedStack || Info.HasRecursion;
765 
766   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
767   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
768   const SIInstrInfo *TII = STM.getInstrInfo();
769   const SIRegisterInfo *RI = &TII->getRegisterInfo();
770 
771   unsigned ExtraSGPRs = getNumExtraSGPRs(STM,
772                                          ProgInfo.VCCUsed,
773                                          ProgInfo.FlatUsed);
774   unsigned ExtraVGPRs = STM.getReservedNumVGPRs(MF);
775 
776   // Check the addressable register limit before we add ExtraSGPRs.
777   if (STM.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
778       !STM.hasSGPRInitBug()) {
779     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
780     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
781       // This can happen due to a compiler bug or when using inline asm.
782       LLVMContext &Ctx = MF.getFunction()->getContext();
783       DiagnosticInfoResourceLimit Diag(*MF.getFunction(),
784                                        "addressable scalar registers",
785                                        ProgInfo.NumSGPR, DS_Error,
786                                        DK_ResourceLimit,
787                                        MaxAddressableNumSGPRs);
788       Ctx.diagnose(Diag);
789       ProgInfo.NumSGPR = MaxAddressableNumSGPRs - 1;
790     }
791   }
792 
793   // Account for extra SGPRs and VGPRs reserved for debugger use.
794   ProgInfo.NumSGPR += ExtraSGPRs;
795   ProgInfo.NumVGPR += ExtraVGPRs;
796 
797   // Adjust number of registers used to meet default/requested minimum/maximum
798   // number of waves per execution unit request.
799   ProgInfo.NumSGPRsForWavesPerEU = std::max(
800     std::max(ProgInfo.NumSGPR, 1u), STM.getMinNumSGPRs(MFI->getMaxWavesPerEU()));
801   ProgInfo.NumVGPRsForWavesPerEU = std::max(
802     std::max(ProgInfo.NumVGPR, 1u), STM.getMinNumVGPRs(MFI->getMaxWavesPerEU()));
803 
804   if (STM.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ||
805       STM.hasSGPRInitBug()) {
806     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
807     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
808       // This can happen due to a compiler bug or when using inline asm to use
809       // the registers which are usually reserved for vcc etc.
810       LLVMContext &Ctx = MF.getFunction()->getContext();
811       DiagnosticInfoResourceLimit Diag(*MF.getFunction(),
812                                        "scalar registers",
813                                        ProgInfo.NumSGPR, DS_Error,
814                                        DK_ResourceLimit,
815                                        MaxAddressableNumSGPRs);
816       Ctx.diagnose(Diag);
817       ProgInfo.NumSGPR = MaxAddressableNumSGPRs;
818       ProgInfo.NumSGPRsForWavesPerEU = MaxAddressableNumSGPRs;
819     }
820   }
821 
822   if (STM.hasSGPRInitBug()) {
823     ProgInfo.NumSGPR =
824         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
825     ProgInfo.NumSGPRsForWavesPerEU =
826         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
827   }
828 
829   if (MFI->getNumUserSGPRs() > STM.getMaxNumUserSGPRs()) {
830     LLVMContext &Ctx = MF.getFunction()->getContext();
831     DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "user SGPRs",
832                                      MFI->getNumUserSGPRs(), DS_Error);
833     Ctx.diagnose(Diag);
834   }
835 
836   if (MFI->getLDSSize() > static_cast<unsigned>(STM.getLocalMemorySize())) {
837     LLVMContext &Ctx = MF.getFunction()->getContext();
838     DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "local memory",
839                                      MFI->getLDSSize(), DS_Error);
840     Ctx.diagnose(Diag);
841   }
842 
843   // SGPRBlocks is actual number of SGPR blocks minus 1.
844   ProgInfo.SGPRBlocks = alignTo(ProgInfo.NumSGPRsForWavesPerEU,
845                                 STM.getSGPREncodingGranule());
846   ProgInfo.SGPRBlocks = ProgInfo.SGPRBlocks / STM.getSGPREncodingGranule() - 1;
847 
848   // VGPRBlocks is actual number of VGPR blocks minus 1.
849   ProgInfo.VGPRBlocks = alignTo(ProgInfo.NumVGPRsForWavesPerEU,
850                                 STM.getVGPREncodingGranule());
851   ProgInfo.VGPRBlocks = ProgInfo.VGPRBlocks / STM.getVGPREncodingGranule() - 1;
852 
853   // Record first reserved VGPR and number of reserved VGPRs.
854   ProgInfo.ReservedVGPRFirst = STM.debuggerReserveRegs() ? ProgInfo.NumVGPR : 0;
855   ProgInfo.ReservedVGPRCount = STM.getReservedNumVGPRs(MF);
856 
857   // Update DebuggerWavefrontPrivateSegmentOffsetSGPR and
858   // DebuggerPrivateSegmentBufferSGPR fields if "amdgpu-debugger-emit-prologue"
859   // attribute was requested.
860   if (STM.debuggerEmitPrologue()) {
861     ProgInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR =
862       RI->getHWRegIndex(MFI->getScratchWaveOffsetReg());
863     ProgInfo.DebuggerPrivateSegmentBufferSGPR =
864       RI->getHWRegIndex(MFI->getScratchRSrcReg());
865   }
866 
867   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
868   // register.
869   ProgInfo.FloatMode = getFPMode(MF);
870 
871   ProgInfo.IEEEMode = STM.enableIEEEBit(MF);
872 
873   // Make clamp modifier on NaN input returns 0.
874   ProgInfo.DX10Clamp = STM.enableDX10Clamp();
875 
876   unsigned LDSAlignShift;
877   if (STM.getGeneration() < SISubtarget::SEA_ISLANDS) {
878     // LDS is allocated in 64 dword blocks.
879     LDSAlignShift = 8;
880   } else {
881     // LDS is allocated in 128 dword blocks.
882     LDSAlignShift = 9;
883   }
884 
885   unsigned LDSSpillSize =
886     MFI->getLDSWaveSpillSize() * MFI->getMaxFlatWorkGroupSize();
887 
888   ProgInfo.LDSSize = MFI->getLDSSize() + LDSSpillSize;
889   ProgInfo.LDSBlocks =
890       alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
891 
892   // Scratch is allocated in 256 dword blocks.
893   unsigned ScratchAlignShift = 10;
894   // We need to program the hardware with the amount of scratch memory that
895   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
896   // scratch memory used per thread.
897   ProgInfo.ScratchBlocks =
898       alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
899               1ULL << ScratchAlignShift) >>
900       ScratchAlignShift;
901 
902   ProgInfo.ComputePGMRSrc1 =
903       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
904       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
905       S_00B848_PRIORITY(ProgInfo.Priority) |
906       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
907       S_00B848_PRIV(ProgInfo.Priv) |
908       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
909       S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
910       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
911 
912   // 0 = X, 1 = XY, 2 = XYZ
913   unsigned TIDIGCompCnt = 0;
914   if (MFI->hasWorkItemIDZ())
915     TIDIGCompCnt = 2;
916   else if (MFI->hasWorkItemIDY())
917     TIDIGCompCnt = 1;
918 
919   ProgInfo.ComputePGMRSrc2 =
920       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
921       S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
922       S_00B84C_TRAP_HANDLER(STM.isTrapHandlerEnabled()) |
923       S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
924       S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
925       S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
926       S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
927       S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
928       S_00B84C_EXCP_EN_MSB(0) |
929       // For AMDHSA, LDS_SIZE must be zero, as it is populated by the CP.
930       S_00B84C_LDS_SIZE(STM.isAmdHsaOS() ? 0 : ProgInfo.LDSBlocks) |
931       S_00B84C_EXCP_EN(0);
932 }
933 
934 static unsigned getRsrcReg(CallingConv::ID CallConv) {
935   switch (CallConv) {
936   default: LLVM_FALLTHROUGH;
937   case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
938   case CallingConv::AMDGPU_LS: return R_00B528_SPI_SHADER_PGM_RSRC1_LS;
939   case CallingConv::AMDGPU_HS: return R_00B428_SPI_SHADER_PGM_RSRC1_HS;
940   case CallingConv::AMDGPU_ES: return R_00B328_SPI_SHADER_PGM_RSRC1_ES;
941   case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
942   case CallingConv::AMDGPU_VS: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
943   case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
944   }
945 }
946 
947 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
948                                          const SIProgramInfo &CurrentProgramInfo) {
949   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
950   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
951   unsigned RsrcReg = getRsrcReg(MF.getFunction()->getCallingConv());
952 
953   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
954     OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
955 
956     OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc1, 4);
957 
958     OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
959     OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc2, 4);
960 
961     OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
962     OutStreamer->EmitIntValue(S_00B860_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
963 
964     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
965     // 0" comment but I don't see a corresponding field in the register spec.
966   } else {
967     OutStreamer->EmitIntValue(RsrcReg, 4);
968     OutStreamer->EmitIntValue(S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
969                               S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks), 4);
970     unsigned Rsrc2Val = 0;
971     if (STM.isVGPRSpillingEnabled(*MF.getFunction())) {
972       OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
973       OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
974       if (TM.getTargetTriple().getOS() == Triple::AMDPAL)
975         Rsrc2Val = S_00B84C_SCRATCH_EN(CurrentProgramInfo.ScratchBlocks > 0);
976     }
977     if (MF.getFunction()->getCallingConv() == CallingConv::AMDGPU_PS) {
978       OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
979       OutStreamer->EmitIntValue(MFI->getPSInputEnable(), 4);
980       OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
981       OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4);
982       Rsrc2Val |= S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks);
983     }
984     if (Rsrc2Val) {
985       OutStreamer->EmitIntValue(RsrcReg + 4 /*rsrc2*/, 4);
986       OutStreamer->EmitIntValue(Rsrc2Val, 4);
987     }
988   }
989 
990   OutStreamer->EmitIntValue(R_SPILLED_SGPRS, 4);
991   OutStreamer->EmitIntValue(MFI->getNumSpilledSGPRs(), 4);
992   OutStreamer->EmitIntValue(R_SPILLED_VGPRS, 4);
993   OutStreamer->EmitIntValue(MFI->getNumSpilledVGPRs(), 4);
994 }
995 
996 // This is the equivalent of EmitProgramInfoSI above, but for when the OS type
997 // is AMDPAL.  It stores each compute/SPI register setting and other PAL
998 // metadata items into the PALMetadataMap, combining with any provided by the
999 // frontend as LLVM metadata. Once all functions are written, PALMetadataMap is
1000 // then written as a single block in the .note section.
1001 void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
1002        const SIProgramInfo &CurrentProgramInfo) {
1003   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1004   // Given the calling convention, calculate the register number for rsrc1. In
1005   // principle the register number could change in future hardware, but we know
1006   // it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so
1007   // we can use the same fixed value that .AMDGPU.config has for Mesa. Note
1008   // that we use a register number rather than a byte offset, so we need to
1009   // divide by 4.
1010   unsigned Rsrc1Reg = getRsrcReg(MF.getFunction()->getCallingConv()) / 4;
1011   unsigned Rsrc2Reg = Rsrc1Reg + 1;
1012   // Also calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used
1013   // with a constant offset to access any non-register shader-specific PAL
1014   // metadata key.
1015   unsigned ScratchSizeKey = PALMD::Key::CS_SCRATCH_SIZE;
1016   switch (MF.getFunction()->getCallingConv()) {
1017     case CallingConv::AMDGPU_PS:
1018       ScratchSizeKey = PALMD::Key::PS_SCRATCH_SIZE;
1019       break;
1020     case CallingConv::AMDGPU_VS:
1021       ScratchSizeKey = PALMD::Key::VS_SCRATCH_SIZE;
1022       break;
1023     case CallingConv::AMDGPU_GS:
1024       ScratchSizeKey = PALMD::Key::GS_SCRATCH_SIZE;
1025       break;
1026     case CallingConv::AMDGPU_ES:
1027       ScratchSizeKey = PALMD::Key::ES_SCRATCH_SIZE;
1028       break;
1029     case CallingConv::AMDGPU_HS:
1030       ScratchSizeKey = PALMD::Key::HS_SCRATCH_SIZE;
1031       break;
1032     case CallingConv::AMDGPU_LS:
1033       ScratchSizeKey = PALMD::Key::LS_SCRATCH_SIZE;
1034       break;
1035   }
1036   unsigned NumUsedVgprsKey = ScratchSizeKey +
1037       PALMD::Key::VS_NUM_USED_VGPRS - PALMD::Key::VS_SCRATCH_SIZE;
1038   unsigned NumUsedSgprsKey = ScratchSizeKey +
1039       PALMD::Key::VS_NUM_USED_SGPRS - PALMD::Key::VS_SCRATCH_SIZE;
1040   PALMetadataMap[NumUsedVgprsKey] = CurrentProgramInfo.NumVGPRsForWavesPerEU;
1041   PALMetadataMap[NumUsedSgprsKey] = CurrentProgramInfo.NumSGPRsForWavesPerEU;
1042   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
1043     PALMetadataMap[Rsrc1Reg] |= CurrentProgramInfo.ComputePGMRSrc1;
1044     PALMetadataMap[Rsrc2Reg] |= CurrentProgramInfo.ComputePGMRSrc2;
1045     // ScratchSize is in bytes, 16 aligned.
1046     PALMetadataMap[ScratchSizeKey] |=
1047         alignTo(CurrentProgramInfo.ScratchSize, 16);
1048   } else {
1049     PALMetadataMap[Rsrc1Reg] |= S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
1050         S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks);
1051     if (CurrentProgramInfo.ScratchBlocks > 0)
1052       PALMetadataMap[Rsrc2Reg] |= S_00B84C_SCRATCH_EN(1);
1053     // ScratchSize is in bytes, 16 aligned.
1054     PALMetadataMap[ScratchSizeKey] |=
1055         alignTo(CurrentProgramInfo.ScratchSize, 16);
1056   }
1057   if (MF.getFunction()->getCallingConv() == CallingConv::AMDGPU_PS) {
1058     PALMetadataMap[Rsrc2Reg] |=
1059         S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks);
1060     PALMetadataMap[R_0286CC_SPI_PS_INPUT_ENA / 4] |= MFI->getPSInputEnable();
1061     PALMetadataMap[R_0286D0_SPI_PS_INPUT_ADDR / 4] |= MFI->getPSInputAddr();
1062   }
1063 }
1064 
1065 // This is supposed to be log2(Size)
1066 static amd_element_byte_size_t getElementByteSizeValue(unsigned Size) {
1067   switch (Size) {
1068   case 4:
1069     return AMD_ELEMENT_4_BYTES;
1070   case 8:
1071     return AMD_ELEMENT_8_BYTES;
1072   case 16:
1073     return AMD_ELEMENT_16_BYTES;
1074   default:
1075     llvm_unreachable("invalid private_element_size");
1076   }
1077 }
1078 
1079 void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out,
1080                                         const SIProgramInfo &CurrentProgramInfo,
1081                                         const MachineFunction &MF) const {
1082   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1083   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
1084 
1085   AMDGPU::initDefaultAMDKernelCodeT(Out, STM.getFeatureBits());
1086 
1087   Out.compute_pgm_resource_registers =
1088       CurrentProgramInfo.ComputePGMRSrc1 |
1089       (CurrentProgramInfo.ComputePGMRSrc2 << 32);
1090   Out.code_properties = AMD_CODE_PROPERTY_IS_PTR64;
1091 
1092   if (CurrentProgramInfo.DynamicCallStack)
1093     Out.code_properties |= AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK;
1094 
1095   AMD_HSA_BITS_SET(Out.code_properties,
1096                    AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE,
1097                    getElementByteSizeValue(STM.getMaxPrivateElementSize()));
1098 
1099   if (MFI->hasPrivateSegmentBuffer()) {
1100     Out.code_properties |=
1101       AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
1102   }
1103 
1104   if (MFI->hasDispatchPtr())
1105     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
1106 
1107   if (MFI->hasQueuePtr())
1108     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
1109 
1110   if (MFI->hasKernargSegmentPtr())
1111     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
1112 
1113   if (MFI->hasDispatchID())
1114     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
1115 
1116   if (MFI->hasFlatScratchInit())
1117     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
1118 
1119   if (MFI->hasGridWorkgroupCountX()) {
1120     Out.code_properties |=
1121       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X;
1122   }
1123 
1124   if (MFI->hasGridWorkgroupCountY()) {
1125     Out.code_properties |=
1126       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y;
1127   }
1128 
1129   if (MFI->hasGridWorkgroupCountZ()) {
1130     Out.code_properties |=
1131       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z;
1132   }
1133 
1134   if (MFI->hasDispatchPtr())
1135     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
1136 
1137   if (STM.debuggerSupported())
1138     Out.code_properties |= AMD_CODE_PROPERTY_IS_DEBUG_SUPPORTED;
1139 
1140   if (STM.isXNACKEnabled())
1141     Out.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED;
1142 
1143   // FIXME: Should use getKernArgSize
1144   Out.kernarg_segment_byte_size =
1145     STM.getKernArgSegmentSize(MF, MFI->getABIArgOffset());
1146   Out.wavefront_sgpr_count = CurrentProgramInfo.NumSGPR;
1147   Out.workitem_vgpr_count = CurrentProgramInfo.NumVGPR;
1148   Out.workitem_private_segment_byte_size = CurrentProgramInfo.ScratchSize;
1149   Out.workgroup_group_segment_byte_size = CurrentProgramInfo.LDSSize;
1150   Out.reserved_vgpr_first = CurrentProgramInfo.ReservedVGPRFirst;
1151   Out.reserved_vgpr_count = CurrentProgramInfo.ReservedVGPRCount;
1152 
1153   // These alignment values are specified in powers of two, so alignment =
1154   // 2^n.  The minimum alignment is 2^4 = 16.
1155   Out.kernarg_segment_alignment = std::max((size_t)4,
1156       countTrailingZeros(MFI->getMaxKernArgAlign()));
1157 
1158   if (STM.debuggerEmitPrologue()) {
1159     Out.debug_wavefront_private_segment_offset_sgpr =
1160       CurrentProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR;
1161     Out.debug_private_segment_buffer_sgpr =
1162       CurrentProgramInfo.DebuggerPrivateSegmentBufferSGPR;
1163   }
1164 }
1165 
1166 AMDGPU::HSAMD::Kernel::CodeProps::Metadata AMDGPUAsmPrinter::getHSACodeProps(
1167     const MachineFunction &MF,
1168     const SIProgramInfo &ProgramInfo) const {
1169   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
1170   const SIMachineFunctionInfo &MFI = *MF.getInfo<SIMachineFunctionInfo>();
1171   HSAMD::Kernel::CodeProps::Metadata HSACodeProps;
1172 
1173   HSACodeProps.mKernargSegmentSize =
1174       STM.getKernArgSegmentSize(MF, MFI.getABIArgOffset());
1175   HSACodeProps.mGroupSegmentFixedSize = ProgramInfo.LDSSize;
1176   HSACodeProps.mPrivateSegmentFixedSize = ProgramInfo.ScratchSize;
1177   HSACodeProps.mKernargSegmentAlign =
1178       std::max(uint32_t(4), MFI.getMaxKernArgAlign());
1179   HSACodeProps.mWavefrontSize = STM.getWavefrontSize();
1180   HSACodeProps.mNumSGPRs = CurrentProgramInfo.NumSGPR;
1181   HSACodeProps.mNumVGPRs = CurrentProgramInfo.NumVGPR;
1182   HSACodeProps.mMaxFlatWorkGroupSize = MFI.getMaxFlatWorkGroupSize();
1183   HSACodeProps.mIsDynamicCallStack = ProgramInfo.DynamicCallStack;
1184   HSACodeProps.mIsXNACKEnabled = STM.isXNACKEnabled();
1185 
1186   return HSACodeProps;
1187 }
1188 
1189 AMDGPU::HSAMD::Kernel::DebugProps::Metadata AMDGPUAsmPrinter::getHSADebugProps(
1190     const MachineFunction &MF,
1191     const SIProgramInfo &ProgramInfo) const {
1192   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
1193   HSAMD::Kernel::DebugProps::Metadata HSADebugProps;
1194 
1195   if (!STM.debuggerSupported())
1196     return HSADebugProps;
1197 
1198   HSADebugProps.mDebuggerABIVersion.push_back(1);
1199   HSADebugProps.mDebuggerABIVersion.push_back(0);
1200   HSADebugProps.mReservedNumVGPRs = ProgramInfo.ReservedVGPRCount;
1201   HSADebugProps.mReservedFirstVGPR = ProgramInfo.ReservedVGPRFirst;
1202 
1203   if (STM.debuggerEmitPrologue()) {
1204     HSADebugProps.mPrivateSegmentBufferSGPR =
1205         ProgramInfo.DebuggerPrivateSegmentBufferSGPR;
1206     HSADebugProps.mWavefrontPrivateSegmentOffsetSGPR =
1207         ProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR;
1208   }
1209 
1210   return HSADebugProps;
1211 }
1212 
1213 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
1214                                        unsigned AsmVariant,
1215                                        const char *ExtraCode, raw_ostream &O) {
1216   // First try the generic code, which knows about modifiers like 'c' and 'n'.
1217   if (!AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O))
1218     return false;
1219 
1220   if (ExtraCode && ExtraCode[0]) {
1221     if (ExtraCode[1] != 0)
1222       return true; // Unknown modifier.
1223 
1224     switch (ExtraCode[0]) {
1225     case 'r':
1226       break;
1227     default:
1228       return true;
1229     }
1230   }
1231 
1232   // TODO: Should be able to support other operand types like globals.
1233   const MachineOperand &MO = MI->getOperand(OpNo);
1234   if (MO.isReg()) {
1235     AMDGPUInstPrinter::printRegOperand(MO.getReg(), O,
1236                                        *MF->getSubtarget().getRegisterInfo());
1237     return false;
1238   }
1239 
1240   return true;
1241 }
1242