1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU assembly printer --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 ///
11 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
12 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
13 /// an MCObjectStreamer it outputs binary code.
14 //
15 //===----------------------------------------------------------------------===//
16 //
17 
18 #include "AMDGPUAsmPrinter.h"
19 #include "AMDGPU.h"
20 #include "AMDGPUHSAMetadataStreamer.h"
21 #include "AMDKernelCodeT.h"
22 #include "GCNSubtarget.h"
23 #include "MCTargetDesc/AMDGPUInstPrinter.h"
24 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
25 #include "R600AsmPrinter.h"
26 #include "SIMachineFunctionInfo.h"
27 #include "TargetInfo/AMDGPUTargetInfo.h"
28 #include "Utils/AMDGPUBaseInfo.h"
29 #include "llvm/IR/DiagnosticInfo.h"
30 #include "llvm/MC/MCAssembler.h"
31 #include "llvm/MC/MCContext.h"
32 #include "llvm/MC/MCSectionELF.h"
33 #include "llvm/MC/MCStreamer.h"
34 #include "llvm/Support/AMDHSAKernelDescriptor.h"
35 #include "llvm/Support/TargetRegistry.h"
36 #include "llvm/Target/TargetLoweringObjectFile.h"
37 #include "llvm/Target/TargetMachine.h"
38 
39 using namespace llvm;
40 using namespace llvm::AMDGPU;
41 
42 // We need to tell the runtime some amount ahead of time if we don't know the
43 // true stack size. Assume a smaller number if this is only due to dynamic /
44 // non-entry block allocas.
45 static cl::opt<uint32_t> AssumedStackSizeForExternalCall(
46   "amdgpu-assume-external-call-stack-size",
47   cl::desc("Assumed stack use of any external call (in bytes)"),
48   cl::Hidden,
49   cl::init(16384));
50 
51 static cl::opt<uint32_t> AssumedStackSizeForDynamicSizeObjects(
52   "amdgpu-assume-dynamic-stack-object-size",
53   cl::desc("Assumed extra stack use if there are any "
54            "variable sized objects (in bytes)"),
55   cl::Hidden,
56   cl::init(4096));
57 
58 // This should get the default rounding mode from the kernel. We just set the
59 // default here, but this could change if the OpenCL rounding mode pragmas are
60 // used.
61 //
62 // The denormal mode here should match what is reported by the OpenCL runtime
63 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
64 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
65 //
66 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
67 // precision, and leaves single precision to flush all and does not report
68 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
69 // CL_FP_DENORM for both.
70 //
71 // FIXME: It seems some instructions do not support single precision denormals
72 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
73 // and sin_f32, cos_f32 on most parts).
74 
75 // We want to use these instructions, and using fp32 denormals also causes
76 // instructions to run at the double precision rate for the device so it's
77 // probably best to just report no single precision denormals.
78 static uint32_t getFPMode(AMDGPU::SIModeRegisterDefaults Mode) {
79   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
80          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
81          FP_DENORM_MODE_SP(Mode.fpDenormModeSPValue()) |
82          FP_DENORM_MODE_DP(Mode.fpDenormModeDPValue());
83 }
84 
85 static AsmPrinter *
86 createAMDGPUAsmPrinterPass(TargetMachine &tm,
87                            std::unique_ptr<MCStreamer> &&Streamer) {
88   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
89 }
90 
91 extern "C" void LLVM_EXTERNAL_VISIBILITY LLVMInitializeAMDGPUAsmPrinter() {
92   TargetRegistry::RegisterAsmPrinter(getTheAMDGPUTarget(),
93                                      llvm::createR600AsmPrinterPass);
94   TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(),
95                                      createAMDGPUAsmPrinterPass);
96 }
97 
98 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
99                                    std::unique_ptr<MCStreamer> Streamer)
100     : AsmPrinter(TM, std::move(Streamer)) {
101   if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
102     if (isHsaAbiVersion2(getGlobalSTI())) {
103       HSAMetadataStream.reset(new HSAMD::MetadataStreamerV2());
104     } else if (isHsaAbiVersion3(getGlobalSTI())) {
105       HSAMetadataStream.reset(new HSAMD::MetadataStreamerV3());
106     } else {
107       HSAMetadataStream.reset(new HSAMD::MetadataStreamerV4());
108     }
109   }
110 }
111 
112 StringRef AMDGPUAsmPrinter::getPassName() const {
113   return "AMDGPU Assembly Printer";
114 }
115 
116 const MCSubtargetInfo *AMDGPUAsmPrinter::getGlobalSTI() const {
117   return TM.getMCSubtargetInfo();
118 }
119 
120 AMDGPUTargetStreamer* AMDGPUAsmPrinter::getTargetStreamer() const {
121   if (!OutStreamer)
122     return nullptr;
123   return static_cast<AMDGPUTargetStreamer*>(OutStreamer->getTargetStreamer());
124 }
125 
126 void AMDGPUAsmPrinter::emitStartOfAsmFile(Module &M) {
127   // TODO: Which one is called first, emitStartOfAsmFile or
128   // emitFunctionBodyStart?
129   if (getTargetStreamer() && !getTargetStreamer()->getTargetID())
130     initializeTargetID(M);
131 
132   if (TM.getTargetTriple().getOS() != Triple::AMDHSA &&
133       TM.getTargetTriple().getOS() != Triple::AMDPAL)
134     return;
135 
136   if (isHsaAbiVersion3Or4(getGlobalSTI()))
137     getTargetStreamer()->EmitDirectiveAMDGCNTarget();
138 
139   if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
140     HSAMetadataStream->begin(M, *getTargetStreamer()->getTargetID());
141 
142   if (TM.getTargetTriple().getOS() == Triple::AMDPAL)
143     getTargetStreamer()->getPALMetadata()->readFromIR(M);
144 
145   if (isHsaAbiVersion3Or4(getGlobalSTI()))
146     return;
147 
148   // HSA emits NT_AMD_HSA_CODE_OBJECT_VERSION for code objects v2.
149   if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
150     getTargetStreamer()->EmitDirectiveHSACodeObjectVersion(2, 1);
151 
152   // HSA and PAL emit NT_AMD_HSA_ISA_VERSION for code objects v2.
153   IsaVersion Version = getIsaVersion(getGlobalSTI()->getCPU());
154   getTargetStreamer()->EmitDirectiveHSACodeObjectISAV2(
155       Version.Major, Version.Minor, Version.Stepping, "AMD", "AMDGPU");
156 }
157 
158 void AMDGPUAsmPrinter::emitEndOfAsmFile(Module &M) {
159   // Following code requires TargetStreamer to be present.
160   if (!getTargetStreamer())
161     return;
162 
163   if (TM.getTargetTriple().getOS() != Triple::AMDHSA ||
164       isHsaAbiVersion2(getGlobalSTI()))
165     getTargetStreamer()->EmitISAVersion();
166 
167   // Emit HSA Metadata (NT_AMD_AMDGPU_HSA_METADATA).
168   // Emit HSA Metadata (NT_AMD_HSA_METADATA).
169   if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
170     HSAMetadataStream->end();
171     bool Success = HSAMetadataStream->emitTo(*getTargetStreamer());
172     (void)Success;
173     assert(Success && "Malformed HSA Metadata");
174   }
175 }
176 
177 bool AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough(
178   const MachineBasicBlock *MBB) const {
179   if (!AsmPrinter::isBlockOnlyReachableByFallthrough(MBB))
180     return false;
181 
182   if (MBB->empty())
183     return true;
184 
185   // If this is a block implementing a long branch, an expression relative to
186   // the start of the block is needed.  to the start of the block.
187   // XXX - Is there a smarter way to check this?
188   return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
189 }
190 
191 void AMDGPUAsmPrinter::emitFunctionBodyStart() {
192   const SIMachineFunctionInfo &MFI = *MF->getInfo<SIMachineFunctionInfo>();
193   const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
194   const Function &F = MF->getFunction();
195 
196   // TODO: Which one is called first, emitStartOfAsmFile or
197   // emitFunctionBodyStart?
198   if (getTargetStreamer() && !getTargetStreamer()->getTargetID())
199     initializeTargetID(*F.getParent());
200 
201   const auto &FunctionTargetID = STM.getTargetID();
202   // Make sure function's xnack settings are compatible with module's
203   // xnack settings.
204   if (FunctionTargetID.isXnackSupported() &&
205       FunctionTargetID.getXnackSetting() != IsaInfo::TargetIDSetting::Any &&
206       FunctionTargetID.getXnackSetting() != getTargetStreamer()->getTargetID()->getXnackSetting()) {
207     OutContext.reportError({}, "xnack setting of '" + Twine(MF->getName()) +
208                            "' function does not match module xnack setting");
209     return;
210   }
211   // Make sure function's sramecc settings are compatible with module's
212   // sramecc settings.
213   if (FunctionTargetID.isSramEccSupported() &&
214       FunctionTargetID.getSramEccSetting() != IsaInfo::TargetIDSetting::Any &&
215       FunctionTargetID.getSramEccSetting() != getTargetStreamer()->getTargetID()->getSramEccSetting()) {
216     OutContext.reportError({}, "sramecc setting of '" + Twine(MF->getName()) +
217                            "' function does not match module sramecc setting");
218     return;
219   }
220 
221   if (!MFI.isEntryFunction())
222     return;
223 
224   if ((STM.isMesaKernel(F) || isHsaAbiVersion2(getGlobalSTI())) &&
225       (F.getCallingConv() == CallingConv::AMDGPU_KERNEL ||
226        F.getCallingConv() == CallingConv::SPIR_KERNEL)) {
227     amd_kernel_code_t KernelCode;
228     getAmdKernelCode(KernelCode, CurrentProgramInfo, *MF);
229     getTargetStreamer()->EmitAMDKernelCodeT(KernelCode);
230   }
231 
232   if (STM.isAmdHsaOS())
233     HSAMetadataStream->emitKernel(*MF, CurrentProgramInfo);
234 }
235 
236 void AMDGPUAsmPrinter::emitFunctionBodyEnd() {
237   const SIMachineFunctionInfo &MFI = *MF->getInfo<SIMachineFunctionInfo>();
238   if (!MFI.isEntryFunction())
239     return;
240 
241   if (TM.getTargetTriple().getOS() != Triple::AMDHSA ||
242       isHsaAbiVersion2(getGlobalSTI()))
243     return;
244 
245   auto &Streamer = getTargetStreamer()->getStreamer();
246   auto &Context = Streamer.getContext();
247   auto &ObjectFileInfo = *Context.getObjectFileInfo();
248   auto &ReadOnlySection = *ObjectFileInfo.getReadOnlySection();
249 
250   Streamer.PushSection();
251   Streamer.SwitchSection(&ReadOnlySection);
252 
253   // CP microcode requires the kernel descriptor to be allocated on 64 byte
254   // alignment.
255   Streamer.emitValueToAlignment(64, 0, 1, 0);
256   if (ReadOnlySection.getAlignment() < 64)
257     ReadOnlySection.setAlignment(Align(64));
258 
259   const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
260 
261   SmallString<128> KernelName;
262   getNameWithPrefix(KernelName, &MF->getFunction());
263   getTargetStreamer()->EmitAmdhsaKernelDescriptor(
264       STM, KernelName, getAmdhsaKernelDescriptor(*MF, CurrentProgramInfo),
265       CurrentProgramInfo.NumVGPRsForWavesPerEU,
266       CurrentProgramInfo.NumSGPRsForWavesPerEU -
267           IsaInfo::getNumExtraSGPRs(&STM,
268                                     CurrentProgramInfo.VCCUsed,
269                                     CurrentProgramInfo.FlatUsed),
270       CurrentProgramInfo.VCCUsed, CurrentProgramInfo.FlatUsed);
271 
272   Streamer.PopSection();
273 }
274 
275 void AMDGPUAsmPrinter::emitFunctionEntryLabel() {
276   if (TM.getTargetTriple().getOS() == Triple::AMDHSA &&
277       isHsaAbiVersion3Or4(getGlobalSTI())) {
278     AsmPrinter::emitFunctionEntryLabel();
279     return;
280   }
281 
282   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
283   const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
284   if (MFI->isEntryFunction() && STM.isAmdHsaOrMesa(MF->getFunction())) {
285     SmallString<128> SymbolName;
286     getNameWithPrefix(SymbolName, &MF->getFunction()),
287     getTargetStreamer()->EmitAMDGPUSymbolType(
288         SymbolName, ELF::STT_AMDGPU_HSA_KERNEL);
289   }
290   if (DumpCodeInstEmitter) {
291     // Disassemble function name label to text.
292     DisasmLines.push_back(MF->getName().str() + ":");
293     DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size());
294     HexLines.push_back("");
295   }
296 
297   AsmPrinter::emitFunctionEntryLabel();
298 }
299 
300 void AMDGPUAsmPrinter::emitBasicBlockStart(const MachineBasicBlock &MBB) {
301   if (DumpCodeInstEmitter && !isBlockOnlyReachableByFallthrough(&MBB)) {
302     // Write a line for the basic block label if it is not only fallthrough.
303     DisasmLines.push_back(
304         (Twine("BB") + Twine(getFunctionNumber())
305          + "_" + Twine(MBB.getNumber()) + ":").str());
306     DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size());
307     HexLines.push_back("");
308   }
309   AsmPrinter::emitBasicBlockStart(MBB);
310 }
311 
312 void AMDGPUAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) {
313   if (GV->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) {
314     if (GV->hasInitializer() && !isa<UndefValue>(GV->getInitializer())) {
315       OutContext.reportError({},
316                              Twine(GV->getName()) +
317                                  ": unsupported initializer for address space");
318       return;
319     }
320 
321     // LDS variables aren't emitted in HSA or PAL yet.
322     const Triple::OSType OS = TM.getTargetTriple().getOS();
323     if (OS == Triple::AMDHSA || OS == Triple::AMDPAL)
324       return;
325 
326     MCSymbol *GVSym = getSymbol(GV);
327 
328     GVSym->redefineIfPossible();
329     if (GVSym->isDefined() || GVSym->isVariable())
330       report_fatal_error("symbol '" + Twine(GVSym->getName()) +
331                          "' is already defined");
332 
333     const DataLayout &DL = GV->getParent()->getDataLayout();
334     uint64_t Size = DL.getTypeAllocSize(GV->getValueType());
335     Align Alignment = GV->getAlign().getValueOr(Align(4));
336 
337     emitVisibility(GVSym, GV->getVisibility(), !GV->isDeclaration());
338     emitLinkage(GV, GVSym);
339     if (auto TS = getTargetStreamer())
340       TS->emitAMDGPULDS(GVSym, Size, Alignment);
341     return;
342   }
343 
344   AsmPrinter::emitGlobalVariable(GV);
345 }
346 
347 bool AMDGPUAsmPrinter::doFinalization(Module &M) {
348   CallGraphResourceInfo.clear();
349 
350   // Pad with s_code_end to help tools and guard against instruction prefetch
351   // causing stale data in caches. Arguably this should be done by the linker,
352   // which is why this isn't done for Mesa.
353   const MCSubtargetInfo &STI = *getGlobalSTI();
354   if ((AMDGPU::isGFX10Plus(STI) || AMDGPU::isGFX90A(STI)) &&
355       (STI.getTargetTriple().getOS() == Triple::AMDHSA ||
356        STI.getTargetTriple().getOS() == Triple::AMDPAL)) {
357     OutStreamer->SwitchSection(getObjFileLowering().getTextSection());
358     getTargetStreamer()->EmitCodeEnd(STI);
359   }
360 
361   return AsmPrinter::doFinalization(M);
362 }
363 
364 // Print comments that apply to both callable functions and entry points.
365 void AMDGPUAsmPrinter::emitCommonFunctionComments(
366   uint32_t NumVGPR,
367   Optional<uint32_t> NumAGPR,
368   uint32_t TotalNumVGPR,
369   uint32_t NumSGPR,
370   uint64_t ScratchSize,
371   uint64_t CodeSize,
372   const AMDGPUMachineFunction *MFI) {
373   OutStreamer->emitRawComment(" codeLenInByte = " + Twine(CodeSize), false);
374   OutStreamer->emitRawComment(" NumSgprs: " + Twine(NumSGPR), false);
375   OutStreamer->emitRawComment(" NumVgprs: " + Twine(NumVGPR), false);
376   if (NumAGPR) {
377     OutStreamer->emitRawComment(" NumAgprs: " + Twine(*NumAGPR), false);
378     OutStreamer->emitRawComment(" TotalNumVgprs: " + Twine(TotalNumVGPR),
379                                 false);
380   }
381   OutStreamer->emitRawComment(" ScratchSize: " + Twine(ScratchSize), false);
382   OutStreamer->emitRawComment(" MemoryBound: " + Twine(MFI->isMemoryBound()),
383                               false);
384 }
385 
386 uint16_t AMDGPUAsmPrinter::getAmdhsaKernelCodeProperties(
387     const MachineFunction &MF) const {
388   const SIMachineFunctionInfo &MFI = *MF.getInfo<SIMachineFunctionInfo>();
389   uint16_t KernelCodeProperties = 0;
390 
391   if (MFI.hasPrivateSegmentBuffer()) {
392     KernelCodeProperties |=
393         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
394   }
395   if (MFI.hasDispatchPtr()) {
396     KernelCodeProperties |=
397         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
398   }
399   if (MFI.hasQueuePtr()) {
400     KernelCodeProperties |=
401         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
402   }
403   if (MFI.hasKernargSegmentPtr()) {
404     KernelCodeProperties |=
405         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
406   }
407   if (MFI.hasDispatchID()) {
408     KernelCodeProperties |=
409         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
410   }
411   if (MFI.hasFlatScratchInit()) {
412     KernelCodeProperties |=
413         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
414   }
415   if (MF.getSubtarget<GCNSubtarget>().isWave32()) {
416     KernelCodeProperties |=
417         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32;
418   }
419 
420   return KernelCodeProperties;
421 }
422 
423 amdhsa::kernel_descriptor_t AMDGPUAsmPrinter::getAmdhsaKernelDescriptor(
424     const MachineFunction &MF,
425     const SIProgramInfo &PI) const {
426   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
427   const Function &F = MF.getFunction();
428 
429   amdhsa::kernel_descriptor_t KernelDescriptor;
430   memset(&KernelDescriptor, 0x0, sizeof(KernelDescriptor));
431 
432   assert(isUInt<32>(PI.ScratchSize));
433   assert(isUInt<32>(PI.getComputePGMRSrc1()));
434   assert(isUInt<32>(PI.ComputePGMRSrc2));
435 
436   KernelDescriptor.group_segment_fixed_size = PI.LDSSize;
437   KernelDescriptor.private_segment_fixed_size = PI.ScratchSize;
438 
439   Align MaxKernArgAlign;
440   KernelDescriptor.kernarg_size = STM.getKernArgSegmentSize(F, MaxKernArgAlign);
441 
442   KernelDescriptor.compute_pgm_rsrc1 = PI.getComputePGMRSrc1();
443   KernelDescriptor.compute_pgm_rsrc2 = PI.ComputePGMRSrc2;
444   KernelDescriptor.kernel_code_properties = getAmdhsaKernelCodeProperties(MF);
445 
446   assert(STM.hasGFX90AInsts() || CurrentProgramInfo.ComputePGMRSrc3GFX90A == 0);
447   if (STM.hasGFX90AInsts())
448     KernelDescriptor.compute_pgm_rsrc3 =
449       CurrentProgramInfo.ComputePGMRSrc3GFX90A;
450 
451   return KernelDescriptor;
452 }
453 
454 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
455   CurrentProgramInfo = SIProgramInfo();
456 
457   const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
458 
459   // The starting address of all shader programs must be 256 bytes aligned.
460   // Regular functions just need the basic required instruction alignment.
461   MF.setAlignment(MFI->isEntryFunction() ? Align(256) : Align(4));
462 
463   SetupMachineFunction(MF);
464 
465   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
466   MCContext &Context = getObjFileLowering().getContext();
467   // FIXME: This should be an explicit check for Mesa.
468   if (!STM.isAmdHsaOS() && !STM.isAmdPalOS()) {
469     MCSectionELF *ConfigSection =
470         Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
471     OutStreamer->SwitchSection(ConfigSection);
472   }
473 
474   if (MFI->isModuleEntryFunction()) {
475     getSIProgramInfo(CurrentProgramInfo, MF);
476   } else {
477     auto I = CallGraphResourceInfo.insert(
478       std::make_pair(&MF.getFunction(), SIFunctionResourceInfo()));
479     SIFunctionResourceInfo &Info = I.first->second;
480     assert(I.second && "should only be called once per function");
481     Info = analyzeResourceUsage(MF);
482   }
483 
484   if (STM.isAmdPalOS()) {
485     if (MFI->isEntryFunction())
486       EmitPALMetadata(MF, CurrentProgramInfo);
487     else if (MFI->isModuleEntryFunction())
488       emitPALFunctionMetadata(MF);
489   } else if (!STM.isAmdHsaOS()) {
490     EmitProgramInfoSI(MF, CurrentProgramInfo);
491   }
492 
493   DumpCodeInstEmitter = nullptr;
494   if (STM.dumpCode()) {
495     // For -dumpcode, get the assembler out of the streamer, even if it does
496     // not really want to let us have it. This only works with -filetype=obj.
497     bool SaveFlag = OutStreamer->getUseAssemblerInfoForParsing();
498     OutStreamer->setUseAssemblerInfoForParsing(true);
499     MCAssembler *Assembler = OutStreamer->getAssemblerPtr();
500     OutStreamer->setUseAssemblerInfoForParsing(SaveFlag);
501     if (Assembler)
502       DumpCodeInstEmitter = Assembler->getEmitterPtr();
503   }
504 
505   DisasmLines.clear();
506   HexLines.clear();
507   DisasmLineMaxLen = 0;
508 
509   emitFunctionBody();
510 
511   if (isVerbose()) {
512     MCSectionELF *CommentSection =
513         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
514     OutStreamer->SwitchSection(CommentSection);
515 
516     if (!MFI->isEntryFunction()) {
517       OutStreamer->emitRawComment(" Function info:", false);
518       SIFunctionResourceInfo &Info = CallGraphResourceInfo[&MF.getFunction()];
519       emitCommonFunctionComments(
520         Info.NumVGPR,
521         STM.hasMAIInsts() ? Info.NumAGPR : Optional<uint32_t>(),
522         Info.getTotalNumVGPRs(STM),
523         Info.getTotalNumSGPRs(MF.getSubtarget<GCNSubtarget>()),
524         Info.PrivateSegmentSize,
525         getFunctionCodeSize(MF), MFI);
526       return false;
527     }
528 
529     OutStreamer->emitRawComment(" Kernel info:", false);
530     emitCommonFunctionComments(CurrentProgramInfo.NumArchVGPR,
531                                STM.hasMAIInsts()
532                                  ? CurrentProgramInfo.NumAccVGPR
533                                  : Optional<uint32_t>(),
534                                CurrentProgramInfo.NumVGPR,
535                                CurrentProgramInfo.NumSGPR,
536                                CurrentProgramInfo.ScratchSize,
537                                getFunctionCodeSize(MF), MFI);
538 
539     OutStreamer->emitRawComment(
540       " FloatMode: " + Twine(CurrentProgramInfo.FloatMode), false);
541     OutStreamer->emitRawComment(
542       " IeeeMode: " + Twine(CurrentProgramInfo.IEEEMode), false);
543     OutStreamer->emitRawComment(
544       " LDSByteSize: " + Twine(CurrentProgramInfo.LDSSize) +
545       " bytes/workgroup (compile time only)", false);
546 
547     OutStreamer->emitRawComment(
548       " SGPRBlocks: " + Twine(CurrentProgramInfo.SGPRBlocks), false);
549     OutStreamer->emitRawComment(
550       " VGPRBlocks: " + Twine(CurrentProgramInfo.VGPRBlocks), false);
551 
552     OutStreamer->emitRawComment(
553       " NumSGPRsForWavesPerEU: " +
554       Twine(CurrentProgramInfo.NumSGPRsForWavesPerEU), false);
555     OutStreamer->emitRawComment(
556       " NumVGPRsForWavesPerEU: " +
557       Twine(CurrentProgramInfo.NumVGPRsForWavesPerEU), false);
558 
559     if (STM.hasGFX90AInsts())
560       OutStreamer->emitRawComment(
561         " AccumOffset: " +
562         Twine((CurrentProgramInfo.AccumOffset + 1) * 4), false);
563 
564     OutStreamer->emitRawComment(
565       " Occupancy: " +
566       Twine(CurrentProgramInfo.Occupancy), false);
567 
568     OutStreamer->emitRawComment(
569       " WaveLimiterHint : " + Twine(MFI->needsWaveLimiter()), false);
570 
571     OutStreamer->emitRawComment(
572       " COMPUTE_PGM_RSRC2:SCRATCH_EN: " +
573       Twine(G_00B84C_SCRATCH_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
574     OutStreamer->emitRawComment(
575       " COMPUTE_PGM_RSRC2:USER_SGPR: " +
576       Twine(G_00B84C_USER_SGPR(CurrentProgramInfo.ComputePGMRSrc2)), false);
577     OutStreamer->emitRawComment(
578       " COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
579       Twine(G_00B84C_TRAP_HANDLER(CurrentProgramInfo.ComputePGMRSrc2)), false);
580     OutStreamer->emitRawComment(
581       " COMPUTE_PGM_RSRC2:TGID_X_EN: " +
582       Twine(G_00B84C_TGID_X_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
583     OutStreamer->emitRawComment(
584       " COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
585       Twine(G_00B84C_TGID_Y_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
586     OutStreamer->emitRawComment(
587       " COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
588       Twine(G_00B84C_TGID_Z_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
589     OutStreamer->emitRawComment(
590       " COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
591       Twine(G_00B84C_TIDIG_COMP_CNT(CurrentProgramInfo.ComputePGMRSrc2)),
592       false);
593 
594     assert(STM.hasGFX90AInsts() ||
595            CurrentProgramInfo.ComputePGMRSrc3GFX90A == 0);
596     if (STM.hasGFX90AInsts()) {
597       OutStreamer->emitRawComment(
598         " COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: " +
599         Twine((AMDHSA_BITS_GET(CurrentProgramInfo.ComputePGMRSrc3GFX90A,
600                                amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET))),
601                                false);
602       OutStreamer->emitRawComment(
603         " COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: " +
604         Twine((AMDHSA_BITS_GET(CurrentProgramInfo.ComputePGMRSrc3GFX90A,
605                                amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT))),
606                                false);
607     }
608   }
609 
610   if (DumpCodeInstEmitter) {
611 
612     OutStreamer->SwitchSection(
613         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_PROGBITS, 0));
614 
615     for (size_t i = 0; i < DisasmLines.size(); ++i) {
616       std::string Comment = "\n";
617       if (!HexLines[i].empty()) {
618         Comment = std::string(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
619         Comment += " ; " + HexLines[i] + "\n";
620       }
621 
622       OutStreamer->emitBytes(StringRef(DisasmLines[i]));
623       OutStreamer->emitBytes(StringRef(Comment));
624     }
625   }
626 
627   return false;
628 }
629 
630 bool AMDGPUAsmPrinter::doInitialization(Module &M) {
631   NonKernelMaxSGPRs = 0;
632   NonKernelMaxVGPRs = 0;
633   // Compute upper bound on the number of SGPRs and VGPRs
634   // for non-kernel functions.
635   for (const Function &F : M) {
636     if (!AMDGPU::isEntryFunctionCC(F.getCallingConv())) {
637       const GCNSubtarget &STM = TM.getSubtarget<GCNSubtarget>(F);
638       NonKernelMaxSGPRs = std::max(NonKernelMaxSGPRs, STM.getMaxNumSGPRs(F));
639       NonKernelMaxVGPRs = std::max(NonKernelMaxVGPRs, STM.getMaxNumVGPRs(F));
640     }
641   }
642   return AsmPrinter::doInitialization(M);
643 }
644 
645 // TODO: Fold this into emitFunctionBodyStart.
646 void AMDGPUAsmPrinter::initializeTargetID(const Module &M) {
647   // In the beginning all features are either 'Any' or 'NotSupported',
648   // depending on global target features. This will cover empty modules.
649   getTargetStreamer()->initializeTargetID(
650       *getGlobalSTI(), getGlobalSTI()->getFeatureString());
651 
652   // If module is empty, we are done.
653   if (M.empty())
654     return;
655 
656   // If module is not empty, need to find first 'Off' or 'On' feature
657   // setting per feature from functions in module.
658   for (auto &F : M) {
659     auto &TSTargetID = getTargetStreamer()->getTargetID();
660     if ((!TSTargetID->isXnackSupported() || TSTargetID->isXnackOnOrOff()) &&
661         (!TSTargetID->isSramEccSupported() || TSTargetID->isSramEccOnOrOff()))
662       break;
663 
664     const GCNSubtarget &STM = TM.getSubtarget<GCNSubtarget>(F);
665     const IsaInfo::AMDGPUTargetID &STMTargetID = STM.getTargetID();
666     if (TSTargetID->isXnackSupported())
667       if (TSTargetID->getXnackSetting() == IsaInfo::TargetIDSetting::Any)
668         TSTargetID->setXnackSetting(STMTargetID.getXnackSetting());
669     if (TSTargetID->isSramEccSupported())
670       if (TSTargetID->getSramEccSetting() == IsaInfo::TargetIDSetting::Any)
671         TSTargetID->setSramEccSetting(STMTargetID.getSramEccSetting());
672   }
673 }
674 
675 uint64_t AMDGPUAsmPrinter::getFunctionCodeSize(const MachineFunction &MF) const {
676   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
677   const SIInstrInfo *TII = STM.getInstrInfo();
678 
679   uint64_t CodeSize = 0;
680 
681   for (const MachineBasicBlock &MBB : MF) {
682     for (const MachineInstr &MI : MBB) {
683       // TODO: CodeSize should account for multiple functions.
684 
685       // TODO: Should we count size of debug info?
686       if (MI.isDebugInstr())
687         continue;
688 
689       CodeSize += TII->getInstSizeInBytes(MI);
690     }
691   }
692 
693   return CodeSize;
694 }
695 
696 static bool hasAnyNonFlatUseOfReg(const MachineRegisterInfo &MRI,
697                                   const SIInstrInfo &TII,
698                                   unsigned Reg) {
699   for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) {
700     if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent()))
701       return true;
702   }
703 
704   return false;
705 }
706 
707 int32_t AMDGPUAsmPrinter::SIFunctionResourceInfo::getTotalNumSGPRs(
708   const GCNSubtarget &ST) const {
709   return NumExplicitSGPR + IsaInfo::getNumExtraSGPRs(
710       &ST, UsesVCC, UsesFlatScratch, ST.getTargetID().isXnackOnOrAny());
711 }
712 
713 int32_t AMDGPUAsmPrinter::SIFunctionResourceInfo::getTotalNumVGPRs(
714   const GCNSubtarget &ST) const {
715   if (ST.hasGFX90AInsts() && NumAGPR)
716     return alignTo(NumVGPR, 4) + NumAGPR;
717   return std::max(NumVGPR, NumAGPR);
718 }
719 
720 static const Function *getCalleeFunction(const MachineOperand &Op) {
721   if (Op.isImm()) {
722     assert(Op.getImm() == 0);
723     return nullptr;
724   }
725 
726   return cast<Function>(Op.getGlobal());
727 }
728 
729 AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
730   const MachineFunction &MF) const {
731   SIFunctionResourceInfo Info;
732 
733   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
734   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
735   const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
736   const MachineRegisterInfo &MRI = MF.getRegInfo();
737   const SIInstrInfo *TII = ST.getInstrInfo();
738   const SIRegisterInfo &TRI = TII->getRegisterInfo();
739 
740   Info.UsesFlatScratch = MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_LO) ||
741                          MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_HI) ||
742                          MRI.isLiveIn(MFI->getPreloadedReg(
743                              AMDGPUFunctionArgInfo::FLAT_SCRATCH_INIT));
744 
745   // Even if FLAT_SCRATCH is implicitly used, it has no effect if flat
746   // instructions aren't used to access the scratch buffer. Inline assembly may
747   // need it though.
748   //
749   // If we only have implicit uses of flat_scr on flat instructions, it is not
750   // really needed.
751   if (Info.UsesFlatScratch && !MFI->hasFlatScratchInit() &&
752       (!hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR) &&
753        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_LO) &&
754        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_HI))) {
755     Info.UsesFlatScratch = false;
756   }
757 
758   Info.PrivateSegmentSize = FrameInfo.getStackSize();
759 
760   // Assume a big number if there are any unknown sized objects.
761   Info.HasDynamicallySizedStack = FrameInfo.hasVarSizedObjects();
762   if (Info.HasDynamicallySizedStack)
763     Info.PrivateSegmentSize += AssumedStackSizeForDynamicSizeObjects;
764 
765   if (MFI->isStackRealigned())
766     Info.PrivateSegmentSize += FrameInfo.getMaxAlign().value();
767 
768   Info.UsesVCC = MRI.isPhysRegUsed(AMDGPU::VCC_LO) ||
769                  MRI.isPhysRegUsed(AMDGPU::VCC_HI);
770 
771   // If there are no calls, MachineRegisterInfo can tell us the used register
772   // count easily.
773   // A tail call isn't considered a call for MachineFrameInfo's purposes.
774   if (!FrameInfo.hasCalls() && !FrameInfo.hasTailCall()) {
775     MCPhysReg HighestVGPRReg = AMDGPU::NoRegister;
776     for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) {
777       if (MRI.isPhysRegUsed(Reg)) {
778         HighestVGPRReg = Reg;
779         break;
780       }
781     }
782 
783     if (ST.hasMAIInsts()) {
784       MCPhysReg HighestAGPRReg = AMDGPU::NoRegister;
785       for (MCPhysReg Reg : reverse(AMDGPU::AGPR_32RegClass.getRegisters())) {
786         if (MRI.isPhysRegUsed(Reg)) {
787           HighestAGPRReg = Reg;
788           break;
789         }
790       }
791       Info.NumAGPR = HighestAGPRReg == AMDGPU::NoRegister ? 0 :
792         TRI.getHWRegIndex(HighestAGPRReg) + 1;
793     }
794 
795     MCPhysReg HighestSGPRReg = AMDGPU::NoRegister;
796     for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) {
797       if (MRI.isPhysRegUsed(Reg)) {
798         HighestSGPRReg = Reg;
799         break;
800       }
801     }
802 
803     // We found the maximum register index. They start at 0, so add one to get the
804     // number of registers.
805     Info.NumVGPR = HighestVGPRReg == AMDGPU::NoRegister ? 0 :
806       TRI.getHWRegIndex(HighestVGPRReg) + 1;
807     Info.NumExplicitSGPR = HighestSGPRReg == AMDGPU::NoRegister ? 0 :
808       TRI.getHWRegIndex(HighestSGPRReg) + 1;
809 
810     return Info;
811   }
812 
813   int32_t MaxVGPR = -1;
814   int32_t MaxAGPR = -1;
815   int32_t MaxSGPR = -1;
816   uint64_t CalleeFrameSize = 0;
817 
818   for (const MachineBasicBlock &MBB : MF) {
819     for (const MachineInstr &MI : MBB) {
820       // TODO: Check regmasks? Do they occur anywhere except calls?
821       for (const MachineOperand &MO : MI.operands()) {
822         unsigned Width = 0;
823         bool IsSGPR = false;
824         bool IsAGPR = false;
825 
826         if (!MO.isReg())
827           continue;
828 
829         Register Reg = MO.getReg();
830         switch (Reg) {
831         case AMDGPU::EXEC:
832         case AMDGPU::EXEC_LO:
833         case AMDGPU::EXEC_HI:
834         case AMDGPU::SCC:
835         case AMDGPU::M0:
836         case AMDGPU::M0_LO16:
837         case AMDGPU::M0_HI16:
838         case AMDGPU::SRC_SHARED_BASE:
839         case AMDGPU::SRC_SHARED_LIMIT:
840         case AMDGPU::SRC_PRIVATE_BASE:
841         case AMDGPU::SRC_PRIVATE_LIMIT:
842         case AMDGPU::SGPR_NULL:
843         case AMDGPU::MODE:
844           continue;
845 
846         case AMDGPU::SRC_POPS_EXITING_WAVE_ID:
847           llvm_unreachable("src_pops_exiting_wave_id should not be used");
848 
849         case AMDGPU::NoRegister:
850           assert(MI.isDebugInstr() && "Instruction uses invalid noreg register");
851           continue;
852 
853         case AMDGPU::VCC:
854         case AMDGPU::VCC_LO:
855         case AMDGPU::VCC_HI:
856         case AMDGPU::VCC_LO_LO16:
857         case AMDGPU::VCC_LO_HI16:
858         case AMDGPU::VCC_HI_LO16:
859         case AMDGPU::VCC_HI_HI16:
860           Info.UsesVCC = true;
861           continue;
862 
863         case AMDGPU::FLAT_SCR:
864         case AMDGPU::FLAT_SCR_LO:
865         case AMDGPU::FLAT_SCR_HI:
866           continue;
867 
868         case AMDGPU::XNACK_MASK:
869         case AMDGPU::XNACK_MASK_LO:
870         case AMDGPU::XNACK_MASK_HI:
871           llvm_unreachable("xnack_mask registers should not be used");
872 
873         case AMDGPU::LDS_DIRECT:
874           llvm_unreachable("lds_direct register should not be used");
875 
876         case AMDGPU::TBA:
877         case AMDGPU::TBA_LO:
878         case AMDGPU::TBA_HI:
879         case AMDGPU::TMA:
880         case AMDGPU::TMA_LO:
881         case AMDGPU::TMA_HI:
882           llvm_unreachable("trap handler registers should not be used");
883 
884         case AMDGPU::SRC_VCCZ:
885           llvm_unreachable("src_vccz register should not be used");
886 
887         case AMDGPU::SRC_EXECZ:
888           llvm_unreachable("src_execz register should not be used");
889 
890         case AMDGPU::SRC_SCC:
891           llvm_unreachable("src_scc register should not be used");
892 
893         default:
894           break;
895         }
896 
897         if (AMDGPU::SReg_32RegClass.contains(Reg) ||
898             AMDGPU::SReg_LO16RegClass.contains(Reg) ||
899             AMDGPU::SGPR_HI16RegClass.contains(Reg)) {
900           assert(!AMDGPU::TTMP_32RegClass.contains(Reg) &&
901                  "trap handler registers should not be used");
902           IsSGPR = true;
903           Width = 1;
904         } else if (AMDGPU::VGPR_32RegClass.contains(Reg) ||
905                    AMDGPU::VGPR_LO16RegClass.contains(Reg) ||
906                    AMDGPU::VGPR_HI16RegClass.contains(Reg)) {
907           IsSGPR = false;
908           Width = 1;
909         } else if (AMDGPU::AGPR_32RegClass.contains(Reg) ||
910                    AMDGPU::AGPR_LO16RegClass.contains(Reg)) {
911           IsSGPR = false;
912           IsAGPR = true;
913           Width = 1;
914         } else if (AMDGPU::SReg_64RegClass.contains(Reg)) {
915           assert(!AMDGPU::TTMP_64RegClass.contains(Reg) &&
916                  "trap handler registers should not be used");
917           IsSGPR = true;
918           Width = 2;
919         } else if (AMDGPU::VReg_64RegClass.contains(Reg)) {
920           IsSGPR = false;
921           Width = 2;
922         } else if (AMDGPU::AReg_64RegClass.contains(Reg)) {
923           IsSGPR = false;
924           IsAGPR = true;
925           Width = 2;
926         } else if (AMDGPU::VReg_96RegClass.contains(Reg)) {
927           IsSGPR = false;
928           Width = 3;
929         } else if (AMDGPU::SReg_96RegClass.contains(Reg)) {
930           IsSGPR = true;
931           Width = 3;
932         } else if (AMDGPU::AReg_96RegClass.contains(Reg)) {
933           IsSGPR = false;
934           IsAGPR = true;
935           Width = 3;
936         } else if (AMDGPU::SReg_128RegClass.contains(Reg)) {
937           assert(!AMDGPU::TTMP_128RegClass.contains(Reg) &&
938             "trap handler registers should not be used");
939           IsSGPR = true;
940           Width = 4;
941         } else if (AMDGPU::VReg_128RegClass.contains(Reg)) {
942           IsSGPR = false;
943           Width = 4;
944         } else if (AMDGPU::AReg_128RegClass.contains(Reg)) {
945           IsSGPR = false;
946           IsAGPR = true;
947           Width = 4;
948         } else if (AMDGPU::VReg_160RegClass.contains(Reg)) {
949           IsSGPR = false;
950           Width = 5;
951         } else if (AMDGPU::SReg_160RegClass.contains(Reg)) {
952           IsSGPR = true;
953           Width = 5;
954         } else if (AMDGPU::AReg_160RegClass.contains(Reg)) {
955           IsSGPR = false;
956           IsAGPR = true;
957           Width = 5;
958         } else if (AMDGPU::VReg_192RegClass.contains(Reg)) {
959           IsSGPR = false;
960           Width = 6;
961         } else if (AMDGPU::SReg_192RegClass.contains(Reg)) {
962           IsSGPR = true;
963           Width = 6;
964         } else if (AMDGPU::AReg_192RegClass.contains(Reg)) {
965           IsSGPR = false;
966           IsAGPR = true;
967           Width = 6;
968         } else if (AMDGPU::VReg_224RegClass.contains(Reg)) {
969           IsSGPR = false;
970           Width = 7;
971         } else if (AMDGPU::SReg_224RegClass.contains(Reg)) {
972           IsSGPR = true;
973           Width = 7;
974         } else if (AMDGPU::AReg_224RegClass.contains(Reg)) {
975           IsSGPR = false;
976           IsAGPR = true;
977           Width = 7;
978         } else if (AMDGPU::SReg_256RegClass.contains(Reg)) {
979           assert(!AMDGPU::TTMP_256RegClass.contains(Reg) &&
980             "trap handler registers should not be used");
981           IsSGPR = true;
982           Width = 8;
983         } else if (AMDGPU::VReg_256RegClass.contains(Reg)) {
984           IsSGPR = false;
985           Width = 8;
986         } else if (AMDGPU::AReg_256RegClass.contains(Reg)) {
987           IsSGPR = false;
988           IsAGPR = true;
989           Width = 8;
990         } else if (AMDGPU::SReg_512RegClass.contains(Reg)) {
991           assert(!AMDGPU::TTMP_512RegClass.contains(Reg) &&
992             "trap handler registers should not be used");
993           IsSGPR = true;
994           Width = 16;
995         } else if (AMDGPU::VReg_512RegClass.contains(Reg)) {
996           IsSGPR = false;
997           Width = 16;
998         } else if (AMDGPU::AReg_512RegClass.contains(Reg)) {
999           IsSGPR = false;
1000           IsAGPR = true;
1001           Width = 16;
1002         } else if (AMDGPU::SReg_1024RegClass.contains(Reg)) {
1003           IsSGPR = true;
1004           Width = 32;
1005         } else if (AMDGPU::VReg_1024RegClass.contains(Reg)) {
1006           IsSGPR = false;
1007           Width = 32;
1008         } else if (AMDGPU::AReg_1024RegClass.contains(Reg)) {
1009           IsSGPR = false;
1010           IsAGPR = true;
1011           Width = 32;
1012         } else {
1013           llvm_unreachable("Unknown register class");
1014         }
1015         unsigned HWReg = TRI.getHWRegIndex(Reg);
1016         int MaxUsed = HWReg + Width - 1;
1017         if (IsSGPR) {
1018           MaxSGPR = MaxUsed > MaxSGPR ? MaxUsed : MaxSGPR;
1019         } else if (IsAGPR) {
1020           MaxAGPR = MaxUsed > MaxAGPR ? MaxUsed : MaxAGPR;
1021         } else {
1022           MaxVGPR = MaxUsed > MaxVGPR ? MaxUsed : MaxVGPR;
1023         }
1024       }
1025 
1026       if (MI.isCall()) {
1027         // Pseudo used just to encode the underlying global. Is there a better
1028         // way to track this?
1029 
1030         const MachineOperand *CalleeOp
1031           = TII->getNamedOperand(MI, AMDGPU::OpName::callee);
1032 
1033         const Function *Callee = getCalleeFunction(*CalleeOp);
1034         DenseMap<const Function *, SIFunctionResourceInfo>::const_iterator I =
1035             CallGraphResourceInfo.end();
1036         bool IsExternal = !Callee || Callee->isDeclaration();
1037         if (!IsExternal)
1038           I = CallGraphResourceInfo.find(Callee);
1039 
1040         if (IsExternal || I == CallGraphResourceInfo.end()) {
1041           // Avoid crashing on undefined behavior with an illegal call to a
1042           // kernel. If a callsite's calling convention doesn't match the
1043           // function's, it's undefined behavior. If the callsite calling
1044           // convention does match, that would have errored earlier.
1045           // FIXME: The verifier shouldn't allow this.
1046           if (!IsExternal &&
1047               AMDGPU::isEntryFunctionCC(Callee->getCallingConv()))
1048             report_fatal_error("invalid call to entry function");
1049 
1050           unsigned ExtraSGPRs = IsaInfo::getNumExtraSGPRs(
1051               TM.getMCSubtargetInfo(), false, ST.hasFlatAddressSpace());
1052           // If this is a call to an external function, we put the
1053           // max values computed in doInitialization().
1054           // Subtract extra SGPRs in case of indirect calls.
1055           // For indirect calls, we take the max for the module
1056           // and use that as the register budget for functions
1057           // which makes an indirect calls. This max value
1058           // includes extra SGPRs too (e.g. flatscratch and vcc).
1059           // which are getting added later.
1060           // Subtract them here so that they don't get added twice.
1061           MaxSGPR = NonKernelMaxSGPRs - ExtraSGPRs - 1;
1062           MaxVGPR = NonKernelMaxVGPRs - 1;
1063           // TODO: handle AGPRs
1064           MaxAGPR = std::max(MaxAGPR, 23);
1065 
1066           CalleeFrameSize = std::max(CalleeFrameSize,
1067             static_cast<uint64_t>(AssumedStackSizeForExternalCall));
1068 
1069           Info.UsesVCC = true;
1070           Info.UsesFlatScratch = ST.hasFlatAddressSpace();
1071           Info.HasDynamicallySizedStack = true;
1072         } else {
1073           // We force CodeGen to run in SCC order, so the callee's register
1074           // usage etc. should be the cumulative usage of all callees.
1075 
1076           MaxSGPR = std::max(I->second.NumExplicitSGPR - 1, MaxSGPR);
1077           MaxVGPR = std::max(I->second.NumVGPR - 1, MaxVGPR);
1078           MaxAGPR = std::max(I->second.NumAGPR - 1, MaxAGPR);
1079           CalleeFrameSize
1080             = std::max(I->second.PrivateSegmentSize, CalleeFrameSize);
1081           Info.UsesVCC |= I->second.UsesVCC;
1082           Info.UsesFlatScratch |= I->second.UsesFlatScratch;
1083           Info.HasDynamicallySizedStack |= I->second.HasDynamicallySizedStack;
1084           Info.HasRecursion |= I->second.HasRecursion;
1085         }
1086 
1087         // FIXME: Call site could have norecurse on it
1088         if (!Callee || !Callee->doesNotRecurse())
1089           Info.HasRecursion = true;
1090       }
1091     }
1092   }
1093 
1094   Info.NumExplicitSGPR = MaxSGPR + 1;
1095   Info.NumVGPR = MaxVGPR + 1;
1096   Info.NumAGPR = MaxAGPR + 1;
1097   Info.PrivateSegmentSize += CalleeFrameSize;
1098 
1099   return Info;
1100 }
1101 
1102 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
1103                                         const MachineFunction &MF) {
1104   SIFunctionResourceInfo Info = analyzeResourceUsage(MF);
1105   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
1106 
1107   ProgInfo.NumArchVGPR = Info.NumVGPR;
1108   ProgInfo.NumAccVGPR = Info.NumAGPR;
1109   ProgInfo.NumVGPR = Info.getTotalNumVGPRs(STM);
1110   ProgInfo.AccumOffset = alignTo(std::max(1, Info.NumVGPR), 4) / 4 - 1;
1111   ProgInfo.TgSplit = STM.isTgSplitEnabled();
1112   ProgInfo.NumSGPR = Info.NumExplicitSGPR;
1113   ProgInfo.ScratchSize = Info.PrivateSegmentSize;
1114   ProgInfo.VCCUsed = Info.UsesVCC;
1115   ProgInfo.FlatUsed = Info.UsesFlatScratch;
1116   ProgInfo.DynamicCallStack = Info.HasDynamicallySizedStack || Info.HasRecursion;
1117 
1118   const uint64_t MaxScratchPerWorkitem =
1119       GCNSubtarget::MaxWaveScratchSize / STM.getWavefrontSize();
1120   if (ProgInfo.ScratchSize > MaxScratchPerWorkitem) {
1121     DiagnosticInfoStackSize DiagStackSize(MF.getFunction(),
1122                                           ProgInfo.ScratchSize, DS_Error);
1123     MF.getFunction().getContext().diagnose(DiagStackSize);
1124   }
1125 
1126   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1127 
1128   // The calculations related to SGPR/VGPR blocks are
1129   // duplicated in part in AMDGPUAsmParser::calculateGPRBlocks, and could be
1130   // unified.
1131   unsigned ExtraSGPRs = IsaInfo::getNumExtraSGPRs(
1132       &STM, ProgInfo.VCCUsed, ProgInfo.FlatUsed);
1133 
1134   // Check the addressable register limit before we add ExtraSGPRs.
1135   if (STM.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
1136       !STM.hasSGPRInitBug()) {
1137     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
1138     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
1139       // This can happen due to a compiler bug or when using inline asm.
1140       LLVMContext &Ctx = MF.getFunction().getContext();
1141       DiagnosticInfoResourceLimit Diag(MF.getFunction(),
1142                                        "addressable scalar registers",
1143                                        ProgInfo.NumSGPR, DS_Error,
1144                                        DK_ResourceLimit,
1145                                        MaxAddressableNumSGPRs);
1146       Ctx.diagnose(Diag);
1147       ProgInfo.NumSGPR = MaxAddressableNumSGPRs - 1;
1148     }
1149   }
1150 
1151   // Account for extra SGPRs and VGPRs reserved for debugger use.
1152   ProgInfo.NumSGPR += ExtraSGPRs;
1153 
1154   const Function &F = MF.getFunction();
1155 
1156   // Ensure there are enough SGPRs and VGPRs for wave dispatch, where wave
1157   // dispatch registers are function args.
1158   unsigned WaveDispatchNumSGPR = 0, WaveDispatchNumVGPR = 0;
1159 
1160   if (isShader(F.getCallingConv())) {
1161     // FIXME: We should be using the number of registers determined during
1162     // calling convention lowering to legalize the types.
1163     const DataLayout &DL = F.getParent()->getDataLayout();
1164     for (auto &Arg : F.args()) {
1165       unsigned NumRegs = (DL.getTypeSizeInBits(Arg.getType()) + 31) / 32;
1166       if (Arg.hasAttribute(Attribute::InReg))
1167         WaveDispatchNumSGPR += NumRegs;
1168       else
1169         WaveDispatchNumVGPR += NumRegs;
1170     }
1171     ProgInfo.NumSGPR = std::max(ProgInfo.NumSGPR, WaveDispatchNumSGPR);
1172     ProgInfo.NumVGPR = std::max(ProgInfo.NumVGPR, WaveDispatchNumVGPR);
1173   }
1174 
1175   // Adjust number of registers used to meet default/requested minimum/maximum
1176   // number of waves per execution unit request.
1177   ProgInfo.NumSGPRsForWavesPerEU = std::max(
1178     std::max(ProgInfo.NumSGPR, 1u), STM.getMinNumSGPRs(MFI->getMaxWavesPerEU()));
1179   ProgInfo.NumVGPRsForWavesPerEU = std::max(
1180     std::max(ProgInfo.NumVGPR, 1u), STM.getMinNumVGPRs(MFI->getMaxWavesPerEU()));
1181 
1182   if (STM.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ||
1183       STM.hasSGPRInitBug()) {
1184     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
1185     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
1186       // This can happen due to a compiler bug or when using inline asm to use
1187       // the registers which are usually reserved for vcc etc.
1188       LLVMContext &Ctx = MF.getFunction().getContext();
1189       DiagnosticInfoResourceLimit Diag(MF.getFunction(),
1190                                        "scalar registers",
1191                                        ProgInfo.NumSGPR, DS_Error,
1192                                        DK_ResourceLimit,
1193                                        MaxAddressableNumSGPRs);
1194       Ctx.diagnose(Diag);
1195       ProgInfo.NumSGPR = MaxAddressableNumSGPRs;
1196       ProgInfo.NumSGPRsForWavesPerEU = MaxAddressableNumSGPRs;
1197     }
1198   }
1199 
1200   if (STM.hasSGPRInitBug()) {
1201     ProgInfo.NumSGPR =
1202         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
1203     ProgInfo.NumSGPRsForWavesPerEU =
1204         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
1205   }
1206 
1207   if (MFI->getNumUserSGPRs() > STM.getMaxNumUserSGPRs()) {
1208     LLVMContext &Ctx = MF.getFunction().getContext();
1209     DiagnosticInfoResourceLimit Diag(MF.getFunction(), "user SGPRs",
1210                                      MFI->getNumUserSGPRs(), DS_Error);
1211     Ctx.diagnose(Diag);
1212   }
1213 
1214   if (MFI->getLDSSize() > static_cast<unsigned>(STM.getLocalMemorySize())) {
1215     LLVMContext &Ctx = MF.getFunction().getContext();
1216     DiagnosticInfoResourceLimit Diag(MF.getFunction(), "local memory",
1217                                      MFI->getLDSSize(), DS_Error);
1218     Ctx.diagnose(Diag);
1219   }
1220 
1221   ProgInfo.SGPRBlocks = IsaInfo::getNumSGPRBlocks(
1222       &STM, ProgInfo.NumSGPRsForWavesPerEU);
1223   ProgInfo.VGPRBlocks = IsaInfo::getNumVGPRBlocks(
1224       &STM, ProgInfo.NumVGPRsForWavesPerEU);
1225 
1226   const SIModeRegisterDefaults Mode = MFI->getMode();
1227 
1228   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
1229   // register.
1230   ProgInfo.FloatMode = getFPMode(Mode);
1231 
1232   ProgInfo.IEEEMode = Mode.IEEE;
1233 
1234   // Make clamp modifier on NaN input returns 0.
1235   ProgInfo.DX10Clamp = Mode.DX10Clamp;
1236 
1237   unsigned LDSAlignShift;
1238   if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
1239     // LDS is allocated in 64 dword blocks.
1240     LDSAlignShift = 8;
1241   } else {
1242     // LDS is allocated in 128 dword blocks.
1243     LDSAlignShift = 9;
1244   }
1245 
1246   unsigned LDSSpillSize =
1247     MFI->getLDSWaveSpillSize() * MFI->getMaxFlatWorkGroupSize();
1248 
1249   ProgInfo.LDSSize = MFI->getLDSSize() + LDSSpillSize;
1250   ProgInfo.LDSBlocks =
1251       alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
1252 
1253   // Scratch is allocated in 256 dword blocks.
1254   unsigned ScratchAlignShift = 10;
1255   // We need to program the hardware with the amount of scratch memory that
1256   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
1257   // scratch memory used per thread.
1258   ProgInfo.ScratchBlocks =
1259       alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
1260               1ULL << ScratchAlignShift) >>
1261       ScratchAlignShift;
1262 
1263   if (getIsaVersion(getGlobalSTI()->getCPU()).Major >= 10) {
1264     ProgInfo.WgpMode = STM.isCuModeEnabled() ? 0 : 1;
1265     ProgInfo.MemOrdered = 1;
1266   }
1267 
1268   // 0 = X, 1 = XY, 2 = XYZ
1269   unsigned TIDIGCompCnt = 0;
1270   if (MFI->hasWorkItemIDZ())
1271     TIDIGCompCnt = 2;
1272   else if (MFI->hasWorkItemIDY())
1273     TIDIGCompCnt = 1;
1274 
1275   ProgInfo.ComputePGMRSrc2 =
1276       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
1277       S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
1278       // For AMDHSA, TRAP_HANDLER must be zero, as it is populated by the CP.
1279       S_00B84C_TRAP_HANDLER(STM.isAmdHsaOS() ? 0 : STM.isTrapHandlerEnabled()) |
1280       S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
1281       S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
1282       S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
1283       S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
1284       S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
1285       S_00B84C_EXCP_EN_MSB(0) |
1286       // For AMDHSA, LDS_SIZE must be zero, as it is populated by the CP.
1287       S_00B84C_LDS_SIZE(STM.isAmdHsaOS() ? 0 : ProgInfo.LDSBlocks) |
1288       S_00B84C_EXCP_EN(0);
1289 
1290   if (STM.hasGFX90AInsts()) {
1291     AMDHSA_BITS_SET(ProgInfo.ComputePGMRSrc3GFX90A,
1292                     amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET,
1293                     ProgInfo.AccumOffset);
1294     AMDHSA_BITS_SET(ProgInfo.ComputePGMRSrc3GFX90A,
1295                     amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT,
1296                     ProgInfo.TgSplit);
1297   }
1298 
1299   ProgInfo.Occupancy = STM.computeOccupancy(MF.getFunction(), ProgInfo.LDSSize,
1300                                             ProgInfo.NumSGPRsForWavesPerEU,
1301                                             ProgInfo.NumVGPRsForWavesPerEU);
1302 }
1303 
1304 static unsigned getRsrcReg(CallingConv::ID CallConv) {
1305   switch (CallConv) {
1306   default: LLVM_FALLTHROUGH;
1307   case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
1308   case CallingConv::AMDGPU_LS: return R_00B528_SPI_SHADER_PGM_RSRC1_LS;
1309   case CallingConv::AMDGPU_HS: return R_00B428_SPI_SHADER_PGM_RSRC1_HS;
1310   case CallingConv::AMDGPU_ES: return R_00B328_SPI_SHADER_PGM_RSRC1_ES;
1311   case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
1312   case CallingConv::AMDGPU_VS: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
1313   case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
1314   }
1315 }
1316 
1317 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
1318                                          const SIProgramInfo &CurrentProgramInfo) {
1319   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1320   unsigned RsrcReg = getRsrcReg(MF.getFunction().getCallingConv());
1321 
1322   if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
1323     OutStreamer->emitInt32(R_00B848_COMPUTE_PGM_RSRC1);
1324 
1325     OutStreamer->emitInt32(CurrentProgramInfo.getComputePGMRSrc1());
1326 
1327     OutStreamer->emitInt32(R_00B84C_COMPUTE_PGM_RSRC2);
1328     OutStreamer->emitInt32(CurrentProgramInfo.ComputePGMRSrc2);
1329 
1330     OutStreamer->emitInt32(R_00B860_COMPUTE_TMPRING_SIZE);
1331     OutStreamer->emitInt32(S_00B860_WAVESIZE(CurrentProgramInfo.ScratchBlocks));
1332 
1333     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
1334     // 0" comment but I don't see a corresponding field in the register spec.
1335   } else {
1336     OutStreamer->emitInt32(RsrcReg);
1337     OutStreamer->emitIntValue(S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
1338                               S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks), 4);
1339     OutStreamer->emitInt32(R_0286E8_SPI_TMPRING_SIZE);
1340     OutStreamer->emitIntValue(
1341         S_0286E8_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
1342   }
1343 
1344   if (MF.getFunction().getCallingConv() == CallingConv::AMDGPU_PS) {
1345     OutStreamer->emitInt32(R_00B02C_SPI_SHADER_PGM_RSRC2_PS);
1346     OutStreamer->emitInt32(
1347         S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks));
1348     OutStreamer->emitInt32(R_0286CC_SPI_PS_INPUT_ENA);
1349     OutStreamer->emitInt32(MFI->getPSInputEnable());
1350     OutStreamer->emitInt32(R_0286D0_SPI_PS_INPUT_ADDR);
1351     OutStreamer->emitInt32(MFI->getPSInputAddr());
1352   }
1353 
1354   OutStreamer->emitInt32(R_SPILLED_SGPRS);
1355   OutStreamer->emitInt32(MFI->getNumSpilledSGPRs());
1356   OutStreamer->emitInt32(R_SPILLED_VGPRS);
1357   OutStreamer->emitInt32(MFI->getNumSpilledVGPRs());
1358 }
1359 
1360 // This is the equivalent of EmitProgramInfoSI above, but for when the OS type
1361 // is AMDPAL.  It stores each compute/SPI register setting and other PAL
1362 // metadata items into the PALMD::Metadata, combining with any provided by the
1363 // frontend as LLVM metadata. Once all functions are written, the PAL metadata
1364 // is then written as a single block in the .note section.
1365 void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
1366        const SIProgramInfo &CurrentProgramInfo) {
1367   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1368   auto CC = MF.getFunction().getCallingConv();
1369   auto MD = getTargetStreamer()->getPALMetadata();
1370 
1371   MD->setEntryPoint(CC, MF.getFunction().getName());
1372   MD->setNumUsedVgprs(CC, CurrentProgramInfo.NumVGPRsForWavesPerEU);
1373   MD->setNumUsedSgprs(CC, CurrentProgramInfo.NumSGPRsForWavesPerEU);
1374   MD->setRsrc1(CC, CurrentProgramInfo.getPGMRSrc1(CC));
1375   if (AMDGPU::isCompute(CC)) {
1376     MD->setRsrc2(CC, CurrentProgramInfo.ComputePGMRSrc2);
1377   } else {
1378     if (CurrentProgramInfo.ScratchBlocks > 0)
1379       MD->setRsrc2(CC, S_00B84C_SCRATCH_EN(1));
1380   }
1381   // ScratchSize is in bytes, 16 aligned.
1382   MD->setScratchSize(CC, alignTo(CurrentProgramInfo.ScratchSize, 16));
1383   if (MF.getFunction().getCallingConv() == CallingConv::AMDGPU_PS) {
1384     MD->setRsrc2(CC, S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks));
1385     MD->setSpiPsInputEna(MFI->getPSInputEnable());
1386     MD->setSpiPsInputAddr(MFI->getPSInputAddr());
1387   }
1388 
1389   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
1390   if (STM.isWave32())
1391     MD->setWave32(MF.getFunction().getCallingConv());
1392 }
1393 
1394 void AMDGPUAsmPrinter::emitPALFunctionMetadata(const MachineFunction &MF) {
1395   auto *MD = getTargetStreamer()->getPALMetadata();
1396   const MachineFrameInfo &MFI = MF.getFrameInfo();
1397   MD->setFunctionScratchSize(MF, MFI.getStackSize());
1398   // Set compute registers
1399   MD->setRsrc1(CallingConv::AMDGPU_CS,
1400                CurrentProgramInfo.getPGMRSrc1(CallingConv::AMDGPU_CS));
1401   MD->setRsrc2(CallingConv::AMDGPU_CS, CurrentProgramInfo.ComputePGMRSrc2);
1402 }
1403 
1404 // This is supposed to be log2(Size)
1405 static amd_element_byte_size_t getElementByteSizeValue(unsigned Size) {
1406   switch (Size) {
1407   case 4:
1408     return AMD_ELEMENT_4_BYTES;
1409   case 8:
1410     return AMD_ELEMENT_8_BYTES;
1411   case 16:
1412     return AMD_ELEMENT_16_BYTES;
1413   default:
1414     llvm_unreachable("invalid private_element_size");
1415   }
1416 }
1417 
1418 void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out,
1419                                         const SIProgramInfo &CurrentProgramInfo,
1420                                         const MachineFunction &MF) const {
1421   const Function &F = MF.getFunction();
1422   assert(F.getCallingConv() == CallingConv::AMDGPU_KERNEL ||
1423          F.getCallingConv() == CallingConv::SPIR_KERNEL);
1424 
1425   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1426   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
1427 
1428   AMDGPU::initDefaultAMDKernelCodeT(Out, &STM);
1429 
1430   Out.compute_pgm_resource_registers =
1431       CurrentProgramInfo.getComputePGMRSrc1() |
1432       (CurrentProgramInfo.ComputePGMRSrc2 << 32);
1433   Out.code_properties |= AMD_CODE_PROPERTY_IS_PTR64;
1434 
1435   if (CurrentProgramInfo.DynamicCallStack)
1436     Out.code_properties |= AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK;
1437 
1438   AMD_HSA_BITS_SET(Out.code_properties,
1439                    AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE,
1440                    getElementByteSizeValue(STM.getMaxPrivateElementSize(true)));
1441 
1442   if (MFI->hasPrivateSegmentBuffer()) {
1443     Out.code_properties |=
1444       AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
1445   }
1446 
1447   if (MFI->hasDispatchPtr())
1448     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
1449 
1450   if (MFI->hasQueuePtr())
1451     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
1452 
1453   if (MFI->hasKernargSegmentPtr())
1454     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
1455 
1456   if (MFI->hasDispatchID())
1457     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
1458 
1459   if (MFI->hasFlatScratchInit())
1460     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
1461 
1462   if (MFI->hasDispatchPtr())
1463     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
1464 
1465   if (STM.isXNACKEnabled())
1466     Out.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED;
1467 
1468   Align MaxKernArgAlign;
1469   Out.kernarg_segment_byte_size = STM.getKernArgSegmentSize(F, MaxKernArgAlign);
1470   Out.wavefront_sgpr_count = CurrentProgramInfo.NumSGPR;
1471   Out.workitem_vgpr_count = CurrentProgramInfo.NumVGPR;
1472   Out.workitem_private_segment_byte_size = CurrentProgramInfo.ScratchSize;
1473   Out.workgroup_group_segment_byte_size = CurrentProgramInfo.LDSSize;
1474 
1475   // kernarg_segment_alignment is specified as log of the alignment.
1476   // The minimum alignment is 16.
1477   Out.kernarg_segment_alignment = Log2(std::max(Align(16), MaxKernArgAlign));
1478 }
1479 
1480 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
1481                                        const char *ExtraCode, raw_ostream &O) {
1482   // First try the generic code, which knows about modifiers like 'c' and 'n'.
1483   if (!AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, O))
1484     return false;
1485 
1486   if (ExtraCode && ExtraCode[0]) {
1487     if (ExtraCode[1] != 0)
1488       return true; // Unknown modifier.
1489 
1490     switch (ExtraCode[0]) {
1491     case 'r':
1492       break;
1493     default:
1494       return true;
1495     }
1496   }
1497 
1498   // TODO: Should be able to support other operand types like globals.
1499   const MachineOperand &MO = MI->getOperand(OpNo);
1500   if (MO.isReg()) {
1501     AMDGPUInstPrinter::printRegOperand(MO.getReg(), O,
1502                                        *MF->getSubtarget().getRegisterInfo());
1503     return false;
1504   } else if (MO.isImm()) {
1505     int64_t Val = MO.getImm();
1506     if (AMDGPU::isInlinableIntLiteral(Val)) {
1507       O << Val;
1508     } else if (isUInt<16>(Val)) {
1509       O << format("0x%" PRIx16, static_cast<uint16_t>(Val));
1510     } else if (isUInt<32>(Val)) {
1511       O << format("0x%" PRIx32, static_cast<uint32_t>(Val));
1512     } else {
1513       O << format("0x%" PRIx64, static_cast<uint64_t>(Val));
1514     }
1515     return false;
1516   }
1517   return true;
1518 }
1519