1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
15 //
16 //===----------------------------------------------------------------------===//
17 //
18 
19 #include "AMDGPUAsmPrinter.h"
20 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
21 #include "InstPrinter/AMDGPUInstPrinter.h"
22 #include "Utils/AMDGPUBaseInfo.h"
23 #include "AMDGPU.h"
24 #include "AMDKernelCodeT.h"
25 #include "AMDGPUSubtarget.h"
26 #include "R600Defines.h"
27 #include "R600MachineFunctionInfo.h"
28 #include "R600RegisterInfo.h"
29 #include "SIDefines.h"
30 #include "SIMachineFunctionInfo.h"
31 #include "SIRegisterInfo.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/MC/MCContext.h"
34 #include "llvm/MC/MCSectionELF.h"
35 #include "llvm/MC/MCStreamer.h"
36 #include "llvm/Support/ELF.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/TargetRegistry.h"
39 #include "llvm/Target/TargetLoweringObjectFile.h"
40 
41 using namespace llvm;
42 
43 // TODO: This should get the default rounding mode from the kernel. We just set
44 // the default here, but this could change if the OpenCL rounding mode pragmas
45 // are used.
46 //
47 // The denormal mode here should match what is reported by the OpenCL runtime
48 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
49 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
50 //
51 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
52 // precision, and leaves single precision to flush all and does not report
53 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
54 // CL_FP_DENORM for both.
55 //
56 // FIXME: It seems some instructions do not support single precision denormals
57 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
58 // and sin_f32, cos_f32 on most parts).
59 
60 // We want to use these instructions, and using fp32 denormals also causes
61 // instructions to run at the double precision rate for the device so it's
62 // probably best to just report no single precision denormals.
63 static uint32_t getFPMode(const MachineFunction &F) {
64   const AMDGPUSubtarget& ST = F.getSubtarget<AMDGPUSubtarget>();
65   // TODO: Is there any real use for the flush in only / flush out only modes?
66 
67   uint32_t FP32Denormals =
68     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
69 
70   uint32_t FP64Denormals =
71     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
72 
73   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
74          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
75          FP_DENORM_MODE_SP(FP32Denormals) |
76          FP_DENORM_MODE_DP(FP64Denormals);
77 }
78 
79 static AsmPrinter *
80 createAMDGPUAsmPrinterPass(TargetMachine &tm,
81                            std::unique_ptr<MCStreamer> &&Streamer) {
82   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
83 }
84 
85 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
86   TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
87   TargetRegistry::RegisterAsmPrinter(TheGCNTarget, createAMDGPUAsmPrinterPass);
88 }
89 
90 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
91                                    std::unique_ptr<MCStreamer> Streamer)
92     : AsmPrinter(TM, std::move(Streamer)) {}
93 
94 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
95   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
96   SIProgramInfo KernelInfo;
97   if (STM.isAmdHsaOS()) {
98     getSIProgramInfo(KernelInfo, *MF);
99     EmitAmdKernelCodeT(*MF, KernelInfo);
100   }
101 }
102 
103 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
104 
105   // This label is used to mark the end of the .text section.
106   const TargetLoweringObjectFile &TLOF = getObjFileLowering();
107   OutStreamer->SwitchSection(TLOF.getTextSection());
108   MCSymbol *EndOfTextLabel =
109       OutContext.getOrCreateSymbol(StringRef(END_OF_TEXT_LABEL_NAME));
110   OutStreamer->EmitLabel(EndOfTextLabel);
111 }
112 
113 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
114   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
115   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
116   if (MFI->isKernel() && STM.isAmdHsaOS()) {
117     AMDGPUTargetStreamer *TS =
118         static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
119     TS->EmitAMDGPUSymbolType(CurrentFnSym->getName(),
120                              ELF::STT_AMDGPU_HSA_KERNEL);
121   }
122 
123   AsmPrinter::EmitFunctionEntryLabel();
124 }
125 
126 static bool isModuleLinkage(const GlobalValue *GV) {
127   switch (GV->getLinkage()) {
128   case GlobalValue::InternalLinkage:
129   case GlobalValue::CommonLinkage:
130    return true;
131   case GlobalValue::ExternalLinkage:
132    return false;
133   default: llvm_unreachable("unknown linkage type");
134   }
135 }
136 
137 void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
138 
139   if (TM.getTargetTriple().getOS() != Triple::AMDHSA ||
140       GV->isDeclaration()) {
141     AsmPrinter::EmitGlobalVariable(GV);
142     return;
143   }
144 
145   // Group segment variables aren't emitted in HSA.
146   if (AMDGPU::isGroupSegment(GV))
147     return;
148 
149   AMDGPUTargetStreamer *TS =
150       static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
151   if (isModuleLinkage(GV)) {
152     TS->EmitAMDGPUHsaModuleScopeGlobal(GV->getName());
153   } else {
154     TS->EmitAMDGPUHsaProgramScopeGlobal(GV->getName());
155   }
156 
157   const DataLayout &DL = getDataLayout();
158   OutStreamer->PushSection();
159   OutStreamer->SwitchSection(
160       getObjFileLowering().SectionForGlobal(GV, *Mang, TM));
161   MCSymbol *GVSym = getSymbol(GV);
162   const Constant *C = GV->getInitializer();
163   OutStreamer->EmitLabel(GVSym);
164   EmitGlobalConstant(DL, C);
165   OutStreamer->PopSection();
166 }
167 
168 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
169 
170   // The starting address of all shader programs must be 256 bytes aligned.
171   MF.setAlignment(8);
172 
173   SetupMachineFunction(MF);
174 
175   MCContext &Context = getObjFileLowering().getContext();
176   MCSectionELF *ConfigSection =
177       Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
178   OutStreamer->SwitchSection(ConfigSection);
179 
180   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
181   SIProgramInfo KernelInfo;
182   if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
183     getSIProgramInfo(KernelInfo, MF);
184     if (!STM.isAmdHsaOS()) {
185       EmitProgramInfoSI(MF, KernelInfo);
186     }
187     // Emit directives
188     AMDGPUTargetStreamer *TS =
189         static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
190     TS->EmitDirectiveHSACodeObjectVersion(1, 0);
191     AMDGPU::IsaVersion ISA = STM.getIsaVersion();
192     TS->EmitDirectiveHSACodeObjectISA(ISA.Major, ISA.Minor, ISA.Stepping,
193                                       "AMD", "AMDGPU");
194   } else {
195     EmitProgramInfoR600(MF);
196   }
197 
198   DisasmLines.clear();
199   HexLines.clear();
200   DisasmLineMaxLen = 0;
201 
202   EmitFunctionBody();
203 
204   if (isVerbose()) {
205     MCSectionELF *CommentSection =
206         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
207     OutStreamer->SwitchSection(CommentSection);
208 
209     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
210       OutStreamer->emitRawComment(" Kernel info:", false);
211       OutStreamer->emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
212                                   false);
213       OutStreamer->emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
214                                   false);
215       OutStreamer->emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
216                                   false);
217       OutStreamer->emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
218                                   false);
219       OutStreamer->emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
220                                   false);
221       OutStreamer->emitRawComment(" ScratchSize: " + Twine(KernelInfo.ScratchSize),
222                                   false);
223 
224       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:USER_SGPR: " +
225                                   Twine(G_00B84C_USER_SGPR(KernelInfo.ComputePGMRSrc2)),
226                                   false);
227       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_X_EN: " +
228                                   Twine(G_00B84C_TGID_X_EN(KernelInfo.ComputePGMRSrc2)),
229                                   false);
230       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
231                                   Twine(G_00B84C_TGID_Y_EN(KernelInfo.ComputePGMRSrc2)),
232                                   false);
233       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
234                                   Twine(G_00B84C_TGID_Z_EN(KernelInfo.ComputePGMRSrc2)),
235                                   false);
236       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
237                                   Twine(G_00B84C_TIDIG_COMP_CNT(KernelInfo.ComputePGMRSrc2)),
238                                   false);
239 
240     } else {
241       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
242       OutStreamer->emitRawComment(
243         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
244     }
245   }
246 
247   if (STM.dumpCode()) {
248 
249     OutStreamer->SwitchSection(
250         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
251 
252     for (size_t i = 0; i < DisasmLines.size(); ++i) {
253       std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
254       Comment += " ; " + HexLines[i] + "\n";
255 
256       OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
257       OutStreamer->EmitBytes(StringRef(Comment));
258     }
259   }
260 
261   return false;
262 }
263 
264 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
265   unsigned MaxGPR = 0;
266   bool killPixel = false;
267   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
268   const R600RegisterInfo *RI =
269       static_cast<const R600RegisterInfo *>(STM.getRegisterInfo());
270   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
271 
272   for (const MachineBasicBlock &MBB : MF) {
273     for (const MachineInstr &MI : MBB) {
274       if (MI.getOpcode() == AMDGPU::KILLGT)
275         killPixel = true;
276       unsigned numOperands = MI.getNumOperands();
277       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
278         const MachineOperand &MO = MI.getOperand(op_idx);
279         if (!MO.isReg())
280           continue;
281         unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
282 
283         // Register with value > 127 aren't GPR
284         if (HWReg > 127)
285           continue;
286         MaxGPR = std::max(MaxGPR, HWReg);
287       }
288     }
289   }
290 
291   unsigned RsrcReg;
292   if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
293     // Evergreen / Northern Islands
294     switch (MFI->getShaderType()) {
295     default: // Fall through
296     case ShaderType::COMPUTE:  RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
297     case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
298     case ShaderType::PIXEL:    RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
299     case ShaderType::VERTEX:   RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
300     }
301   } else {
302     // R600 / R700
303     switch (MFI->getShaderType()) {
304     default: // Fall through
305     case ShaderType::GEOMETRY: // Fall through
306     case ShaderType::COMPUTE:  // Fall through
307     case ShaderType::VERTEX:   RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
308     case ShaderType::PIXEL:    RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
309     }
310   }
311 
312   OutStreamer->EmitIntValue(RsrcReg, 4);
313   OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
314                            S_STACK_SIZE(MFI->StackSize), 4);
315   OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
316   OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
317 
318   if (MFI->getShaderType() == ShaderType::COMPUTE) {
319     OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
320     OutStreamer->EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
321   }
322 }
323 
324 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
325                                         const MachineFunction &MF) const {
326   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
327   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
328   uint64_t CodeSize = 0;
329   unsigned MaxSGPR = 0;
330   unsigned MaxVGPR = 0;
331   bool VCCUsed = false;
332   bool FlatUsed = false;
333   const SIRegisterInfo *RI =
334       static_cast<const SIRegisterInfo *>(STM.getRegisterInfo());
335 
336   for (const MachineBasicBlock &MBB : MF) {
337     for (const MachineInstr &MI : MBB) {
338       // TODO: CodeSize should account for multiple functions.
339 
340       // TODO: Should we count size of debug info?
341       if (MI.isDebugValue())
342         continue;
343 
344       // FIXME: This is reporting 0 for many instructions.
345       CodeSize += MI.getDesc().Size;
346 
347       unsigned numOperands = MI.getNumOperands();
348       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
349         const MachineOperand &MO = MI.getOperand(op_idx);
350         unsigned width = 0;
351         bool isSGPR = false;
352 
353         if (!MO.isReg())
354           continue;
355 
356         unsigned reg = MO.getReg();
357         switch (reg) {
358         case AMDGPU::EXEC:
359         case AMDGPU::SCC:
360         case AMDGPU::M0:
361           continue;
362 
363         case AMDGPU::VCC:
364         case AMDGPU::VCC_LO:
365         case AMDGPU::VCC_HI:
366           VCCUsed = true;
367           continue;
368 
369         case AMDGPU::FLAT_SCR:
370         case AMDGPU::FLAT_SCR_LO:
371         case AMDGPU::FLAT_SCR_HI:
372           FlatUsed = true;
373           continue;
374 
375         default:
376           break;
377         }
378 
379         if (AMDGPU::SReg_32RegClass.contains(reg)) {
380           isSGPR = true;
381           width = 1;
382         } else if (AMDGPU::VGPR_32RegClass.contains(reg)) {
383           isSGPR = false;
384           width = 1;
385         } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
386           isSGPR = true;
387           width = 2;
388         } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
389           isSGPR = false;
390           width = 2;
391         } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
392           isSGPR = false;
393           width = 3;
394         } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
395           isSGPR = true;
396           width = 4;
397         } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
398           isSGPR = false;
399           width = 4;
400         } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
401           isSGPR = true;
402           width = 8;
403         } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
404           isSGPR = false;
405           width = 8;
406         } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
407           isSGPR = true;
408           width = 16;
409         } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
410           isSGPR = false;
411           width = 16;
412         } else {
413           llvm_unreachable("Unknown register class");
414         }
415         unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
416         unsigned maxUsed = hwReg + width - 1;
417         if (isSGPR) {
418           MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
419         } else {
420           MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
421         }
422       }
423     }
424   }
425 
426   if (VCCUsed)
427     MaxSGPR += 2;
428 
429   if (FlatUsed)
430     MaxSGPR += 2;
431 
432   // We found the maximum register index. They start at 0, so add one to get the
433   // number of registers.
434   ProgInfo.NumVGPR = MaxVGPR + 1;
435   ProgInfo.NumSGPR = MaxSGPR + 1;
436 
437   if (STM.hasSGPRInitBug()) {
438     if (ProgInfo.NumSGPR > AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG) {
439       LLVMContext &Ctx = MF.getFunction()->getContext();
440       Ctx.emitError("too many SGPRs used with the SGPR init bug");
441     }
442 
443     ProgInfo.NumSGPR = AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG;
444   }
445 
446   if (MFI->NumUserSGPRs > STM.getMaxNumUserSGPRs()) {
447     LLVMContext &Ctx = MF.getFunction()->getContext();
448     Ctx.emitError("too many user SGPRs used");
449   }
450 
451   ProgInfo.VGPRBlocks = (ProgInfo.NumVGPR - 1) / 4;
452   ProgInfo.SGPRBlocks = (ProgInfo.NumSGPR - 1) / 8;
453   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
454   // register.
455   ProgInfo.FloatMode = getFPMode(MF);
456 
457   // XXX: Not quite sure what this does, but sc seems to unset this.
458   ProgInfo.IEEEMode = 0;
459 
460   // Do not clamp NAN to 0.
461   ProgInfo.DX10Clamp = 0;
462 
463   const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
464   ProgInfo.ScratchSize = FrameInfo->estimateStackSize(MF);
465 
466   ProgInfo.FlatUsed = FlatUsed;
467   ProgInfo.VCCUsed = VCCUsed;
468   ProgInfo.CodeLen = CodeSize;
469 
470   unsigned LDSAlignShift;
471   if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
472     // LDS is allocated in 64 dword blocks.
473     LDSAlignShift = 8;
474   } else {
475     // LDS is allocated in 128 dword blocks.
476     LDSAlignShift = 9;
477   }
478 
479   unsigned LDSSpillSize = MFI->LDSWaveSpillSize *
480                           MFI->getMaximumWorkGroupSize(MF);
481 
482   ProgInfo.LDSSize = MFI->LDSSize + LDSSpillSize;
483   ProgInfo.LDSBlocks =
484      RoundUpToAlignment(ProgInfo.LDSSize, 1 << LDSAlignShift) >> LDSAlignShift;
485 
486   // Scratch is allocated in 256 dword blocks.
487   unsigned ScratchAlignShift = 10;
488   // We need to program the hardware with the amount of scratch memory that
489   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
490   // scratch memory used per thread.
491   ProgInfo.ScratchBlocks =
492     RoundUpToAlignment(ProgInfo.ScratchSize * STM.getWavefrontSize(),
493                        1 << ScratchAlignShift) >> ScratchAlignShift;
494 
495   ProgInfo.ComputePGMRSrc1 =
496       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
497       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
498       S_00B848_PRIORITY(ProgInfo.Priority) |
499       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
500       S_00B848_PRIV(ProgInfo.Priv) |
501       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
502       S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
503       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
504 
505   // 0 = X, 1 = XY, 2 = XYZ
506   unsigned TIDIGCompCnt = 0;
507   if (MFI->hasWorkItemIDZ())
508     TIDIGCompCnt = 2;
509   else if (MFI->hasWorkItemIDY())
510     TIDIGCompCnt = 1;
511 
512   ProgInfo.ComputePGMRSrc2 =
513       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
514       S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
515       S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
516       S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
517       S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
518       S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
519       S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
520       S_00B84C_EXCP_EN_MSB(0) |
521       S_00B84C_LDS_SIZE(ProgInfo.LDSBlocks) |
522       S_00B84C_EXCP_EN(0);
523 }
524 
525 static unsigned getRsrcReg(unsigned ShaderType) {
526   switch (ShaderType) {
527   default: // Fall through
528   case ShaderType::COMPUTE:  return R_00B848_COMPUTE_PGM_RSRC1;
529   case ShaderType::GEOMETRY: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
530   case ShaderType::PIXEL:    return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
531   case ShaderType::VERTEX:   return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
532   }
533 }
534 
535 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
536                                          const SIProgramInfo &KernelInfo) {
537   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
538   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
539   unsigned RsrcReg = getRsrcReg(MFI->getShaderType());
540 
541   if (MFI->getShaderType() == ShaderType::COMPUTE) {
542     OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
543 
544     OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc1, 4);
545 
546     OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
547     OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc2, 4);
548 
549     OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
550     OutStreamer->EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4);
551 
552     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
553     // 0" comment but I don't see a corresponding field in the register spec.
554   } else {
555     OutStreamer->EmitIntValue(RsrcReg, 4);
556     OutStreamer->EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
557                               S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4);
558     if (STM.isVGPRSpillingEnabled(MFI)) {
559       OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
560       OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(KernelInfo.ScratchBlocks), 4);
561     }
562   }
563 
564   if (MFI->getShaderType() == ShaderType::PIXEL) {
565     OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
566     OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4);
567     OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
568     OutStreamer->EmitIntValue(MFI->PSInputAddr, 4);
569   }
570 }
571 
572 void AMDGPUAsmPrinter::EmitAmdKernelCodeT(const MachineFunction &MF,
573                                          const SIProgramInfo &KernelInfo) const {
574   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
575   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
576   amd_kernel_code_t header;
577 
578   AMDGPU::initDefaultAMDKernelCodeT(header, STM.getFeatureBits());
579 
580   header.compute_pgm_resource_registers =
581       KernelInfo.ComputePGMRSrc1 |
582       (KernelInfo.ComputePGMRSrc2 << 32);
583   header.code_properties = AMD_CODE_PROPERTY_IS_PTR64;
584 
585   if (MFI->hasPrivateSegmentBuffer()) {
586     header.code_properties |=
587       AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
588   }
589 
590   if (MFI->hasDispatchPtr())
591     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
592 
593   if (MFI->hasQueuePtr())
594     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
595 
596   if (MFI->hasKernargSegmentPtr())
597     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
598 
599   if (MFI->hasDispatchID())
600     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
601 
602   if (MFI->hasFlatScratchInit())
603     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
604 
605   // TODO: Private segment size
606 
607   if (MFI->hasGridWorkgroupCountX()) {
608     header.code_properties |=
609       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X;
610   }
611 
612   if (MFI->hasGridWorkgroupCountY()) {
613     header.code_properties |=
614       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y;
615   }
616 
617   if (MFI->hasGridWorkgroupCountZ()) {
618     header.code_properties |=
619       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z;
620   }
621 
622   if (MFI->hasDispatchPtr())
623     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
624 
625   header.kernarg_segment_byte_size = MFI->ABIArgOffset;
626   header.wavefront_sgpr_count = KernelInfo.NumSGPR;
627   header.workitem_vgpr_count = KernelInfo.NumVGPR;
628 
629   AMDGPUTargetStreamer *TS =
630       static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
631   TS->EmitAMDKernelCodeT(header);
632 }
633 
634 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
635                                        unsigned AsmVariant,
636                                        const char *ExtraCode, raw_ostream &O) {
637   if (ExtraCode && ExtraCode[0]) {
638     if (ExtraCode[1] != 0)
639       return true; // Unknown modifier.
640 
641     switch (ExtraCode[0]) {
642     default:
643       // See if this is a generic print operand
644       return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
645     case 'r':
646       break;
647     }
648   }
649 
650   AMDGPUInstPrinter::printRegOperand(MI->getOperand(OpNo).getReg(), O,
651                    *TM.getSubtargetImpl(*MF->getFunction())->getRegisterInfo());
652   return false;
653 }
654