1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
15 //
16 //===----------------------------------------------------------------------===//
17 //
18 
19 #include "AMDGPUAsmPrinter.h"
20 #include "AMDGPU.h"
21 #include "AMDGPUSubtarget.h"
22 #include "AMDGPUTargetMachine.h"
23 #include "InstPrinter/AMDGPUInstPrinter.h"
24 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
25 #include "R600Defines.h"
26 #include "R600MachineFunctionInfo.h"
27 #include "R600RegisterInfo.h"
28 #include "SIDefines.h"
29 #include "SIInstrInfo.h"
30 #include "SIMachineFunctionInfo.h"
31 #include "SIRegisterInfo.h"
32 #include "Utils/AMDGPUBaseInfo.h"
33 #include "llvm/BinaryFormat/ELF.h"
34 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/IR/DiagnosticInfo.h"
36 #include "llvm/MC/MCContext.h"
37 #include "llvm/MC/MCSectionELF.h"
38 #include "llvm/MC/MCStreamer.h"
39 #include "llvm/Support/AMDGPUMetadata.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Target/TargetLoweringObjectFile.h"
43 
44 using namespace llvm;
45 using namespace llvm::AMDGPU;
46 
47 // TODO: This should get the default rounding mode from the kernel. We just set
48 // the default here, but this could change if the OpenCL rounding mode pragmas
49 // are used.
50 //
51 // The denormal mode here should match what is reported by the OpenCL runtime
52 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
53 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
54 //
55 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
56 // precision, and leaves single precision to flush all and does not report
57 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
58 // CL_FP_DENORM for both.
59 //
60 // FIXME: It seems some instructions do not support single precision denormals
61 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
62 // and sin_f32, cos_f32 on most parts).
63 
64 // We want to use these instructions, and using fp32 denormals also causes
65 // instructions to run at the double precision rate for the device so it's
66 // probably best to just report no single precision denormals.
67 static uint32_t getFPMode(const MachineFunction &F) {
68   const SISubtarget& ST = F.getSubtarget<SISubtarget>();
69   // TODO: Is there any real use for the flush in only / flush out only modes?
70 
71   uint32_t FP32Denormals =
72     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
73 
74   uint32_t FP64Denormals =
75     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
76 
77   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
78          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
79          FP_DENORM_MODE_SP(FP32Denormals) |
80          FP_DENORM_MODE_DP(FP64Denormals);
81 }
82 
83 static AsmPrinter *
84 createAMDGPUAsmPrinterPass(TargetMachine &tm,
85                            std::unique_ptr<MCStreamer> &&Streamer) {
86   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
87 }
88 
89 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
90   TargetRegistry::RegisterAsmPrinter(getTheAMDGPUTarget(),
91                                      createAMDGPUAsmPrinterPass);
92   TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(),
93                                      createAMDGPUAsmPrinterPass);
94 }
95 
96 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
97                                    std::unique_ptr<MCStreamer> Streamer)
98   : AsmPrinter(TM, std::move(Streamer)) {
99     AMDGPUASI = static_cast<AMDGPUTargetMachine*>(&TM)->getAMDGPUAS();
100   }
101 
102 StringRef AMDGPUAsmPrinter::getPassName() const {
103   return "AMDGPU Assembly Printer";
104 }
105 
106 const MCSubtargetInfo* AMDGPUAsmPrinter::getSTI() const {
107   return TM.getMCSubtargetInfo();
108 }
109 
110 AMDGPUTargetStreamer* AMDGPUAsmPrinter::getTargetStreamer() const {
111   if (!OutStreamer)
112     return nullptr;
113   return static_cast<AMDGPUTargetStreamer*>(OutStreamer->getTargetStreamer());
114 }
115 
116 void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) {
117   if (TM.getTargetTriple().getArch() != Triple::amdgcn)
118     return;
119 
120   if (TM.getTargetTriple().getOS() != Triple::AMDHSA &&
121       TM.getTargetTriple().getOS() != Triple::AMDPAL)
122     return;
123 
124   if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
125     HSAMetadataStream.begin(M);
126 
127   if (TM.getTargetTriple().getOS() == Triple::AMDPAL)
128     readPALMetadata(M);
129 
130   // Deprecated notes are not emitted for code object v3.
131   if (IsaInfo::hasCodeObjectV3(getSTI()->getFeatureBits()))
132     return;
133 
134   // HSA emits NT_AMDGPU_HSA_CODE_OBJECT_VERSION for code objects v2.
135   if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
136     getTargetStreamer()->EmitDirectiveHSACodeObjectVersion(2, 1);
137 
138   // HSA and PAL emit NT_AMDGPU_HSA_ISA for code objects v2.
139   IsaInfo::IsaVersion ISA = IsaInfo::getIsaVersion(getSTI()->getFeatureBits());
140   getTargetStreamer()->EmitDirectiveHSACodeObjectISA(
141       ISA.Major, ISA.Minor, ISA.Stepping, "AMD", "AMDGPU");
142 }
143 
144 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
145   if (TM.getTargetTriple().getArch() != Triple::amdgcn)
146     return;
147 
148   // Following code requires TargetStreamer to be present.
149   if (!getTargetStreamer())
150     return;
151 
152   // Emit ISA Version (NT_AMD_AMDGPU_ISA).
153   std::string ISAVersionString;
154   raw_string_ostream ISAVersionStream(ISAVersionString);
155   IsaInfo::streamIsaVersion(getSTI(), ISAVersionStream);
156   getTargetStreamer()->EmitISAVersion(ISAVersionStream.str());
157 
158   // Emit HSA Metadata (NT_AMD_AMDGPU_HSA_METADATA).
159   if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
160     HSAMetadataStream.end();
161     getTargetStreamer()->EmitHSAMetadata(HSAMetadataStream.getHSAMetadata());
162   }
163 
164   // Emit PAL Metadata (NT_AMD_AMDGPU_PAL_METADATA).
165   if (TM.getTargetTriple().getOS() == Triple::AMDPAL) {
166     // Copy the PAL metadata from the map where we collected it into a vector,
167     // then write it as a .note.
168     PALMD::Metadata PALMetadataVector;
169     for (auto i : PALMetadataMap) {
170       PALMetadataVector.push_back(i.first);
171       PALMetadataVector.push_back(i.second);
172     }
173     getTargetStreamer()->EmitPALMetadata(PALMetadataVector);
174   }
175 }
176 
177 bool AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough(
178   const MachineBasicBlock *MBB) const {
179   if (!AsmPrinter::isBlockOnlyReachableByFallthrough(MBB))
180     return false;
181 
182   if (MBB->empty())
183     return true;
184 
185   // If this is a block implementing a long branch, an expression relative to
186   // the start of the block is needed.  to the start of the block.
187   // XXX - Is there a smarter way to check this?
188   return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
189 }
190 
191 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
192   const AMDGPUMachineFunction *MFI = MF->getInfo<AMDGPUMachineFunction>();
193   if (!MFI->isEntryFunction())
194     return;
195 
196   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
197   amd_kernel_code_t KernelCode;
198   if (STM.isAmdCodeObjectV2(*MF)) {
199     getAmdKernelCode(KernelCode, CurrentProgramInfo, *MF);
200     getTargetStreamer()->EmitAMDKernelCodeT(KernelCode);
201   }
202 
203   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
204     return;
205 
206   HSAMetadataStream.emitKernel(MF->getFunction(),
207                                getHSACodeProps(*MF, CurrentProgramInfo),
208                                getHSADebugProps(*MF, CurrentProgramInfo));
209 }
210 
211 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
212   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
213   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
214   if (MFI->isEntryFunction() && STM.isAmdCodeObjectV2(*MF)) {
215     SmallString<128> SymbolName;
216     getNameWithPrefix(SymbolName, &MF->getFunction()),
217     getTargetStreamer()->EmitAMDGPUSymbolType(
218         SymbolName, ELF::STT_AMDGPU_HSA_KERNEL);
219   }
220   const AMDGPUSubtarget &STI = MF->getSubtarget<AMDGPUSubtarget>();
221   if (STI.dumpCode()) {
222     // Disassemble function name label to text.
223     DisasmLines.push_back(MF->getName().str() + ":");
224     DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size());
225     HexLines.push_back("");
226   }
227 
228   AsmPrinter::EmitFunctionEntryLabel();
229 }
230 
231 void AMDGPUAsmPrinter::EmitBasicBlockStart(const MachineBasicBlock &MBB) const {
232   const AMDGPUSubtarget &STI = MBB.getParent()->getSubtarget<AMDGPUSubtarget>();
233   if (STI.dumpCode() && !isBlockOnlyReachableByFallthrough(&MBB)) {
234     // Write a line for the basic block label if it is not only fallthrough.
235     DisasmLines.push_back(
236         (Twine("BB") + Twine(getFunctionNumber())
237          + "_" + Twine(MBB.getNumber()) + ":").str());
238     DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size());
239     HexLines.push_back("");
240   }
241   AsmPrinter::EmitBasicBlockStart(MBB);
242 }
243 
244 void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
245 
246   // Group segment variables aren't emitted in HSA.
247   if (AMDGPU::isGroupSegment(GV))
248     return;
249 
250   AsmPrinter::EmitGlobalVariable(GV);
251 }
252 
253 bool AMDGPUAsmPrinter::doFinalization(Module &M) {
254   CallGraphResourceInfo.clear();
255   return AsmPrinter::doFinalization(M);
256 }
257 
258 // For the amdpal OS type, read the amdgpu.pal.metadata supplied by the
259 // frontend into our PALMetadataMap, ready for per-function modification.  It
260 // is a NamedMD containing an MDTuple containing a number of MDNodes each of
261 // which is an integer value, and each two integer values forms a key=value
262 // pair that we store as PALMetadataMap[key]=value in the map.
263 void AMDGPUAsmPrinter::readPALMetadata(Module &M) {
264   auto NamedMD = M.getNamedMetadata("amdgpu.pal.metadata");
265   if (!NamedMD || !NamedMD->getNumOperands())
266     return;
267   auto Tuple = dyn_cast<MDTuple>(NamedMD->getOperand(0));
268   if (!Tuple)
269     return;
270   for (unsigned I = 0, E = Tuple->getNumOperands() & -2; I != E; I += 2) {
271     auto Key = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I));
272     auto Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I + 1));
273     if (!Key || !Val)
274       continue;
275     PALMetadataMap[Key->getZExtValue()] = Val->getZExtValue();
276   }
277 }
278 
279 // Print comments that apply to both callable functions and entry points.
280 void AMDGPUAsmPrinter::emitCommonFunctionComments(
281   uint32_t NumVGPR,
282   uint32_t NumSGPR,
283   uint64_t ScratchSize,
284   uint64_t CodeSize) {
285   OutStreamer->emitRawComment(" codeLenInByte = " + Twine(CodeSize), false);
286   OutStreamer->emitRawComment(" NumSgprs: " + Twine(NumSGPR), false);
287   OutStreamer->emitRawComment(" NumVgprs: " + Twine(NumVGPR), false);
288   OutStreamer->emitRawComment(" ScratchSize: " + Twine(ScratchSize), false);
289 }
290 
291 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
292   CurrentProgramInfo = SIProgramInfo();
293 
294   const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
295 
296   // The starting address of all shader programs must be 256 bytes aligned.
297   // Regular functions just need the basic required instruction alignment.
298   MF.setAlignment(MFI->isEntryFunction() ? 8 : 2);
299 
300   SetupMachineFunction(MF);
301 
302   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
303   MCContext &Context = getObjFileLowering().getContext();
304   // FIXME: This should be an explicit check for Mesa.
305   if (!STM.isAmdHsaOS() && !STM.isAmdPalOS()) {
306     MCSectionELF *ConfigSection =
307         Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
308     OutStreamer->SwitchSection(ConfigSection);
309   }
310 
311   if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
312     if (MFI->isEntryFunction()) {
313       getSIProgramInfo(CurrentProgramInfo, MF);
314     } else {
315       auto I = CallGraphResourceInfo.insert(
316         std::make_pair(&MF.getFunction(), SIFunctionResourceInfo()));
317       SIFunctionResourceInfo &Info = I.first->second;
318       assert(I.second && "should only be called once per function");
319       Info = analyzeResourceUsage(MF);
320     }
321 
322     if (STM.isAmdPalOS())
323       EmitPALMetadata(MF, CurrentProgramInfo);
324     else if (!STM.isAmdHsaOS()) {
325       EmitProgramInfoSI(MF, CurrentProgramInfo);
326     }
327   } else {
328     EmitProgramInfoR600(MF);
329   }
330 
331   DisasmLines.clear();
332   HexLines.clear();
333   DisasmLineMaxLen = 0;
334 
335   EmitFunctionBody();
336 
337   if (isVerbose()) {
338     MCSectionELF *CommentSection =
339         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
340     OutStreamer->SwitchSection(CommentSection);
341 
342     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
343       if (!MFI->isEntryFunction()) {
344         OutStreamer->emitRawComment(" Function info:", false);
345         SIFunctionResourceInfo &Info = CallGraphResourceInfo[&MF.getFunction()];
346         emitCommonFunctionComments(
347           Info.NumVGPR,
348           Info.getTotalNumSGPRs(MF.getSubtarget<SISubtarget>()),
349           Info.PrivateSegmentSize,
350           getFunctionCodeSize(MF));
351         return false;
352       }
353 
354       OutStreamer->emitRawComment(" Kernel info:", false);
355       emitCommonFunctionComments(CurrentProgramInfo.NumVGPR,
356                                  CurrentProgramInfo.NumSGPR,
357                                  CurrentProgramInfo.ScratchSize,
358                                  getFunctionCodeSize(MF));
359 
360       OutStreamer->emitRawComment(
361         " FloatMode: " + Twine(CurrentProgramInfo.FloatMode), false);
362       OutStreamer->emitRawComment(
363         " IeeeMode: " + Twine(CurrentProgramInfo.IEEEMode), false);
364       OutStreamer->emitRawComment(
365         " LDSByteSize: " + Twine(CurrentProgramInfo.LDSSize) +
366         " bytes/workgroup (compile time only)", false);
367 
368       OutStreamer->emitRawComment(
369         " SGPRBlocks: " + Twine(CurrentProgramInfo.SGPRBlocks), false);
370       OutStreamer->emitRawComment(
371         " VGPRBlocks: " + Twine(CurrentProgramInfo.VGPRBlocks), false);
372 
373       OutStreamer->emitRawComment(
374         " NumSGPRsForWavesPerEU: " +
375         Twine(CurrentProgramInfo.NumSGPRsForWavesPerEU), false);
376       OutStreamer->emitRawComment(
377         " NumVGPRsForWavesPerEU: " +
378         Twine(CurrentProgramInfo.NumVGPRsForWavesPerEU), false);
379 
380       OutStreamer->emitRawComment(
381         " ReservedVGPRFirst: " + Twine(CurrentProgramInfo.ReservedVGPRFirst),
382         false);
383       OutStreamer->emitRawComment(
384         " ReservedVGPRCount: " + Twine(CurrentProgramInfo.ReservedVGPRCount),
385         false);
386 
387       if (MF.getSubtarget<SISubtarget>().debuggerEmitPrologue()) {
388         OutStreamer->emitRawComment(
389           " DebuggerWavefrontPrivateSegmentOffsetSGPR: s" +
390           Twine(CurrentProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR), false);
391         OutStreamer->emitRawComment(
392           " DebuggerPrivateSegmentBufferSGPR: s" +
393           Twine(CurrentProgramInfo.DebuggerPrivateSegmentBufferSGPR), false);
394       }
395 
396       OutStreamer->emitRawComment(
397         " COMPUTE_PGM_RSRC2:USER_SGPR: " +
398         Twine(G_00B84C_USER_SGPR(CurrentProgramInfo.ComputePGMRSrc2)), false);
399       OutStreamer->emitRawComment(
400         " COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
401         Twine(G_00B84C_TRAP_HANDLER(CurrentProgramInfo.ComputePGMRSrc2)), false);
402       OutStreamer->emitRawComment(
403         " COMPUTE_PGM_RSRC2:TGID_X_EN: " +
404         Twine(G_00B84C_TGID_X_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
405       OutStreamer->emitRawComment(
406         " COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
407         Twine(G_00B84C_TGID_Y_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
408       OutStreamer->emitRawComment(
409         " COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
410         Twine(G_00B84C_TGID_Z_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
411       OutStreamer->emitRawComment(
412         " COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
413         Twine(G_00B84C_TIDIG_COMP_CNT(CurrentProgramInfo.ComputePGMRSrc2)),
414         false);
415     } else {
416       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
417       OutStreamer->emitRawComment(
418         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->CFStackSize)));
419     }
420   }
421 
422   if (STM.dumpCode()) {
423 
424     OutStreamer->SwitchSection(
425         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
426 
427     for (size_t i = 0; i < DisasmLines.size(); ++i) {
428       std::string Comment = "\n";
429       if (!HexLines[i].empty()) {
430         Comment = std::string(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
431         Comment += " ; " + HexLines[i] + "\n";
432       }
433 
434       OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
435       OutStreamer->EmitBytes(StringRef(Comment));
436     }
437   }
438 
439   return false;
440 }
441 
442 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
443   unsigned MaxGPR = 0;
444   bool killPixel = false;
445   const R600Subtarget &STM = MF.getSubtarget<R600Subtarget>();
446   const R600RegisterInfo *RI = STM.getRegisterInfo();
447   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
448 
449   for (const MachineBasicBlock &MBB : MF) {
450     for (const MachineInstr &MI : MBB) {
451       if (MI.getOpcode() == AMDGPU::KILLGT)
452         killPixel = true;
453       unsigned numOperands = MI.getNumOperands();
454       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
455         const MachineOperand &MO = MI.getOperand(op_idx);
456         if (!MO.isReg())
457           continue;
458         unsigned HWReg = RI->getHWRegIndex(MO.getReg());
459 
460         // Register with value > 127 aren't GPR
461         if (HWReg > 127)
462           continue;
463         MaxGPR = std::max(MaxGPR, HWReg);
464       }
465     }
466   }
467 
468   unsigned RsrcReg;
469   if (STM.getGeneration() >= R600Subtarget::EVERGREEN) {
470     // Evergreen / Northern Islands
471     switch (MF.getFunction().getCallingConv()) {
472     default: LLVM_FALLTHROUGH;
473     case CallingConv::AMDGPU_CS: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
474     case CallingConv::AMDGPU_GS: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
475     case CallingConv::AMDGPU_PS: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
476     case CallingConv::AMDGPU_VS: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
477     }
478   } else {
479     // R600 / R700
480     switch (MF.getFunction().getCallingConv()) {
481     default: LLVM_FALLTHROUGH;
482     case CallingConv::AMDGPU_GS: LLVM_FALLTHROUGH;
483     case CallingConv::AMDGPU_CS: LLVM_FALLTHROUGH;
484     case CallingConv::AMDGPU_VS: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
485     case CallingConv::AMDGPU_PS: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
486     }
487   }
488 
489   OutStreamer->EmitIntValue(RsrcReg, 4);
490   OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
491                            S_STACK_SIZE(MFI->CFStackSize), 4);
492   OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
493   OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
494 
495   if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
496     OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
497     OutStreamer->EmitIntValue(alignTo(MFI->getLDSSize(), 4) >> 2, 4);
498   }
499 }
500 
501 uint64_t AMDGPUAsmPrinter::getFunctionCodeSize(const MachineFunction &MF) const {
502   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
503   const SIInstrInfo *TII = STM.getInstrInfo();
504 
505   uint64_t CodeSize = 0;
506 
507   for (const MachineBasicBlock &MBB : MF) {
508     for (const MachineInstr &MI : MBB) {
509       // TODO: CodeSize should account for multiple functions.
510 
511       // TODO: Should we count size of debug info?
512       if (MI.isDebugInstr())
513         continue;
514 
515       CodeSize += TII->getInstSizeInBytes(MI);
516     }
517   }
518 
519   return CodeSize;
520 }
521 
522 static bool hasAnyNonFlatUseOfReg(const MachineRegisterInfo &MRI,
523                                   const SIInstrInfo &TII,
524                                   unsigned Reg) {
525   for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) {
526     if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent()))
527       return true;
528   }
529 
530   return false;
531 }
532 
533 static unsigned getNumExtraSGPRs(const SISubtarget &ST,
534                                  bool VCCUsed,
535                                  bool FlatScrUsed) {
536   unsigned ExtraSGPRs = 0;
537   if (VCCUsed)
538     ExtraSGPRs = 2;
539 
540   if (ST.getGeneration() < SISubtarget::VOLCANIC_ISLANDS) {
541     if (FlatScrUsed)
542       ExtraSGPRs = 4;
543   } else {
544     if (ST.isXNACKEnabled())
545       ExtraSGPRs = 4;
546 
547     if (FlatScrUsed)
548       ExtraSGPRs = 6;
549   }
550 
551   return ExtraSGPRs;
552 }
553 
554 int32_t AMDGPUAsmPrinter::SIFunctionResourceInfo::getTotalNumSGPRs(
555   const SISubtarget &ST) const {
556   return NumExplicitSGPR + getNumExtraSGPRs(ST, UsesVCC, UsesFlatScratch);
557 }
558 
559 AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
560   const MachineFunction &MF) const {
561   SIFunctionResourceInfo Info;
562 
563   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
564   const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
565   const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
566   const MachineRegisterInfo &MRI = MF.getRegInfo();
567   const SIInstrInfo *TII = ST.getInstrInfo();
568   const SIRegisterInfo &TRI = TII->getRegisterInfo();
569 
570   Info.UsesFlatScratch = MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_LO) ||
571                          MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_HI);
572 
573   // Even if FLAT_SCRATCH is implicitly used, it has no effect if flat
574   // instructions aren't used to access the scratch buffer. Inline assembly may
575   // need it though.
576   //
577   // If we only have implicit uses of flat_scr on flat instructions, it is not
578   // really needed.
579   if (Info.UsesFlatScratch && !MFI->hasFlatScratchInit() &&
580       (!hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR) &&
581        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_LO) &&
582        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_HI))) {
583     Info.UsesFlatScratch = false;
584   }
585 
586   Info.HasDynamicallySizedStack = FrameInfo.hasVarSizedObjects();
587   Info.PrivateSegmentSize = FrameInfo.getStackSize();
588   if (MFI->isStackRealigned())
589     Info.PrivateSegmentSize += FrameInfo.getMaxAlignment();
590 
591 
592   Info.UsesVCC = MRI.isPhysRegUsed(AMDGPU::VCC_LO) ||
593                  MRI.isPhysRegUsed(AMDGPU::VCC_HI);
594 
595   // If there are no calls, MachineRegisterInfo can tell us the used register
596   // count easily.
597   // A tail call isn't considered a call for MachineFrameInfo's purposes.
598   if (!FrameInfo.hasCalls() && !FrameInfo.hasTailCall()) {
599     MCPhysReg HighestVGPRReg = AMDGPU::NoRegister;
600     for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) {
601       if (MRI.isPhysRegUsed(Reg)) {
602         HighestVGPRReg = Reg;
603         break;
604       }
605     }
606 
607     MCPhysReg HighestSGPRReg = AMDGPU::NoRegister;
608     for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) {
609       if (MRI.isPhysRegUsed(Reg)) {
610         HighestSGPRReg = Reg;
611         break;
612       }
613     }
614 
615     // We found the maximum register index. They start at 0, so add one to get the
616     // number of registers.
617     Info.NumVGPR = HighestVGPRReg == AMDGPU::NoRegister ? 0 :
618       TRI.getHWRegIndex(HighestVGPRReg) + 1;
619     Info.NumExplicitSGPR = HighestSGPRReg == AMDGPU::NoRegister ? 0 :
620       TRI.getHWRegIndex(HighestSGPRReg) + 1;
621 
622     return Info;
623   }
624 
625   int32_t MaxVGPR = -1;
626   int32_t MaxSGPR = -1;
627   uint64_t CalleeFrameSize = 0;
628 
629   for (const MachineBasicBlock &MBB : MF) {
630     for (const MachineInstr &MI : MBB) {
631       // TODO: Check regmasks? Do they occur anywhere except calls?
632       for (const MachineOperand &MO : MI.operands()) {
633         unsigned Width = 0;
634         bool IsSGPR = false;
635 
636         if (!MO.isReg())
637           continue;
638 
639         unsigned Reg = MO.getReg();
640         switch (Reg) {
641         case AMDGPU::EXEC:
642         case AMDGPU::EXEC_LO:
643         case AMDGPU::EXEC_HI:
644         case AMDGPU::SCC:
645         case AMDGPU::M0:
646         case AMDGPU::SRC_SHARED_BASE:
647         case AMDGPU::SRC_SHARED_LIMIT:
648         case AMDGPU::SRC_PRIVATE_BASE:
649         case AMDGPU::SRC_PRIVATE_LIMIT:
650           continue;
651 
652         case AMDGPU::NoRegister:
653           assert(MI.isDebugInstr());
654           continue;
655 
656         case AMDGPU::VCC:
657         case AMDGPU::VCC_LO:
658         case AMDGPU::VCC_HI:
659           Info.UsesVCC = true;
660           continue;
661 
662         case AMDGPU::FLAT_SCR:
663         case AMDGPU::FLAT_SCR_LO:
664         case AMDGPU::FLAT_SCR_HI:
665           continue;
666 
667         case AMDGPU::XNACK_MASK:
668         case AMDGPU::XNACK_MASK_LO:
669         case AMDGPU::XNACK_MASK_HI:
670           llvm_unreachable("xnack_mask registers should not be used");
671 
672         case AMDGPU::TBA:
673         case AMDGPU::TBA_LO:
674         case AMDGPU::TBA_HI:
675         case AMDGPU::TMA:
676         case AMDGPU::TMA_LO:
677         case AMDGPU::TMA_HI:
678           llvm_unreachable("trap handler registers should not be used");
679 
680         default:
681           break;
682         }
683 
684         if (AMDGPU::SReg_32RegClass.contains(Reg)) {
685           assert(!AMDGPU::TTMP_32RegClass.contains(Reg) &&
686                  "trap handler registers should not be used");
687           IsSGPR = true;
688           Width = 1;
689         } else if (AMDGPU::VGPR_32RegClass.contains(Reg)) {
690           IsSGPR = false;
691           Width = 1;
692         } else if (AMDGPU::SReg_64RegClass.contains(Reg)) {
693           assert(!AMDGPU::TTMP_64RegClass.contains(Reg) &&
694                  "trap handler registers should not be used");
695           IsSGPR = true;
696           Width = 2;
697         } else if (AMDGPU::VReg_64RegClass.contains(Reg)) {
698           IsSGPR = false;
699           Width = 2;
700         } else if (AMDGPU::VReg_96RegClass.contains(Reg)) {
701           IsSGPR = false;
702           Width = 3;
703         } else if (AMDGPU::SReg_128RegClass.contains(Reg)) {
704           assert(!AMDGPU::TTMP_128RegClass.contains(Reg) &&
705             "trap handler registers should not be used");
706           IsSGPR = true;
707           Width = 4;
708         } else if (AMDGPU::VReg_128RegClass.contains(Reg)) {
709           IsSGPR = false;
710           Width = 4;
711         } else if (AMDGPU::SReg_256RegClass.contains(Reg)) {
712           assert(!AMDGPU::TTMP_256RegClass.contains(Reg) &&
713             "trap handler registers should not be used");
714           IsSGPR = true;
715           Width = 8;
716         } else if (AMDGPU::VReg_256RegClass.contains(Reg)) {
717           IsSGPR = false;
718           Width = 8;
719         } else if (AMDGPU::SReg_512RegClass.contains(Reg)) {
720           assert(!AMDGPU::TTMP_512RegClass.contains(Reg) &&
721             "trap handler registers should not be used");
722           IsSGPR = true;
723           Width = 16;
724         } else if (AMDGPU::VReg_512RegClass.contains(Reg)) {
725           IsSGPR = false;
726           Width = 16;
727         } else {
728           llvm_unreachable("Unknown register class");
729         }
730         unsigned HWReg = TRI.getHWRegIndex(Reg);
731         int MaxUsed = HWReg + Width - 1;
732         if (IsSGPR) {
733           MaxSGPR = MaxUsed > MaxSGPR ? MaxUsed : MaxSGPR;
734         } else {
735           MaxVGPR = MaxUsed > MaxVGPR ? MaxUsed : MaxVGPR;
736         }
737       }
738 
739       if (MI.isCall()) {
740         // Pseudo used just to encode the underlying global. Is there a better
741         // way to track this?
742 
743         const MachineOperand *CalleeOp
744           = TII->getNamedOperand(MI, AMDGPU::OpName::callee);
745         const Function *Callee = cast<Function>(CalleeOp->getGlobal());
746         if (Callee->isDeclaration()) {
747           // If this is a call to an external function, we can't do much. Make
748           // conservative guesses.
749 
750           // 48 SGPRs - vcc, - flat_scr, -xnack
751           int MaxSGPRGuess = 47 - getNumExtraSGPRs(ST, true,
752                                                    ST.hasFlatAddressSpace());
753           MaxSGPR = std::max(MaxSGPR, MaxSGPRGuess);
754           MaxVGPR = std::max(MaxVGPR, 23);
755 
756           CalleeFrameSize = std::max(CalleeFrameSize, UINT64_C(16384));
757           Info.UsesVCC = true;
758           Info.UsesFlatScratch = ST.hasFlatAddressSpace();
759           Info.HasDynamicallySizedStack = true;
760         } else {
761           // We force CodeGen to run in SCC order, so the callee's register
762           // usage etc. should be the cumulative usage of all callees.
763           auto I = CallGraphResourceInfo.find(Callee);
764           assert(I != CallGraphResourceInfo.end() &&
765                  "callee should have been handled before caller");
766 
767           MaxSGPR = std::max(I->second.NumExplicitSGPR - 1, MaxSGPR);
768           MaxVGPR = std::max(I->second.NumVGPR - 1, MaxVGPR);
769           CalleeFrameSize
770             = std::max(I->second.PrivateSegmentSize, CalleeFrameSize);
771           Info.UsesVCC |= I->second.UsesVCC;
772           Info.UsesFlatScratch |= I->second.UsesFlatScratch;
773           Info.HasDynamicallySizedStack |= I->second.HasDynamicallySizedStack;
774           Info.HasRecursion |= I->second.HasRecursion;
775         }
776 
777         if (!Callee->doesNotRecurse())
778           Info.HasRecursion = true;
779       }
780     }
781   }
782 
783   Info.NumExplicitSGPR = MaxSGPR + 1;
784   Info.NumVGPR = MaxVGPR + 1;
785   Info.PrivateSegmentSize += CalleeFrameSize;
786 
787   return Info;
788 }
789 
790 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
791                                         const MachineFunction &MF) {
792   SIFunctionResourceInfo Info = analyzeResourceUsage(MF);
793 
794   ProgInfo.NumVGPR = Info.NumVGPR;
795   ProgInfo.NumSGPR = Info.NumExplicitSGPR;
796   ProgInfo.ScratchSize = Info.PrivateSegmentSize;
797   ProgInfo.VCCUsed = Info.UsesVCC;
798   ProgInfo.FlatUsed = Info.UsesFlatScratch;
799   ProgInfo.DynamicCallStack = Info.HasDynamicallySizedStack || Info.HasRecursion;
800 
801   if (!isUInt<32>(ProgInfo.ScratchSize)) {
802     DiagnosticInfoStackSize DiagStackSize(MF.getFunction(),
803                                           ProgInfo.ScratchSize, DS_Error);
804     MF.getFunction().getContext().diagnose(DiagStackSize);
805   }
806 
807   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
808   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
809   const SIInstrInfo *TII = STM.getInstrInfo();
810   const SIRegisterInfo *RI = &TII->getRegisterInfo();
811 
812   unsigned ExtraSGPRs = getNumExtraSGPRs(STM,
813                                          ProgInfo.VCCUsed,
814                                          ProgInfo.FlatUsed);
815   unsigned ExtraVGPRs = STM.getReservedNumVGPRs(MF);
816 
817   // Check the addressable register limit before we add ExtraSGPRs.
818   if (STM.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
819       !STM.hasSGPRInitBug()) {
820     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
821     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
822       // This can happen due to a compiler bug or when using inline asm.
823       LLVMContext &Ctx = MF.getFunction().getContext();
824       DiagnosticInfoResourceLimit Diag(MF.getFunction(),
825                                        "addressable scalar registers",
826                                        ProgInfo.NumSGPR, DS_Error,
827                                        DK_ResourceLimit,
828                                        MaxAddressableNumSGPRs);
829       Ctx.diagnose(Diag);
830       ProgInfo.NumSGPR = MaxAddressableNumSGPRs - 1;
831     }
832   }
833 
834   // Account for extra SGPRs and VGPRs reserved for debugger use.
835   ProgInfo.NumSGPR += ExtraSGPRs;
836   ProgInfo.NumVGPR += ExtraVGPRs;
837 
838   // Ensure there are enough SGPRs and VGPRs for wave dispatch, where wave
839   // dispatch registers are function args.
840   unsigned WaveDispatchNumSGPR = 0, WaveDispatchNumVGPR = 0;
841   for (auto &Arg : MF.getFunction().args()) {
842     unsigned NumRegs = (Arg.getType()->getPrimitiveSizeInBits() + 31) / 32;
843     if (Arg.hasAttribute(Attribute::InReg))
844       WaveDispatchNumSGPR += NumRegs;
845     else
846       WaveDispatchNumVGPR += NumRegs;
847   }
848   ProgInfo.NumSGPR = std::max(ProgInfo.NumSGPR, WaveDispatchNumSGPR);
849   ProgInfo.NumVGPR = std::max(ProgInfo.NumVGPR, WaveDispatchNumVGPR);
850 
851   // Adjust number of registers used to meet default/requested minimum/maximum
852   // number of waves per execution unit request.
853   ProgInfo.NumSGPRsForWavesPerEU = std::max(
854     std::max(ProgInfo.NumSGPR, 1u), STM.getMinNumSGPRs(MFI->getMaxWavesPerEU()));
855   ProgInfo.NumVGPRsForWavesPerEU = std::max(
856     std::max(ProgInfo.NumVGPR, 1u), STM.getMinNumVGPRs(MFI->getMaxWavesPerEU()));
857 
858   if (STM.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ||
859       STM.hasSGPRInitBug()) {
860     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
861     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
862       // This can happen due to a compiler bug or when using inline asm to use
863       // the registers which are usually reserved for vcc etc.
864       LLVMContext &Ctx = MF.getFunction().getContext();
865       DiagnosticInfoResourceLimit Diag(MF.getFunction(),
866                                        "scalar registers",
867                                        ProgInfo.NumSGPR, DS_Error,
868                                        DK_ResourceLimit,
869                                        MaxAddressableNumSGPRs);
870       Ctx.diagnose(Diag);
871       ProgInfo.NumSGPR = MaxAddressableNumSGPRs;
872       ProgInfo.NumSGPRsForWavesPerEU = MaxAddressableNumSGPRs;
873     }
874   }
875 
876   if (STM.hasSGPRInitBug()) {
877     ProgInfo.NumSGPR =
878         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
879     ProgInfo.NumSGPRsForWavesPerEU =
880         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
881   }
882 
883   if (MFI->getNumUserSGPRs() > STM.getMaxNumUserSGPRs()) {
884     LLVMContext &Ctx = MF.getFunction().getContext();
885     DiagnosticInfoResourceLimit Diag(MF.getFunction(), "user SGPRs",
886                                      MFI->getNumUserSGPRs(), DS_Error);
887     Ctx.diagnose(Diag);
888   }
889 
890   if (MFI->getLDSSize() > static_cast<unsigned>(STM.getLocalMemorySize())) {
891     LLVMContext &Ctx = MF.getFunction().getContext();
892     DiagnosticInfoResourceLimit Diag(MF.getFunction(), "local memory",
893                                      MFI->getLDSSize(), DS_Error);
894     Ctx.diagnose(Diag);
895   }
896 
897   // SGPRBlocks is actual number of SGPR blocks minus 1.
898   ProgInfo.SGPRBlocks = alignTo(ProgInfo.NumSGPRsForWavesPerEU,
899                                 STM.getSGPREncodingGranule());
900   ProgInfo.SGPRBlocks = ProgInfo.SGPRBlocks / STM.getSGPREncodingGranule() - 1;
901 
902   // VGPRBlocks is actual number of VGPR blocks minus 1.
903   ProgInfo.VGPRBlocks = alignTo(ProgInfo.NumVGPRsForWavesPerEU,
904                                 STM.getVGPREncodingGranule());
905   ProgInfo.VGPRBlocks = ProgInfo.VGPRBlocks / STM.getVGPREncodingGranule() - 1;
906 
907   // Record first reserved VGPR and number of reserved VGPRs.
908   ProgInfo.ReservedVGPRFirst = STM.debuggerReserveRegs() ? ProgInfo.NumVGPR : 0;
909   ProgInfo.ReservedVGPRCount = STM.getReservedNumVGPRs(MF);
910 
911   // Update DebuggerWavefrontPrivateSegmentOffsetSGPR and
912   // DebuggerPrivateSegmentBufferSGPR fields if "amdgpu-debugger-emit-prologue"
913   // attribute was requested.
914   if (STM.debuggerEmitPrologue()) {
915     ProgInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR =
916       RI->getHWRegIndex(MFI->getScratchWaveOffsetReg());
917     ProgInfo.DebuggerPrivateSegmentBufferSGPR =
918       RI->getHWRegIndex(MFI->getScratchRSrcReg());
919   }
920 
921   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
922   // register.
923   ProgInfo.FloatMode = getFPMode(MF);
924 
925   ProgInfo.IEEEMode = STM.enableIEEEBit(MF);
926 
927   // Make clamp modifier on NaN input returns 0.
928   ProgInfo.DX10Clamp = STM.enableDX10Clamp();
929 
930   unsigned LDSAlignShift;
931   if (STM.getGeneration() < SISubtarget::SEA_ISLANDS) {
932     // LDS is allocated in 64 dword blocks.
933     LDSAlignShift = 8;
934   } else {
935     // LDS is allocated in 128 dword blocks.
936     LDSAlignShift = 9;
937   }
938 
939   unsigned LDSSpillSize =
940     MFI->getLDSWaveSpillSize() * MFI->getMaxFlatWorkGroupSize();
941 
942   ProgInfo.LDSSize = MFI->getLDSSize() + LDSSpillSize;
943   ProgInfo.LDSBlocks =
944       alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
945 
946   // Scratch is allocated in 256 dword blocks.
947   unsigned ScratchAlignShift = 10;
948   // We need to program the hardware with the amount of scratch memory that
949   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
950   // scratch memory used per thread.
951   ProgInfo.ScratchBlocks =
952       alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
953               1ULL << ScratchAlignShift) >>
954       ScratchAlignShift;
955 
956   ProgInfo.ComputePGMRSrc1 =
957       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
958       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
959       S_00B848_PRIORITY(ProgInfo.Priority) |
960       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
961       S_00B848_PRIV(ProgInfo.Priv) |
962       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
963       S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
964       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
965 
966   // 0 = X, 1 = XY, 2 = XYZ
967   unsigned TIDIGCompCnt = 0;
968   if (MFI->hasWorkItemIDZ())
969     TIDIGCompCnt = 2;
970   else if (MFI->hasWorkItemIDY())
971     TIDIGCompCnt = 1;
972 
973   ProgInfo.ComputePGMRSrc2 =
974       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
975       S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
976       S_00B84C_TRAP_HANDLER(STM.isTrapHandlerEnabled()) |
977       S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
978       S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
979       S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
980       S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
981       S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
982       S_00B84C_EXCP_EN_MSB(0) |
983       // For AMDHSA, LDS_SIZE must be zero, as it is populated by the CP.
984       S_00B84C_LDS_SIZE(STM.isAmdHsaOS() ? 0 : ProgInfo.LDSBlocks) |
985       S_00B84C_EXCP_EN(0);
986 }
987 
988 static unsigned getRsrcReg(CallingConv::ID CallConv) {
989   switch (CallConv) {
990   default: LLVM_FALLTHROUGH;
991   case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
992   case CallingConv::AMDGPU_LS: return R_00B528_SPI_SHADER_PGM_RSRC1_LS;
993   case CallingConv::AMDGPU_HS: return R_00B428_SPI_SHADER_PGM_RSRC1_HS;
994   case CallingConv::AMDGPU_ES: return R_00B328_SPI_SHADER_PGM_RSRC1_ES;
995   case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
996   case CallingConv::AMDGPU_VS: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
997   case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
998   }
999 }
1000 
1001 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
1002                                          const SIProgramInfo &CurrentProgramInfo) {
1003   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
1004   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1005   unsigned RsrcReg = getRsrcReg(MF.getFunction().getCallingConv());
1006 
1007   if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
1008     OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
1009 
1010     OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc1, 4);
1011 
1012     OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
1013     OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc2, 4);
1014 
1015     OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
1016     OutStreamer->EmitIntValue(S_00B860_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
1017 
1018     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
1019     // 0" comment but I don't see a corresponding field in the register spec.
1020   } else {
1021     OutStreamer->EmitIntValue(RsrcReg, 4);
1022     OutStreamer->EmitIntValue(S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
1023                               S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks), 4);
1024     if (STM.isVGPRSpillingEnabled(MF.getFunction())) {
1025       OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
1026       OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
1027     }
1028   }
1029 
1030   if (MF.getFunction().getCallingConv() == CallingConv::AMDGPU_PS) {
1031     OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
1032     OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks), 4);
1033     OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
1034     OutStreamer->EmitIntValue(MFI->getPSInputEnable(), 4);
1035     OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
1036     OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4);
1037   }
1038 
1039   OutStreamer->EmitIntValue(R_SPILLED_SGPRS, 4);
1040   OutStreamer->EmitIntValue(MFI->getNumSpilledSGPRs(), 4);
1041   OutStreamer->EmitIntValue(R_SPILLED_VGPRS, 4);
1042   OutStreamer->EmitIntValue(MFI->getNumSpilledVGPRs(), 4);
1043 }
1044 
1045 // This is the equivalent of EmitProgramInfoSI above, but for when the OS type
1046 // is AMDPAL.  It stores each compute/SPI register setting and other PAL
1047 // metadata items into the PALMetadataMap, combining with any provided by the
1048 // frontend as LLVM metadata. Once all functions are written, PALMetadataMap is
1049 // then written as a single block in the .note section.
1050 void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
1051        const SIProgramInfo &CurrentProgramInfo) {
1052   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1053   // Given the calling convention, calculate the register number for rsrc1. In
1054   // principle the register number could change in future hardware, but we know
1055   // it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so
1056   // we can use the same fixed value that .AMDGPU.config has for Mesa. Note
1057   // that we use a register number rather than a byte offset, so we need to
1058   // divide by 4.
1059   unsigned Rsrc1Reg = getRsrcReg(MF.getFunction().getCallingConv()) / 4;
1060   unsigned Rsrc2Reg = Rsrc1Reg + 1;
1061   // Also calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used
1062   // with a constant offset to access any non-register shader-specific PAL
1063   // metadata key.
1064   unsigned ScratchSizeKey = PALMD::Key::CS_SCRATCH_SIZE;
1065   switch (MF.getFunction().getCallingConv()) {
1066     case CallingConv::AMDGPU_PS:
1067       ScratchSizeKey = PALMD::Key::PS_SCRATCH_SIZE;
1068       break;
1069     case CallingConv::AMDGPU_VS:
1070       ScratchSizeKey = PALMD::Key::VS_SCRATCH_SIZE;
1071       break;
1072     case CallingConv::AMDGPU_GS:
1073       ScratchSizeKey = PALMD::Key::GS_SCRATCH_SIZE;
1074       break;
1075     case CallingConv::AMDGPU_ES:
1076       ScratchSizeKey = PALMD::Key::ES_SCRATCH_SIZE;
1077       break;
1078     case CallingConv::AMDGPU_HS:
1079       ScratchSizeKey = PALMD::Key::HS_SCRATCH_SIZE;
1080       break;
1081     case CallingConv::AMDGPU_LS:
1082       ScratchSizeKey = PALMD::Key::LS_SCRATCH_SIZE;
1083       break;
1084   }
1085   unsigned NumUsedVgprsKey = ScratchSizeKey +
1086       PALMD::Key::VS_NUM_USED_VGPRS - PALMD::Key::VS_SCRATCH_SIZE;
1087   unsigned NumUsedSgprsKey = ScratchSizeKey +
1088       PALMD::Key::VS_NUM_USED_SGPRS - PALMD::Key::VS_SCRATCH_SIZE;
1089   PALMetadataMap[NumUsedVgprsKey] = CurrentProgramInfo.NumVGPRsForWavesPerEU;
1090   PALMetadataMap[NumUsedSgprsKey] = CurrentProgramInfo.NumSGPRsForWavesPerEU;
1091   if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
1092     PALMetadataMap[Rsrc1Reg] |= CurrentProgramInfo.ComputePGMRSrc1;
1093     PALMetadataMap[Rsrc2Reg] |= CurrentProgramInfo.ComputePGMRSrc2;
1094     // ScratchSize is in bytes, 16 aligned.
1095     PALMetadataMap[ScratchSizeKey] |=
1096         alignTo(CurrentProgramInfo.ScratchSize, 16);
1097   } else {
1098     PALMetadataMap[Rsrc1Reg] |= S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
1099         S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks);
1100     if (CurrentProgramInfo.ScratchBlocks > 0)
1101       PALMetadataMap[Rsrc2Reg] |= S_00B84C_SCRATCH_EN(1);
1102     // ScratchSize is in bytes, 16 aligned.
1103     PALMetadataMap[ScratchSizeKey] |=
1104         alignTo(CurrentProgramInfo.ScratchSize, 16);
1105   }
1106   if (MF.getFunction().getCallingConv() == CallingConv::AMDGPU_PS) {
1107     PALMetadataMap[Rsrc2Reg] |=
1108         S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks);
1109     PALMetadataMap[R_0286CC_SPI_PS_INPUT_ENA / 4] |= MFI->getPSInputEnable();
1110     PALMetadataMap[R_0286D0_SPI_PS_INPUT_ADDR / 4] |= MFI->getPSInputAddr();
1111   }
1112 }
1113 
1114 // This is supposed to be log2(Size)
1115 static amd_element_byte_size_t getElementByteSizeValue(unsigned Size) {
1116   switch (Size) {
1117   case 4:
1118     return AMD_ELEMENT_4_BYTES;
1119   case 8:
1120     return AMD_ELEMENT_8_BYTES;
1121   case 16:
1122     return AMD_ELEMENT_16_BYTES;
1123   default:
1124     llvm_unreachable("invalid private_element_size");
1125   }
1126 }
1127 
1128 void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out,
1129                                         const SIProgramInfo &CurrentProgramInfo,
1130                                         const MachineFunction &MF) const {
1131   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1132   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
1133 
1134   AMDGPU::initDefaultAMDKernelCodeT(Out, STM.getFeatureBits());
1135 
1136   Out.compute_pgm_resource_registers =
1137       CurrentProgramInfo.ComputePGMRSrc1 |
1138       (CurrentProgramInfo.ComputePGMRSrc2 << 32);
1139   Out.code_properties = AMD_CODE_PROPERTY_IS_PTR64;
1140 
1141   if (CurrentProgramInfo.DynamicCallStack)
1142     Out.code_properties |= AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK;
1143 
1144   AMD_HSA_BITS_SET(Out.code_properties,
1145                    AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE,
1146                    getElementByteSizeValue(STM.getMaxPrivateElementSize()));
1147 
1148   if (MFI->hasPrivateSegmentBuffer()) {
1149     Out.code_properties |=
1150       AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
1151   }
1152 
1153   if (MFI->hasDispatchPtr())
1154     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
1155 
1156   if (MFI->hasQueuePtr())
1157     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
1158 
1159   if (MFI->hasKernargSegmentPtr())
1160     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
1161 
1162   if (MFI->hasDispatchID())
1163     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
1164 
1165   if (MFI->hasFlatScratchInit())
1166     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
1167 
1168   if (MFI->hasGridWorkgroupCountX()) {
1169     Out.code_properties |=
1170       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X;
1171   }
1172 
1173   if (MFI->hasGridWorkgroupCountY()) {
1174     Out.code_properties |=
1175       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y;
1176   }
1177 
1178   if (MFI->hasGridWorkgroupCountZ()) {
1179     Out.code_properties |=
1180       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z;
1181   }
1182 
1183   if (MFI->hasDispatchPtr())
1184     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
1185 
1186   if (STM.debuggerSupported())
1187     Out.code_properties |= AMD_CODE_PROPERTY_IS_DEBUG_SUPPORTED;
1188 
1189   if (STM.isXNACKEnabled())
1190     Out.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED;
1191 
1192   // FIXME: Should use getKernArgSize
1193   Out.kernarg_segment_byte_size =
1194     STM.getKernArgSegmentSize(MF, MFI->getABIArgOffset());
1195   Out.wavefront_sgpr_count = CurrentProgramInfo.NumSGPR;
1196   Out.workitem_vgpr_count = CurrentProgramInfo.NumVGPR;
1197   Out.workitem_private_segment_byte_size = CurrentProgramInfo.ScratchSize;
1198   Out.workgroup_group_segment_byte_size = CurrentProgramInfo.LDSSize;
1199   Out.reserved_vgpr_first = CurrentProgramInfo.ReservedVGPRFirst;
1200   Out.reserved_vgpr_count = CurrentProgramInfo.ReservedVGPRCount;
1201 
1202   // These alignment values are specified in powers of two, so alignment =
1203   // 2^n.  The minimum alignment is 2^4 = 16.
1204   Out.kernarg_segment_alignment = std::max((size_t)4,
1205       countTrailingZeros(MFI->getMaxKernArgAlign()));
1206 
1207   if (STM.debuggerEmitPrologue()) {
1208     Out.debug_wavefront_private_segment_offset_sgpr =
1209       CurrentProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR;
1210     Out.debug_private_segment_buffer_sgpr =
1211       CurrentProgramInfo.DebuggerPrivateSegmentBufferSGPR;
1212   }
1213 }
1214 
1215 AMDGPU::HSAMD::Kernel::CodeProps::Metadata AMDGPUAsmPrinter::getHSACodeProps(
1216     const MachineFunction &MF,
1217     const SIProgramInfo &ProgramInfo) const {
1218   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
1219   const SIMachineFunctionInfo &MFI = *MF.getInfo<SIMachineFunctionInfo>();
1220   HSAMD::Kernel::CodeProps::Metadata HSACodeProps;
1221 
1222   HSACodeProps.mKernargSegmentSize =
1223       STM.getKernArgSegmentSize(MF, MFI.getABIArgOffset());
1224   HSACodeProps.mGroupSegmentFixedSize = ProgramInfo.LDSSize;
1225   HSACodeProps.mPrivateSegmentFixedSize = ProgramInfo.ScratchSize;
1226   HSACodeProps.mKernargSegmentAlign =
1227       std::max(uint32_t(4), MFI.getMaxKernArgAlign());
1228   HSACodeProps.mWavefrontSize = STM.getWavefrontSize();
1229   HSACodeProps.mNumSGPRs = CurrentProgramInfo.NumSGPR;
1230   HSACodeProps.mNumVGPRs = CurrentProgramInfo.NumVGPR;
1231   HSACodeProps.mMaxFlatWorkGroupSize = MFI.getMaxFlatWorkGroupSize();
1232   HSACodeProps.mIsDynamicCallStack = ProgramInfo.DynamicCallStack;
1233   HSACodeProps.mIsXNACKEnabled = STM.isXNACKEnabled();
1234   HSACodeProps.mNumSpilledSGPRs = MFI.getNumSpilledSGPRs();
1235   HSACodeProps.mNumSpilledVGPRs = MFI.getNumSpilledVGPRs();
1236 
1237   return HSACodeProps;
1238 }
1239 
1240 AMDGPU::HSAMD::Kernel::DebugProps::Metadata AMDGPUAsmPrinter::getHSADebugProps(
1241     const MachineFunction &MF,
1242     const SIProgramInfo &ProgramInfo) const {
1243   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
1244   HSAMD::Kernel::DebugProps::Metadata HSADebugProps;
1245 
1246   if (!STM.debuggerSupported())
1247     return HSADebugProps;
1248 
1249   HSADebugProps.mDebuggerABIVersion.push_back(1);
1250   HSADebugProps.mDebuggerABIVersion.push_back(0);
1251   HSADebugProps.mReservedNumVGPRs = ProgramInfo.ReservedVGPRCount;
1252   HSADebugProps.mReservedFirstVGPR = ProgramInfo.ReservedVGPRFirst;
1253 
1254   if (STM.debuggerEmitPrologue()) {
1255     HSADebugProps.mPrivateSegmentBufferSGPR =
1256         ProgramInfo.DebuggerPrivateSegmentBufferSGPR;
1257     HSADebugProps.mWavefrontPrivateSegmentOffsetSGPR =
1258         ProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR;
1259   }
1260 
1261   return HSADebugProps;
1262 }
1263 
1264 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
1265                                        unsigned AsmVariant,
1266                                        const char *ExtraCode, raw_ostream &O) {
1267   // First try the generic code, which knows about modifiers like 'c' and 'n'.
1268   if (!AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O))
1269     return false;
1270 
1271   if (ExtraCode && ExtraCode[0]) {
1272     if (ExtraCode[1] != 0)
1273       return true; // Unknown modifier.
1274 
1275     switch (ExtraCode[0]) {
1276     case 'r':
1277       break;
1278     default:
1279       return true;
1280     }
1281   }
1282 
1283   // TODO: Should be able to support other operand types like globals.
1284   const MachineOperand &MO = MI->getOperand(OpNo);
1285   if (MO.isReg()) {
1286     AMDGPUInstPrinter::printRegOperand(MO.getReg(), O,
1287                                        *MF->getSubtarget().getRegisterInfo());
1288     return false;
1289   }
1290 
1291   return true;
1292 }
1293