1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
15 //
16 //===----------------------------------------------------------------------===//
17 //
18 
19 #include "AMDGPUAsmPrinter.h"
20 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
21 #include "InstPrinter/AMDGPUInstPrinter.h"
22 #include "Utils/AMDGPUBaseInfo.h"
23 #include "AMDGPU.h"
24 #include "AMDKernelCodeT.h"
25 #include "AMDGPUSubtarget.h"
26 #include "R600Defines.h"
27 #include "R600MachineFunctionInfo.h"
28 #include "R600RegisterInfo.h"
29 #include "SIDefines.h"
30 #include "SIMachineFunctionInfo.h"
31 #include "SIInstrInfo.h"
32 #include "SIRegisterInfo.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/IR/DiagnosticInfo.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCSectionELF.h"
37 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/Support/ELF.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Target/TargetLoweringObjectFile.h"
42 #include "AMDGPURuntimeMetadata.h"
43 
44 using namespace ::AMDGPU;
45 using namespace llvm;
46 
47 // TODO: This should get the default rounding mode from the kernel. We just set
48 // the default here, but this could change if the OpenCL rounding mode pragmas
49 // are used.
50 //
51 // The denormal mode here should match what is reported by the OpenCL runtime
52 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
53 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
54 //
55 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
56 // precision, and leaves single precision to flush all and does not report
57 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
58 // CL_FP_DENORM for both.
59 //
60 // FIXME: It seems some instructions do not support single precision denormals
61 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
62 // and sin_f32, cos_f32 on most parts).
63 
64 // We want to use these instructions, and using fp32 denormals also causes
65 // instructions to run at the double precision rate for the device so it's
66 // probably best to just report no single precision denormals.
67 static uint32_t getFPMode(const MachineFunction &F) {
68   const SISubtarget& ST = F.getSubtarget<SISubtarget>();
69   // TODO: Is there any real use for the flush in only / flush out only modes?
70 
71   uint32_t FP32Denormals =
72     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
73 
74   uint32_t FP64Denormals =
75     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
76 
77   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
78          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
79          FP_DENORM_MODE_SP(FP32Denormals) |
80          FP_DENORM_MODE_DP(FP64Denormals);
81 }
82 
83 static AsmPrinter *
84 createAMDGPUAsmPrinterPass(TargetMachine &tm,
85                            std::unique_ptr<MCStreamer> &&Streamer) {
86   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
87 }
88 
89 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
90   TargetRegistry::RegisterAsmPrinter(getTheAMDGPUTarget(),
91                                      createAMDGPUAsmPrinterPass);
92   TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(),
93                                      createAMDGPUAsmPrinterPass);
94 }
95 
96 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
97                                    std::unique_ptr<MCStreamer> Streamer)
98   : AsmPrinter(TM, std::move(Streamer)) {}
99 
100 StringRef AMDGPUAsmPrinter::getPassName() const {
101   return "AMDGPU Assembly Printer";
102 }
103 
104 void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) {
105   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
106     return;
107 
108   // Need to construct an MCSubtargetInfo here in case we have no functions
109   // in the module.
110   std::unique_ptr<MCSubtargetInfo> STI(TM.getTarget().createMCSubtargetInfo(
111         TM.getTargetTriple().str(), TM.getTargetCPU(),
112         TM.getTargetFeatureString()));
113 
114   AMDGPUTargetStreamer *TS =
115       static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
116 
117   TS->EmitDirectiveHSACodeObjectVersion(2, 1);
118 
119   AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI->getFeatureBits());
120   TS->EmitDirectiveHSACodeObjectISA(ISA.Major, ISA.Minor, ISA.Stepping,
121                                     "AMD", "AMDGPU");
122   emitStartOfRuntimeMetadata(M);
123 }
124 
125 bool AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough(
126   const MachineBasicBlock *MBB) const {
127   if (!AsmPrinter::isBlockOnlyReachableByFallthrough(MBB))
128     return false;
129 
130   if (MBB->empty())
131     return true;
132 
133   // If this is a block implementing a long branch, an expression relative to
134   // the start of the block is needed.  to the start of the block.
135   // XXX - Is there a smarter way to check this?
136   return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
137 }
138 
139 
140 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
141   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
142   SIProgramInfo KernelInfo;
143   if (STM.isAmdCodeObjectV2()) {
144     getSIProgramInfo(KernelInfo, *MF);
145     EmitAmdKernelCodeT(*MF, KernelInfo);
146   }
147 }
148 
149 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
150   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
151   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
152   if (MFI->isKernel() && STM.isAmdCodeObjectV2()) {
153     AMDGPUTargetStreamer *TS =
154         static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
155     SmallString<128> SymbolName;
156     getNameWithPrefix(SymbolName, MF->getFunction()),
157     TS->EmitAMDGPUSymbolType(SymbolName, ELF::STT_AMDGPU_HSA_KERNEL);
158   }
159 
160   AsmPrinter::EmitFunctionEntryLabel();
161 }
162 
163 void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
164 
165   // Group segment variables aren't emitted in HSA.
166   if (AMDGPU::isGroupSegment(GV))
167     return;
168 
169   AsmPrinter::EmitGlobalVariable(GV);
170 }
171 
172 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
173 
174   // The starting address of all shader programs must be 256 bytes aligned.
175   MF.setAlignment(8);
176 
177   SetupMachineFunction(MF);
178 
179   MCContext &Context = getObjFileLowering().getContext();
180   MCSectionELF *ConfigSection =
181       Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
182   OutStreamer->SwitchSection(ConfigSection);
183 
184   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
185   SIProgramInfo KernelInfo;
186   if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
187     getSIProgramInfo(KernelInfo, MF);
188     if (!STM.isAmdHsaOS()) {
189       EmitProgramInfoSI(MF, KernelInfo);
190     }
191   } else {
192     EmitProgramInfoR600(MF);
193   }
194 
195   DisasmLines.clear();
196   HexLines.clear();
197   DisasmLineMaxLen = 0;
198 
199   EmitFunctionBody();
200 
201   if (isVerbose()) {
202     MCSectionELF *CommentSection =
203         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
204     OutStreamer->SwitchSection(CommentSection);
205 
206     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
207       OutStreamer->emitRawComment(" Kernel info:", false);
208       OutStreamer->emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
209                                   false);
210       OutStreamer->emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
211                                   false);
212       OutStreamer->emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
213                                   false);
214       OutStreamer->emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
215                                   false);
216       OutStreamer->emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
217                                   false);
218       OutStreamer->emitRawComment(" ScratchSize: " + Twine(KernelInfo.ScratchSize),
219                                   false);
220       OutStreamer->emitRawComment(" LDSByteSize: " + Twine(KernelInfo.LDSSize) +
221                                   " bytes/workgroup (compile time only)", false);
222 
223       OutStreamer->emitRawComment(" SGPRBlocks: " +
224                                   Twine(KernelInfo.SGPRBlocks), false);
225       OutStreamer->emitRawComment(" VGPRBlocks: " +
226                                   Twine(KernelInfo.VGPRBlocks), false);
227 
228       OutStreamer->emitRawComment(" NumSGPRsForWavesPerEU: " +
229                                   Twine(KernelInfo.NumSGPRsForWavesPerEU), false);
230       OutStreamer->emitRawComment(" NumVGPRsForWavesPerEU: " +
231                                   Twine(KernelInfo.NumVGPRsForWavesPerEU), false);
232 
233       OutStreamer->emitRawComment(" ReservedVGPRFirst: " + Twine(KernelInfo.ReservedVGPRFirst),
234                                   false);
235       OutStreamer->emitRawComment(" ReservedVGPRCount: " + Twine(KernelInfo.ReservedVGPRCount),
236                                   false);
237 
238       if (MF.getSubtarget<SISubtarget>().debuggerEmitPrologue()) {
239         OutStreamer->emitRawComment(" DebuggerWavefrontPrivateSegmentOffsetSGPR: s" +
240                                     Twine(KernelInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR), false);
241         OutStreamer->emitRawComment(" DebuggerPrivateSegmentBufferSGPR: s" +
242                                     Twine(KernelInfo.DebuggerPrivateSegmentBufferSGPR), false);
243       }
244 
245       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:USER_SGPR: " +
246                                   Twine(G_00B84C_USER_SGPR(KernelInfo.ComputePGMRSrc2)),
247                                   false);
248       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_X_EN: " +
249                                   Twine(G_00B84C_TGID_X_EN(KernelInfo.ComputePGMRSrc2)),
250                                   false);
251       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
252                                   Twine(G_00B84C_TGID_Y_EN(KernelInfo.ComputePGMRSrc2)),
253                                   false);
254       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
255                                   Twine(G_00B84C_TGID_Z_EN(KernelInfo.ComputePGMRSrc2)),
256                                   false);
257       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
258                                   Twine(G_00B84C_TIDIG_COMP_CNT(KernelInfo.ComputePGMRSrc2)),
259                                   false);
260 
261     } else {
262       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
263       OutStreamer->emitRawComment(
264         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->CFStackSize)));
265     }
266   }
267 
268   if (STM.dumpCode()) {
269 
270     OutStreamer->SwitchSection(
271         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
272 
273     for (size_t i = 0; i < DisasmLines.size(); ++i) {
274       std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
275       Comment += " ; " + HexLines[i] + "\n";
276 
277       OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
278       OutStreamer->EmitBytes(StringRef(Comment));
279     }
280   }
281 
282   emitRuntimeMetadata(*MF.getFunction());
283 
284   return false;
285 }
286 
287 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
288   unsigned MaxGPR = 0;
289   bool killPixel = false;
290   const R600Subtarget &STM = MF.getSubtarget<R600Subtarget>();
291   const R600RegisterInfo *RI = STM.getRegisterInfo();
292   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
293 
294   for (const MachineBasicBlock &MBB : MF) {
295     for (const MachineInstr &MI : MBB) {
296       if (MI.getOpcode() == AMDGPU::KILLGT)
297         killPixel = true;
298       unsigned numOperands = MI.getNumOperands();
299       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
300         const MachineOperand &MO = MI.getOperand(op_idx);
301         if (!MO.isReg())
302           continue;
303         unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
304 
305         // Register with value > 127 aren't GPR
306         if (HWReg > 127)
307           continue;
308         MaxGPR = std::max(MaxGPR, HWReg);
309       }
310     }
311   }
312 
313   unsigned RsrcReg;
314   if (STM.getGeneration() >= R600Subtarget::EVERGREEN) {
315     // Evergreen / Northern Islands
316     switch (MF.getFunction()->getCallingConv()) {
317     default: LLVM_FALLTHROUGH;
318     case CallingConv::AMDGPU_CS: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
319     case CallingConv::AMDGPU_GS: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
320     case CallingConv::AMDGPU_PS: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
321     case CallingConv::AMDGPU_VS: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
322     }
323   } else {
324     // R600 / R700
325     switch (MF.getFunction()->getCallingConv()) {
326     default: LLVM_FALLTHROUGH;
327     case CallingConv::AMDGPU_GS: LLVM_FALLTHROUGH;
328     case CallingConv::AMDGPU_CS: LLVM_FALLTHROUGH;
329     case CallingConv::AMDGPU_VS: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
330     case CallingConv::AMDGPU_PS: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
331     }
332   }
333 
334   OutStreamer->EmitIntValue(RsrcReg, 4);
335   OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
336                            S_STACK_SIZE(MFI->CFStackSize), 4);
337   OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
338   OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
339 
340   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
341     OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
342     OutStreamer->EmitIntValue(alignTo(MFI->getLDSSize(), 4) >> 2, 4);
343   }
344 }
345 
346 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
347                                         const MachineFunction &MF) const {
348   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
349   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
350   uint64_t CodeSize = 0;
351   unsigned MaxSGPR = 0;
352   unsigned MaxVGPR = 0;
353   bool VCCUsed = false;
354   bool FlatUsed = false;
355   const SIRegisterInfo *RI = STM.getRegisterInfo();
356   const SIInstrInfo *TII = STM.getInstrInfo();
357 
358   for (const MachineBasicBlock &MBB : MF) {
359     for (const MachineInstr &MI : MBB) {
360       // TODO: CodeSize should account for multiple functions.
361 
362       // TODO: Should we count size of debug info?
363       if (MI.isDebugValue())
364         continue;
365 
366       if (isVerbose())
367         CodeSize += TII->getInstSizeInBytes(MI);
368 
369       unsigned numOperands = MI.getNumOperands();
370       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
371         const MachineOperand &MO = MI.getOperand(op_idx);
372         unsigned width = 0;
373         bool isSGPR = false;
374 
375         if (!MO.isReg())
376           continue;
377 
378         unsigned reg = MO.getReg();
379         switch (reg) {
380         case AMDGPU::EXEC:
381         case AMDGPU::EXEC_LO:
382         case AMDGPU::EXEC_HI:
383         case AMDGPU::SCC:
384         case AMDGPU::M0:
385           continue;
386 
387         case AMDGPU::VCC:
388         case AMDGPU::VCC_LO:
389         case AMDGPU::VCC_HI:
390           VCCUsed = true;
391           continue;
392 
393         case AMDGPU::FLAT_SCR:
394         case AMDGPU::FLAT_SCR_LO:
395         case AMDGPU::FLAT_SCR_HI:
396           FlatUsed = true;
397           continue;
398 
399         case AMDGPU::TBA:
400         case AMDGPU::TBA_LO:
401         case AMDGPU::TBA_HI:
402         case AMDGPU::TMA:
403         case AMDGPU::TMA_LO:
404         case AMDGPU::TMA_HI:
405           llvm_unreachable("trap handler registers should not be used");
406 
407         default:
408           break;
409         }
410 
411         if (AMDGPU::SReg_32RegClass.contains(reg)) {
412           assert(!AMDGPU::TTMP_32RegClass.contains(reg) &&
413                  "trap handler registers should not be used");
414           isSGPR = true;
415           width = 1;
416         } else if (AMDGPU::VGPR_32RegClass.contains(reg)) {
417           isSGPR = false;
418           width = 1;
419         } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
420           assert(!AMDGPU::TTMP_64RegClass.contains(reg) &&
421                  "trap handler registers should not be used");
422           isSGPR = true;
423           width = 2;
424         } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
425           isSGPR = false;
426           width = 2;
427         } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
428           isSGPR = false;
429           width = 3;
430         } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
431           isSGPR = true;
432           width = 4;
433         } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
434           isSGPR = false;
435           width = 4;
436         } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
437           isSGPR = true;
438           width = 8;
439         } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
440           isSGPR = false;
441           width = 8;
442         } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
443           isSGPR = true;
444           width = 16;
445         } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
446           isSGPR = false;
447           width = 16;
448         } else {
449           llvm_unreachable("Unknown register class");
450         }
451         unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
452         unsigned maxUsed = hwReg + width - 1;
453         if (isSGPR) {
454           MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
455         } else {
456           MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
457         }
458       }
459     }
460   }
461 
462   unsigned ExtraSGPRs = 0;
463 
464   if (VCCUsed)
465     ExtraSGPRs = 2;
466 
467   if (STM.getGeneration() < SISubtarget::VOLCANIC_ISLANDS) {
468     if (FlatUsed)
469       ExtraSGPRs = 4;
470   } else {
471     if (STM.isXNACKEnabled())
472       ExtraSGPRs = 4;
473 
474     if (FlatUsed)
475       ExtraSGPRs = 6;
476   }
477 
478   // Record first reserved register and reserved register count fields, and
479   // update max register counts if "amdgpu-debugger-reserve-regs" attribute was
480   // requested.
481   ProgInfo.ReservedVGPRFirst = STM.debuggerReserveRegs() ? MaxVGPR + 1 : 0;
482   ProgInfo.ReservedVGPRCount = RI->getNumDebuggerReservedVGPRs(STM);
483 
484   // Update DebuggerWavefrontPrivateSegmentOffsetSGPR and
485   // DebuggerPrivateSegmentBufferSGPR fields if "amdgpu-debugger-emit-prologue"
486   // attribute was requested.
487   if (STM.debuggerEmitPrologue()) {
488     ProgInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR =
489       RI->getHWRegIndex(MFI->getScratchWaveOffsetReg());
490     ProgInfo.DebuggerPrivateSegmentBufferSGPR =
491       RI->getHWRegIndex(MFI->getScratchRSrcReg());
492   }
493 
494   // Account for extra SGPRs and VGPRs reserved for debugger use.
495   MaxSGPR += ExtraSGPRs;
496   MaxVGPR += RI->getNumDebuggerReservedVGPRs(STM);
497 
498   // We found the maximum register index. They start at 0, so add one to get the
499   // number of registers.
500   ProgInfo.NumVGPR = MaxVGPR + 1;
501   ProgInfo.NumSGPR = MaxSGPR + 1;
502 
503   // Adjust number of registers used to meet default/requested minimum/maximum
504   // number of waves per execution unit request.
505   ProgInfo.NumSGPRsForWavesPerEU = std::max(
506     ProgInfo.NumSGPR, RI->getMinNumSGPRs(STM, MFI->getMaxWavesPerEU()));
507   ProgInfo.NumVGPRsForWavesPerEU = std::max(
508     ProgInfo.NumVGPR, RI->getMinNumVGPRs(MFI->getMaxWavesPerEU()));
509 
510   unsigned MaxNumSGPRs = STM.getMaxNumSGPRs();
511   if (ProgInfo.NumSGPR > MaxNumSGPRs) {
512     // This can happen due to a compiler bug or when using inline asm to use the
513     // registers which are usually reserved for vcc etc.
514 
515     LLVMContext &Ctx = MF.getFunction()->getContext();
516     DiagnosticInfoResourceLimit Diag(*MF.getFunction(),
517                                      "scalar registers",
518                                      ProgInfo.NumSGPR, DS_Error,
519                                      DK_ResourceLimit, MaxNumSGPRs);
520     Ctx.diagnose(Diag);
521     ProgInfo.NumSGPR = MaxNumSGPRs;
522     ProgInfo.NumSGPRsForWavesPerEU = MaxNumSGPRs;
523   }
524 
525   if (STM.hasSGPRInitBug()) {
526     ProgInfo.NumSGPR = SISubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG;
527     ProgInfo.NumSGPRsForWavesPerEU = SISubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG;
528   }
529 
530   if (MFI->NumUserSGPRs > STM.getMaxNumUserSGPRs()) {
531     LLVMContext &Ctx = MF.getFunction()->getContext();
532     DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "user SGPRs",
533                                      MFI->NumUserSGPRs, DS_Error);
534     Ctx.diagnose(Diag);
535   }
536 
537   if (MFI->getLDSSize() > static_cast<unsigned>(STM.getLocalMemorySize())) {
538     LLVMContext &Ctx = MF.getFunction()->getContext();
539     DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "local memory",
540                                      MFI->getLDSSize(), DS_Error);
541     Ctx.diagnose(Diag);
542   }
543 
544   // SGPRBlocks is actual number of SGPR blocks minus 1.
545   ProgInfo.SGPRBlocks = alignTo(ProgInfo.NumSGPRsForWavesPerEU,
546                                 RI->getSGPRAllocGranule());
547   ProgInfo.SGPRBlocks = ProgInfo.SGPRBlocks / RI->getSGPRAllocGranule() - 1;
548 
549   // VGPRBlocks is actual number of VGPR blocks minus 1.
550   ProgInfo.VGPRBlocks = alignTo(ProgInfo.NumVGPRsForWavesPerEU,
551                                 RI->getVGPRAllocGranule());
552   ProgInfo.VGPRBlocks = ProgInfo.VGPRBlocks / RI->getVGPRAllocGranule() - 1;
553 
554   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
555   // register.
556   ProgInfo.FloatMode = getFPMode(MF);
557 
558   ProgInfo.IEEEMode = STM.enableIEEEBit(MF);
559 
560   // Make clamp modifier on NaN input returns 0.
561   ProgInfo.DX10Clamp = 1;
562 
563   const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
564   ProgInfo.ScratchSize = FrameInfo.getStackSize();
565 
566   ProgInfo.FlatUsed = FlatUsed;
567   ProgInfo.VCCUsed = VCCUsed;
568   ProgInfo.CodeLen = CodeSize;
569 
570   unsigned LDSAlignShift;
571   if (STM.getGeneration() < SISubtarget::SEA_ISLANDS) {
572     // LDS is allocated in 64 dword blocks.
573     LDSAlignShift = 8;
574   } else {
575     // LDS is allocated in 128 dword blocks.
576     LDSAlignShift = 9;
577   }
578 
579   unsigned LDSSpillSize =
580     MFI->LDSWaveSpillSize * MFI->getMaxFlatWorkGroupSize();
581 
582   ProgInfo.LDSSize = MFI->getLDSSize() + LDSSpillSize;
583   ProgInfo.LDSBlocks =
584       alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
585 
586   // Scratch is allocated in 256 dword blocks.
587   unsigned ScratchAlignShift = 10;
588   // We need to program the hardware with the amount of scratch memory that
589   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
590   // scratch memory used per thread.
591   ProgInfo.ScratchBlocks =
592       alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
593               1ULL << ScratchAlignShift) >>
594       ScratchAlignShift;
595 
596   ProgInfo.ComputePGMRSrc1 =
597       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
598       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
599       S_00B848_PRIORITY(ProgInfo.Priority) |
600       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
601       S_00B848_PRIV(ProgInfo.Priv) |
602       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
603       S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
604       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
605 
606   // 0 = X, 1 = XY, 2 = XYZ
607   unsigned TIDIGCompCnt = 0;
608   if (MFI->hasWorkItemIDZ())
609     TIDIGCompCnt = 2;
610   else if (MFI->hasWorkItemIDY())
611     TIDIGCompCnt = 1;
612 
613   ProgInfo.ComputePGMRSrc2 =
614       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
615       S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
616       S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
617       S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
618       S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
619       S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
620       S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
621       S_00B84C_EXCP_EN_MSB(0) |
622       S_00B84C_LDS_SIZE(ProgInfo.LDSBlocks) |
623       S_00B84C_EXCP_EN(0);
624 }
625 
626 static unsigned getRsrcReg(CallingConv::ID CallConv) {
627   switch (CallConv) {
628   default: LLVM_FALLTHROUGH;
629   case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
630   case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
631   case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
632   case CallingConv::AMDGPU_VS: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
633   }
634 }
635 
636 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
637                                          const SIProgramInfo &KernelInfo) {
638   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
639   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
640   unsigned RsrcReg = getRsrcReg(MF.getFunction()->getCallingConv());
641 
642   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
643     OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
644 
645     OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc1, 4);
646 
647     OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
648     OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc2, 4);
649 
650     OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
651     OutStreamer->EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4);
652 
653     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
654     // 0" comment but I don't see a corresponding field in the register spec.
655   } else {
656     OutStreamer->EmitIntValue(RsrcReg, 4);
657     OutStreamer->EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
658                               S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4);
659     if (STM.isVGPRSpillingEnabled(*MF.getFunction())) {
660       OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
661       OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(KernelInfo.ScratchBlocks), 4);
662     }
663   }
664 
665   if (MF.getFunction()->getCallingConv() == CallingConv::AMDGPU_PS) {
666     OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
667     OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4);
668     OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
669     OutStreamer->EmitIntValue(MFI->PSInputEna, 4);
670     OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
671     OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4);
672   }
673 
674   OutStreamer->EmitIntValue(R_SPILLED_SGPRS, 4);
675   OutStreamer->EmitIntValue(MFI->getNumSpilledSGPRs(), 4);
676   OutStreamer->EmitIntValue(R_SPILLED_VGPRS, 4);
677   OutStreamer->EmitIntValue(MFI->getNumSpilledVGPRs(), 4);
678 }
679 
680 // This is supposed to be log2(Size)
681 static amd_element_byte_size_t getElementByteSizeValue(unsigned Size) {
682   switch (Size) {
683   case 4:
684     return AMD_ELEMENT_4_BYTES;
685   case 8:
686     return AMD_ELEMENT_8_BYTES;
687   case 16:
688     return AMD_ELEMENT_16_BYTES;
689   default:
690     llvm_unreachable("invalid private_element_size");
691   }
692 }
693 
694 void AMDGPUAsmPrinter::EmitAmdKernelCodeT(const MachineFunction &MF,
695                                          const SIProgramInfo &KernelInfo) const {
696   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
697   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
698   amd_kernel_code_t header;
699 
700   AMDGPU::initDefaultAMDKernelCodeT(header, STM.getFeatureBits());
701 
702   header.compute_pgm_resource_registers =
703       KernelInfo.ComputePGMRSrc1 |
704       (KernelInfo.ComputePGMRSrc2 << 32);
705   header.code_properties = AMD_CODE_PROPERTY_IS_PTR64;
706 
707 
708   AMD_HSA_BITS_SET(header.code_properties,
709                    AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE,
710                    getElementByteSizeValue(STM.getMaxPrivateElementSize()));
711 
712   if (MFI->hasPrivateSegmentBuffer()) {
713     header.code_properties |=
714       AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
715   }
716 
717   if (MFI->hasDispatchPtr())
718     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
719 
720   if (MFI->hasQueuePtr())
721     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
722 
723   if (MFI->hasKernargSegmentPtr())
724     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
725 
726   if (MFI->hasDispatchID())
727     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
728 
729   if (MFI->hasFlatScratchInit())
730     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
731 
732   // TODO: Private segment size
733 
734   if (MFI->hasGridWorkgroupCountX()) {
735     header.code_properties |=
736       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X;
737   }
738 
739   if (MFI->hasGridWorkgroupCountY()) {
740     header.code_properties |=
741       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y;
742   }
743 
744   if (MFI->hasGridWorkgroupCountZ()) {
745     header.code_properties |=
746       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z;
747   }
748 
749   if (MFI->hasDispatchPtr())
750     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
751 
752   if (STM.debuggerSupported())
753     header.code_properties |= AMD_CODE_PROPERTY_IS_DEBUG_SUPPORTED;
754 
755   if (STM.isXNACKEnabled())
756     header.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED;
757 
758   // FIXME: Should use getKernArgSize
759   header.kernarg_segment_byte_size =
760       STM.getKernArgSegmentSize(MFI->getABIArgOffset());
761   header.wavefront_sgpr_count = KernelInfo.NumSGPR;
762   header.workitem_vgpr_count = KernelInfo.NumVGPR;
763   header.workitem_private_segment_byte_size = KernelInfo.ScratchSize;
764   header.workgroup_group_segment_byte_size = KernelInfo.LDSSize;
765   header.reserved_vgpr_first = KernelInfo.ReservedVGPRFirst;
766   header.reserved_vgpr_count = KernelInfo.ReservedVGPRCount;
767 
768   if (STM.debuggerEmitPrologue()) {
769     header.debug_wavefront_private_segment_offset_sgpr =
770       KernelInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR;
771     header.debug_private_segment_buffer_sgpr =
772       KernelInfo.DebuggerPrivateSegmentBufferSGPR;
773   }
774 
775   AMDGPUTargetStreamer *TS =
776       static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
777 
778   OutStreamer->SwitchSection(getObjFileLowering().getTextSection());
779   TS->EmitAMDKernelCodeT(header);
780 }
781 
782 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
783                                        unsigned AsmVariant,
784                                        const char *ExtraCode, raw_ostream &O) {
785   if (ExtraCode && ExtraCode[0]) {
786     if (ExtraCode[1] != 0)
787       return true; // Unknown modifier.
788 
789     switch (ExtraCode[0]) {
790     default:
791       // See if this is a generic print operand
792       return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
793     case 'r':
794       break;
795     }
796   }
797 
798   AMDGPUInstPrinter::printRegOperand(MI->getOperand(OpNo).getReg(), O,
799                    *TM.getSubtargetImpl(*MF->getFunction())->getRegisterInfo());
800   return false;
801 }
802 
803 // Emit a key and an integer value for runtime metadata.
804 static void emitRuntimeMDIntValue(MCStreamer &Streamer,
805                                   RuntimeMD::Key K, uint64_t V,
806                                   unsigned Size) {
807   Streamer.EmitIntValue(K, 1);
808   Streamer.EmitIntValue(V, Size);
809 }
810 
811 // Emit a key and a string value for runtime metadata.
812 static void emitRuntimeMDStringValue(MCStreamer &Streamer,
813                                      RuntimeMD::Key K, StringRef S) {
814   Streamer.EmitIntValue(K, 1);
815   Streamer.EmitIntValue(S.size(), 4);
816   Streamer.EmitBytes(S);
817 }
818 
819 // Emit a key and three integer values for runtime metadata.
820 // The three integer values are obtained from MDNode \p Node;
821 static void emitRuntimeMDThreeIntValues(MCStreamer &Streamer,
822                                         RuntimeMD::Key K, MDNode *Node,
823                                         unsigned Size) {
824   assert(Node->getNumOperands() == 3);
825 
826   Streamer.EmitIntValue(K, 1);
827   for (const MDOperand &Op : Node->operands()) {
828     const ConstantInt *CI = mdconst::extract<ConstantInt>(Op);
829     Streamer.EmitIntValue(CI->getZExtValue(), Size);
830   }
831 }
832 
833 void AMDGPUAsmPrinter::emitStartOfRuntimeMetadata(const Module &M) {
834   OutStreamer->SwitchSection(getObjFileLowering().getContext()
835     .getELFSection(RuntimeMD::SectionName, ELF::SHT_PROGBITS, 0));
836 
837   emitRuntimeMDIntValue(*OutStreamer, RuntimeMD::KeyMDVersion,
838                         RuntimeMD::MDVersion << 8 | RuntimeMD::MDRevision, 2);
839   if (auto MD = M.getNamedMetadata("opencl.ocl.version")) {
840     if (MD->getNumOperands() != 0) {
841       auto Node = MD->getOperand(0);
842       if (Node->getNumOperands() > 1) {
843         emitRuntimeMDIntValue(*OutStreamer, RuntimeMD::KeyLanguage,
844                               RuntimeMD::OpenCL_C, 1);
845         uint16_t Major = mdconst::extract<ConstantInt>(Node->getOperand(0))
846                          ->getZExtValue();
847         uint16_t Minor = mdconst::extract<ConstantInt>(Node->getOperand(1))
848                          ->getZExtValue();
849         emitRuntimeMDIntValue(*OutStreamer, RuntimeMD::KeyLanguageVersion,
850                               Major * 100 + Minor * 10, 2);
851       }
852     }
853   }
854 
855   if (auto MD = M.getNamedMetadata("llvm.printf.fmts")) {
856     for (unsigned I = 0; I < MD->getNumOperands(); ++I) {
857       auto Node = MD->getOperand(I);
858       if (Node->getNumOperands() > 0)
859         emitRuntimeMDStringValue(*OutStreamer, RuntimeMD::KeyPrintfInfo,
860             cast<MDString>(Node->getOperand(0))->getString());
861     }
862   }
863 }
864 
865 static std::string getOCLTypeName(Type *Ty, bool Signed) {
866   switch (Ty->getTypeID()) {
867   case Type::HalfTyID:
868     return "half";
869   case Type::FloatTyID:
870     return "float";
871   case Type::DoubleTyID:
872     return "double";
873   case Type::IntegerTyID: {
874     if (!Signed)
875       return (Twine('u') + getOCLTypeName(Ty, true)).str();
876     unsigned BW = Ty->getIntegerBitWidth();
877     switch (BW) {
878     case 8:
879       return "char";
880     case 16:
881       return "short";
882     case 32:
883       return "int";
884     case 64:
885       return "long";
886     default:
887       return (Twine('i') + Twine(BW)).str();
888     }
889   }
890   case Type::VectorTyID: {
891     VectorType *VecTy = cast<VectorType>(Ty);
892     Type *EleTy = VecTy->getElementType();
893     unsigned Size = VecTy->getVectorNumElements();
894     return (Twine(getOCLTypeName(EleTy, Signed)) + Twine(Size)).str();
895   }
896   default:
897     return "unknown";
898   }
899 }
900 
901 static RuntimeMD::KernelArg::ValueType getRuntimeMDValueType(
902   Type *Ty, StringRef TypeName) {
903   switch (Ty->getTypeID()) {
904   case Type::HalfTyID:
905     return RuntimeMD::KernelArg::F16;
906   case Type::FloatTyID:
907     return RuntimeMD::KernelArg::F32;
908   case Type::DoubleTyID:
909     return RuntimeMD::KernelArg::F64;
910   case Type::IntegerTyID: {
911     bool Signed = !TypeName.startswith("u");
912     switch (Ty->getIntegerBitWidth()) {
913     case 8:
914       return Signed ? RuntimeMD::KernelArg::I8 : RuntimeMD::KernelArg::U8;
915     case 16:
916       return Signed ? RuntimeMD::KernelArg::I16 : RuntimeMD::KernelArg::U16;
917     case 32:
918       return Signed ? RuntimeMD::KernelArg::I32 : RuntimeMD::KernelArg::U32;
919     case 64:
920       return Signed ? RuntimeMD::KernelArg::I64 : RuntimeMD::KernelArg::U64;
921     default:
922       // Runtime does not recognize other integer types. Report as struct type.
923       return RuntimeMD::KernelArg::Struct;
924     }
925   }
926   case Type::VectorTyID:
927     return getRuntimeMDValueType(Ty->getVectorElementType(), TypeName);
928   case Type::PointerTyID:
929     return getRuntimeMDValueType(Ty->getPointerElementType(), TypeName);
930   default:
931     return RuntimeMD::KernelArg::Struct;
932   }
933 }
934 
935 static RuntimeMD::KernelArg::AddressSpaceQualifer getRuntimeAddrSpace(
936     AMDGPUAS::AddressSpaces A) {
937   switch (A) {
938   case AMDGPUAS::GLOBAL_ADDRESS:
939     return RuntimeMD::KernelArg::Global;
940   case AMDGPUAS::CONSTANT_ADDRESS:
941     return RuntimeMD::KernelArg::Constant;
942   case AMDGPUAS::LOCAL_ADDRESS:
943     return RuntimeMD::KernelArg::Local;
944   case AMDGPUAS::FLAT_ADDRESS:
945     return RuntimeMD::KernelArg::Generic;
946   case AMDGPUAS::REGION_ADDRESS:
947     return RuntimeMD::KernelArg::Region;
948   default:
949     return RuntimeMD::KernelArg::Private;
950   }
951 }
952 
953 static void emitRuntimeMetadataForKernelArg(const DataLayout &DL,
954     MCStreamer &OutStreamer, Type *T,
955     RuntimeMD::KernelArg::Kind Kind,
956     StringRef BaseTypeName = "", StringRef TypeName = "",
957     StringRef ArgName = "", StringRef TypeQual = "", StringRef AccQual = "") {
958   // Emit KeyArgBegin.
959   OutStreamer.EmitIntValue(RuntimeMD::KeyArgBegin, 1);
960 
961   // Emit KeyArgSize and KeyArgAlign.
962   emitRuntimeMDIntValue(OutStreamer, RuntimeMD::KeyArgSize,
963                         DL.getTypeAllocSize(T), 4);
964   emitRuntimeMDIntValue(OutStreamer, RuntimeMD::KeyArgAlign,
965                         DL.getABITypeAlignment(T), 4);
966   if (auto PT = dyn_cast<PointerType>(T)) {
967     auto ET = PT->getElementType();
968     if (PT->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS && ET->isSized())
969       emitRuntimeMDIntValue(OutStreamer, RuntimeMD::KeyArgPointeeAlign,
970                         DL.getABITypeAlignment(ET), 4);
971   }
972 
973   // Emit KeyArgTypeName.
974   if (!TypeName.empty())
975     emitRuntimeMDStringValue(OutStreamer, RuntimeMD::KeyArgTypeName, TypeName);
976 
977   // Emit KeyArgName.
978   if (!ArgName.empty())
979     emitRuntimeMDStringValue(OutStreamer, RuntimeMD::KeyArgName, ArgName);
980 
981   // Emit KeyArgIsVolatile, KeyArgIsRestrict, KeyArgIsConst and KeyArgIsPipe.
982   SmallVector<StringRef, 1> SplitQ;
983   TypeQual.split(SplitQ, " ", -1, false /* Drop empty entry */);
984 
985   for (StringRef KeyName : SplitQ) {
986     auto Key = StringSwitch<RuntimeMD::Key>(KeyName)
987       .Case("volatile", RuntimeMD::KeyArgIsVolatile)
988       .Case("restrict", RuntimeMD::KeyArgIsRestrict)
989       .Case("const",    RuntimeMD::KeyArgIsConst)
990       .Case("pipe",     RuntimeMD::KeyArgIsPipe)
991       .Default(RuntimeMD::KeyNull);
992     OutStreamer.EmitIntValue(Key, 1);
993   }
994 
995   // Emit KeyArgKind.
996   emitRuntimeMDIntValue(OutStreamer, RuntimeMD::KeyArgKind, Kind, 1);
997 
998   // Emit KeyArgValueType.
999   emitRuntimeMDIntValue(OutStreamer, RuntimeMD::KeyArgValueType,
1000                         getRuntimeMDValueType(T, BaseTypeName), 2);
1001 
1002   // Emit KeyArgAccQual.
1003   if (!AccQual.empty()) {
1004     auto AQ = StringSwitch<RuntimeMD::KernelArg::AccessQualifer>(AccQual)
1005       .Case("read_only",  RuntimeMD::KernelArg::ReadOnly)
1006       .Case("write_only", RuntimeMD::KernelArg::WriteOnly)
1007       .Case("read_write", RuntimeMD::KernelArg::ReadWrite)
1008       .Default(RuntimeMD::KernelArg::None);
1009     emitRuntimeMDIntValue(OutStreamer, RuntimeMD::KeyArgAccQual, AQ, 1);
1010   }
1011 
1012   // Emit KeyArgAddrQual.
1013   if (auto *PT = dyn_cast<PointerType>(T))
1014     emitRuntimeMDIntValue(OutStreamer, RuntimeMD::KeyArgAddrQual,
1015         getRuntimeAddrSpace(static_cast<AMDGPUAS::AddressSpaces>(
1016             PT->getAddressSpace())), 1);
1017 
1018   // Emit KeyArgEnd
1019   OutStreamer.EmitIntValue(RuntimeMD::KeyArgEnd, 1);
1020 }
1021 
1022 void AMDGPUAsmPrinter::emitRuntimeMetadata(const Function &F) {
1023   if (!F.getMetadata("kernel_arg_type"))
1024     return;
1025 
1026   MCContext &Context = getObjFileLowering().getContext();
1027   OutStreamer->SwitchSection(
1028       Context.getELFSection(RuntimeMD::SectionName, ELF::SHT_PROGBITS, 0));
1029   OutStreamer->EmitIntValue(RuntimeMD::KeyKernelBegin, 1);
1030   emitRuntimeMDStringValue(*OutStreamer, RuntimeMD::KeyKernelName, F.getName());
1031 
1032   const DataLayout &DL = F.getParent()->getDataLayout();
1033   for (auto &Arg : F.args()) {
1034     unsigned I = Arg.getArgNo();
1035     Type *T = Arg.getType();
1036     auto TypeName = dyn_cast<MDString>(F.getMetadata(
1037         "kernel_arg_type")->getOperand(I))->getString();
1038     auto BaseTypeName = cast<MDString>(F.getMetadata(
1039         "kernel_arg_base_type")->getOperand(I))->getString();
1040     StringRef ArgName;
1041     if (auto ArgNameMD = F.getMetadata("kernel_arg_name"))
1042       ArgName = cast<MDString>(ArgNameMD->getOperand(I))->getString();
1043     auto TypeQual = cast<MDString>(F.getMetadata(
1044         "kernel_arg_type_qual")->getOperand(I))->getString();
1045     auto AccQual = cast<MDString>(F.getMetadata(
1046         "kernel_arg_access_qual")->getOperand(I))->getString();
1047     RuntimeMD::KernelArg::Kind Kind;
1048     if (TypeQual.find("pipe") != StringRef::npos)
1049       Kind = RuntimeMD::KernelArg::Pipe;
1050     else Kind = StringSwitch<RuntimeMD::KernelArg::Kind>(BaseTypeName)
1051       .Case("sampler_t", RuntimeMD::KernelArg::Sampler)
1052       .Case("queue_t",   RuntimeMD::KernelArg::Queue)
1053       .Cases("image1d_t", "image1d_array_t", "image1d_buffer_t",
1054              "image2d_t" , "image2d_array_t",  RuntimeMD::KernelArg::Image)
1055       .Cases("image2d_depth_t", "image2d_array_depth_t",
1056              "image2d_msaa_t", "image2d_array_msaa_t",
1057              "image2d_msaa_depth_t",  RuntimeMD::KernelArg::Image)
1058       .Cases("image2d_array_msaa_depth_t", "image3d_t",
1059              RuntimeMD::KernelArg::Image)
1060       .Default(isa<PointerType>(T) ?
1061                    (T->getPointerAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ?
1062                    RuntimeMD::KernelArg::DynamicSharedPointer :
1063                    RuntimeMD::KernelArg::GlobalBuffer) :
1064                    RuntimeMD::KernelArg::ByValue);
1065     emitRuntimeMetadataForKernelArg(DL, *OutStreamer, T,
1066         Kind, BaseTypeName, TypeName, ArgName, TypeQual, AccQual);
1067   }
1068 
1069   // Emit hidden kernel arguments for OpenCL kernels.
1070   if (F.getParent()->getNamedMetadata("opencl.ocl.version")) {
1071     auto Int64T = Type::getInt64Ty(F.getContext());
1072     emitRuntimeMetadataForKernelArg(DL, *OutStreamer, Int64T,
1073                                     RuntimeMD::KernelArg::HiddenGlobalOffsetX);
1074     emitRuntimeMetadataForKernelArg(DL, *OutStreamer, Int64T,
1075                                     RuntimeMD::KernelArg::HiddenGlobalOffsetY);
1076     emitRuntimeMetadataForKernelArg(DL, *OutStreamer, Int64T,
1077                                     RuntimeMD::KernelArg::HiddenGlobalOffsetZ);
1078     if (F.getParent()->getNamedMetadata("llvm.printf.fmts")) {
1079       auto Int8PtrT = Type::getInt8PtrTy(F.getContext(),
1080           RuntimeMD::KernelArg::Global);
1081       emitRuntimeMetadataForKernelArg(DL, *OutStreamer, Int8PtrT,
1082                                       RuntimeMD::KernelArg::HiddenPrintfBuffer);
1083     }
1084   }
1085 
1086   // Emit KeyReqdWorkGroupSize, KeyWorkGroupSizeHint, and KeyVecTypeHint.
1087   if (auto RWGS = F.getMetadata("reqd_work_group_size")) {
1088     emitRuntimeMDThreeIntValues(*OutStreamer, RuntimeMD::KeyReqdWorkGroupSize,
1089                                 RWGS, 4);
1090   }
1091 
1092   if (auto WGSH = F.getMetadata("work_group_size_hint")) {
1093     emitRuntimeMDThreeIntValues(*OutStreamer, RuntimeMD::KeyWorkGroupSizeHint,
1094                                 WGSH, 4);
1095   }
1096 
1097   if (auto VTH = F.getMetadata("vec_type_hint")) {
1098     auto TypeName = getOCLTypeName(cast<ValueAsMetadata>(
1099       VTH->getOperand(0))->getType(), mdconst::extract<ConstantInt>(
1100       VTH->getOperand(1))->getZExtValue());
1101     emitRuntimeMDStringValue(*OutStreamer, RuntimeMD::KeyVecTypeHint, TypeName);
1102   }
1103 
1104   // Emit KeyKernelEnd
1105   OutStreamer->EmitIntValue(RuntimeMD::KeyKernelEnd, 1);
1106 }
1107