1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
15 //
16 //===----------------------------------------------------------------------===//
17 //
18 
19 #include "AMDGPUAsmPrinter.h"
20 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
21 #include "InstPrinter/AMDGPUInstPrinter.h"
22 #include "Utils/AMDGPUBaseInfo.h"
23 #include "AMDGPU.h"
24 #include "AMDKernelCodeT.h"
25 #include "AMDGPUSubtarget.h"
26 #include "R600Defines.h"
27 #include "R600MachineFunctionInfo.h"
28 #include "R600RegisterInfo.h"
29 #include "SIDefines.h"
30 #include "SIMachineFunctionInfo.h"
31 #include "SIInstrInfo.h"
32 #include "SIRegisterInfo.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/IR/DiagnosticInfo.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCSectionELF.h"
37 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/Support/ELF.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Target/TargetLoweringObjectFile.h"
42 
43 using namespace llvm;
44 
45 // TODO: This should get the default rounding mode from the kernel. We just set
46 // the default here, but this could change if the OpenCL rounding mode pragmas
47 // are used.
48 //
49 // The denormal mode here should match what is reported by the OpenCL runtime
50 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
51 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
52 //
53 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
54 // precision, and leaves single precision to flush all and does not report
55 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
56 // CL_FP_DENORM for both.
57 //
58 // FIXME: It seems some instructions do not support single precision denormals
59 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
60 // and sin_f32, cos_f32 on most parts).
61 
62 // We want to use these instructions, and using fp32 denormals also causes
63 // instructions to run at the double precision rate for the device so it's
64 // probably best to just report no single precision denormals.
65 static uint32_t getFPMode(const MachineFunction &F) {
66   const SISubtarget& ST = F.getSubtarget<SISubtarget>();
67   // TODO: Is there any real use for the flush in only / flush out only modes?
68 
69   uint32_t FP32Denormals =
70     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
71 
72   uint32_t FP64Denormals =
73     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
74 
75   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
76          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
77          FP_DENORM_MODE_SP(FP32Denormals) |
78          FP_DENORM_MODE_DP(FP64Denormals);
79 }
80 
81 static AsmPrinter *
82 createAMDGPUAsmPrinterPass(TargetMachine &tm,
83                            std::unique_ptr<MCStreamer> &&Streamer) {
84   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
85 }
86 
87 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
88   TargetRegistry::RegisterAsmPrinter(getTheAMDGPUTarget(),
89                                      createAMDGPUAsmPrinterPass);
90   TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(),
91                                      createAMDGPUAsmPrinterPass);
92 }
93 
94 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
95                                    std::unique_ptr<MCStreamer> Streamer)
96   : AsmPrinter(TM, std::move(Streamer)) {}
97 
98 StringRef AMDGPUAsmPrinter::getPassName() const {
99   return "AMDGPU Assembly Printer";
100 }
101 
102 void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) {
103   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
104     return;
105 
106   AMDGPUTargetStreamer *TS =
107       static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
108 
109   TS->EmitDirectiveHSACodeObjectVersion(2, 1);
110 
111   const MCSubtargetInfo *STI = TM.getMCSubtargetInfo();
112   AMDGPU::IsaInfo::IsaVersion ISA =
113       AMDGPU::IsaInfo::getIsaVersion(STI->getFeatureBits());
114   TS->EmitDirectiveHSACodeObjectISA(ISA.Major, ISA.Minor, ISA.Stepping,
115                                     "AMD", "AMDGPU");
116 
117   // Emit runtime metadata.
118   TS->EmitRuntimeMetadata(STI->getFeatureBits(), M);
119 }
120 
121 bool AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough(
122   const MachineBasicBlock *MBB) const {
123   if (!AsmPrinter::isBlockOnlyReachableByFallthrough(MBB))
124     return false;
125 
126   if (MBB->empty())
127     return true;
128 
129   // If this is a block implementing a long branch, an expression relative to
130   // the start of the block is needed.  to the start of the block.
131   // XXX - Is there a smarter way to check this?
132   return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
133 }
134 
135 
136 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
137   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
138   SIProgramInfo KernelInfo;
139   if (STM.isAmdCodeObjectV2(*MF)) {
140     getSIProgramInfo(KernelInfo, *MF);
141     EmitAmdKernelCodeT(*MF, KernelInfo);
142   }
143 }
144 
145 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
146   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
147   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
148   if (MFI->isKernel() && STM.isAmdCodeObjectV2(*MF)) {
149     AMDGPUTargetStreamer *TS =
150         static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
151     SmallString<128> SymbolName;
152     getNameWithPrefix(SymbolName, MF->getFunction()),
153     TS->EmitAMDGPUSymbolType(SymbolName, ELF::STT_AMDGPU_HSA_KERNEL);
154   }
155 
156   AsmPrinter::EmitFunctionEntryLabel();
157 }
158 
159 void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
160 
161   // Group segment variables aren't emitted in HSA.
162   if (AMDGPU::isGroupSegment(GV))
163     return;
164 
165   AsmPrinter::EmitGlobalVariable(GV);
166 }
167 
168 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
169 
170   // The starting address of all shader programs must be 256 bytes aligned.
171   MF.setAlignment(8);
172 
173   SetupMachineFunction(MF);
174 
175   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
176   MCContext &Context = getObjFileLowering().getContext();
177   if (!STM.isAmdHsaOS()) {
178     MCSectionELF *ConfigSection =
179         Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
180     OutStreamer->SwitchSection(ConfigSection);
181   }
182 
183   SIProgramInfo KernelInfo;
184   if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
185     getSIProgramInfo(KernelInfo, MF);
186     if (!STM.isAmdHsaOS()) {
187       EmitProgramInfoSI(MF, KernelInfo);
188     }
189   } else {
190     EmitProgramInfoR600(MF);
191   }
192 
193   DisasmLines.clear();
194   HexLines.clear();
195   DisasmLineMaxLen = 0;
196 
197   EmitFunctionBody();
198 
199   if (isVerbose()) {
200     MCSectionELF *CommentSection =
201         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
202     OutStreamer->SwitchSection(CommentSection);
203 
204     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
205       OutStreamer->emitRawComment(" Kernel info:", false);
206       OutStreamer->emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
207                                   false);
208       OutStreamer->emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
209                                   false);
210       OutStreamer->emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
211                                   false);
212       OutStreamer->emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
213                                   false);
214       OutStreamer->emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
215                                   false);
216       OutStreamer->emitRawComment(" ScratchSize: " + Twine(KernelInfo.ScratchSize),
217                                   false);
218       OutStreamer->emitRawComment(" LDSByteSize: " + Twine(KernelInfo.LDSSize) +
219                                   " bytes/workgroup (compile time only)", false);
220 
221       OutStreamer->emitRawComment(" SGPRBlocks: " +
222                                   Twine(KernelInfo.SGPRBlocks), false);
223       OutStreamer->emitRawComment(" VGPRBlocks: " +
224                                   Twine(KernelInfo.VGPRBlocks), false);
225 
226       OutStreamer->emitRawComment(" NumSGPRsForWavesPerEU: " +
227                                   Twine(KernelInfo.NumSGPRsForWavesPerEU), false);
228       OutStreamer->emitRawComment(" NumVGPRsForWavesPerEU: " +
229                                   Twine(KernelInfo.NumVGPRsForWavesPerEU), false);
230 
231       OutStreamer->emitRawComment(" ReservedVGPRFirst: " + Twine(KernelInfo.ReservedVGPRFirst),
232                                   false);
233       OutStreamer->emitRawComment(" ReservedVGPRCount: " + Twine(KernelInfo.ReservedVGPRCount),
234                                   false);
235 
236       if (MF.getSubtarget<SISubtarget>().debuggerEmitPrologue()) {
237         OutStreamer->emitRawComment(" DebuggerWavefrontPrivateSegmentOffsetSGPR: s" +
238                                     Twine(KernelInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR), false);
239         OutStreamer->emitRawComment(" DebuggerPrivateSegmentBufferSGPR: s" +
240                                     Twine(KernelInfo.DebuggerPrivateSegmentBufferSGPR), false);
241       }
242 
243       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:USER_SGPR: " +
244                                   Twine(G_00B84C_USER_SGPR(KernelInfo.ComputePGMRSrc2)),
245                                   false);
246       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
247                                   Twine(G_00B84C_TRAP_HANDLER(KernelInfo.ComputePGMRSrc2)),
248                                   false);
249       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_X_EN: " +
250                                   Twine(G_00B84C_TGID_X_EN(KernelInfo.ComputePGMRSrc2)),
251                                   false);
252       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
253                                   Twine(G_00B84C_TGID_Y_EN(KernelInfo.ComputePGMRSrc2)),
254                                   false);
255       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
256                                   Twine(G_00B84C_TGID_Z_EN(KernelInfo.ComputePGMRSrc2)),
257                                   false);
258       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
259                                   Twine(G_00B84C_TIDIG_COMP_CNT(KernelInfo.ComputePGMRSrc2)),
260                                   false);
261 
262     } else {
263       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
264       OutStreamer->emitRawComment(
265         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->CFStackSize)));
266     }
267   }
268 
269   if (STM.dumpCode()) {
270 
271     OutStreamer->SwitchSection(
272         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
273 
274     for (size_t i = 0; i < DisasmLines.size(); ++i) {
275       std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
276       Comment += " ; " + HexLines[i] + "\n";
277 
278       OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
279       OutStreamer->EmitBytes(StringRef(Comment));
280     }
281   }
282 
283   return false;
284 }
285 
286 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
287   unsigned MaxGPR = 0;
288   bool killPixel = false;
289   const R600Subtarget &STM = MF.getSubtarget<R600Subtarget>();
290   const R600RegisterInfo *RI = STM.getRegisterInfo();
291   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
292 
293   for (const MachineBasicBlock &MBB : MF) {
294     for (const MachineInstr &MI : MBB) {
295       if (MI.getOpcode() == AMDGPU::KILLGT)
296         killPixel = true;
297       unsigned numOperands = MI.getNumOperands();
298       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
299         const MachineOperand &MO = MI.getOperand(op_idx);
300         if (!MO.isReg())
301           continue;
302         unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
303 
304         // Register with value > 127 aren't GPR
305         if (HWReg > 127)
306           continue;
307         MaxGPR = std::max(MaxGPR, HWReg);
308       }
309     }
310   }
311 
312   unsigned RsrcReg;
313   if (STM.getGeneration() >= R600Subtarget::EVERGREEN) {
314     // Evergreen / Northern Islands
315     switch (MF.getFunction()->getCallingConv()) {
316     default: LLVM_FALLTHROUGH;
317     case CallingConv::AMDGPU_CS: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
318     case CallingConv::AMDGPU_GS: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
319     case CallingConv::AMDGPU_PS: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
320     case CallingConv::AMDGPU_VS: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
321     }
322   } else {
323     // R600 / R700
324     switch (MF.getFunction()->getCallingConv()) {
325     default: LLVM_FALLTHROUGH;
326     case CallingConv::AMDGPU_GS: LLVM_FALLTHROUGH;
327     case CallingConv::AMDGPU_CS: LLVM_FALLTHROUGH;
328     case CallingConv::AMDGPU_VS: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
329     case CallingConv::AMDGPU_PS: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
330     }
331   }
332 
333   OutStreamer->EmitIntValue(RsrcReg, 4);
334   OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
335                            S_STACK_SIZE(MFI->CFStackSize), 4);
336   OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
337   OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
338 
339   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
340     OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
341     OutStreamer->EmitIntValue(alignTo(MFI->getLDSSize(), 4) >> 2, 4);
342   }
343 }
344 
345 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
346                                         const MachineFunction &MF) const {
347   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
348   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
349   uint64_t CodeSize = 0;
350   unsigned MaxSGPR = 0;
351   unsigned MaxVGPR = 0;
352   bool VCCUsed = false;
353   bool FlatUsed = false;
354   const SIRegisterInfo *RI = STM.getRegisterInfo();
355   const SIInstrInfo *TII = STM.getInstrInfo();
356 
357   for (const MachineBasicBlock &MBB : MF) {
358     for (const MachineInstr &MI : MBB) {
359       // TODO: CodeSize should account for multiple functions.
360 
361       // TODO: Should we count size of debug info?
362       if (MI.isDebugValue())
363         continue;
364 
365       if (isVerbose())
366         CodeSize += TII->getInstSizeInBytes(MI);
367 
368       unsigned numOperands = MI.getNumOperands();
369       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
370         const MachineOperand &MO = MI.getOperand(op_idx);
371         unsigned width = 0;
372         bool isSGPR = false;
373 
374         if (!MO.isReg())
375           continue;
376 
377         unsigned reg = MO.getReg();
378         switch (reg) {
379         case AMDGPU::EXEC:
380         case AMDGPU::EXEC_LO:
381         case AMDGPU::EXEC_HI:
382         case AMDGPU::SCC:
383         case AMDGPU::M0:
384         case AMDGPU::SRC_SHARED_BASE:
385         case AMDGPU::SRC_SHARED_LIMIT:
386         case AMDGPU::SRC_PRIVATE_BASE:
387         case AMDGPU::SRC_PRIVATE_LIMIT:
388           continue;
389 
390         case AMDGPU::VCC:
391         case AMDGPU::VCC_LO:
392         case AMDGPU::VCC_HI:
393           VCCUsed = true;
394           continue;
395 
396         case AMDGPU::FLAT_SCR:
397         case AMDGPU::FLAT_SCR_LO:
398         case AMDGPU::FLAT_SCR_HI:
399           // Even if FLAT_SCRATCH is implicitly used, it has no effect if flat
400           // instructions aren't used to access the scratch buffer.
401           if (MFI->hasFlatScratchInit())
402             FlatUsed = true;
403           continue;
404 
405         case AMDGPU::TBA:
406         case AMDGPU::TBA_LO:
407         case AMDGPU::TBA_HI:
408         case AMDGPU::TMA:
409         case AMDGPU::TMA_LO:
410         case AMDGPU::TMA_HI:
411           llvm_unreachable("trap handler registers should not be used");
412 
413         default:
414           break;
415         }
416 
417         if (AMDGPU::SReg_32RegClass.contains(reg)) {
418           assert(!AMDGPU::TTMP_32RegClass.contains(reg) &&
419                  "trap handler registers should not be used");
420           isSGPR = true;
421           width = 1;
422         } else if (AMDGPU::VGPR_32RegClass.contains(reg)) {
423           isSGPR = false;
424           width = 1;
425         } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
426           assert(!AMDGPU::TTMP_64RegClass.contains(reg) &&
427                  "trap handler registers should not be used");
428           isSGPR = true;
429           width = 2;
430         } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
431           isSGPR = false;
432           width = 2;
433         } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
434           isSGPR = false;
435           width = 3;
436         } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
437           isSGPR = true;
438           width = 4;
439         } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
440           isSGPR = false;
441           width = 4;
442         } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
443           isSGPR = true;
444           width = 8;
445         } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
446           isSGPR = false;
447           width = 8;
448         } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
449           isSGPR = true;
450           width = 16;
451         } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
452           isSGPR = false;
453           width = 16;
454         } else {
455           llvm_unreachable("Unknown register class");
456         }
457         unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
458         unsigned maxUsed = hwReg + width - 1;
459         if (isSGPR) {
460           MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
461         } else {
462           MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
463         }
464       }
465     }
466   }
467 
468   unsigned ExtraSGPRs = 0;
469 
470   if (VCCUsed)
471     ExtraSGPRs = 2;
472 
473   if (STM.getGeneration() < SISubtarget::VOLCANIC_ISLANDS) {
474     if (FlatUsed)
475       ExtraSGPRs = 4;
476   } else {
477     if (STM.isXNACKEnabled())
478       ExtraSGPRs = 4;
479 
480     if (FlatUsed)
481       ExtraSGPRs = 6;
482   }
483 
484   unsigned ExtraVGPRs = STM.getReservedNumVGPRs(MF);
485 
486   // Check the addressable register limit before we add ExtraSGPRs.
487   if (STM.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
488       !STM.hasSGPRInitBug()) {
489     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
490     if (MaxSGPR + 1 > MaxAddressableNumSGPRs) {
491       // This can happen due to a compiler bug or when using inline asm.
492       LLVMContext &Ctx = MF.getFunction()->getContext();
493       DiagnosticInfoResourceLimit Diag(*MF.getFunction(),
494                                        "addressable scalar registers",
495                                        MaxSGPR + 1, DS_Error,
496                                        DK_ResourceLimit,
497                                        MaxAddressableNumSGPRs);
498       Ctx.diagnose(Diag);
499       MaxSGPR = MaxAddressableNumSGPRs - 1;
500     }
501   }
502 
503   // Account for extra SGPRs and VGPRs reserved for debugger use.
504   MaxSGPR += ExtraSGPRs;
505   MaxVGPR += ExtraVGPRs;
506 
507   // We found the maximum register index. They start at 0, so add one to get the
508   // number of registers.
509   ProgInfo.NumSGPR = MaxSGPR + 1;
510   ProgInfo.NumVGPR = MaxVGPR + 1;
511 
512   // Adjust number of registers used to meet default/requested minimum/maximum
513   // number of waves per execution unit request.
514   ProgInfo.NumSGPRsForWavesPerEU = std::max(
515     ProgInfo.NumSGPR, STM.getMinNumSGPRs(MFI->getMaxWavesPerEU()));
516   ProgInfo.NumVGPRsForWavesPerEU = std::max(
517     ProgInfo.NumVGPR, STM.getMinNumVGPRs(MFI->getMaxWavesPerEU()));
518 
519   if (STM.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ||
520       STM.hasSGPRInitBug()) {
521     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
522     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
523       // This can happen due to a compiler bug or when using inline asm to use
524       // the registers which are usually reserved for vcc etc.
525       LLVMContext &Ctx = MF.getFunction()->getContext();
526       DiagnosticInfoResourceLimit Diag(*MF.getFunction(),
527                                        "scalar registers",
528                                        ProgInfo.NumSGPR, DS_Error,
529                                        DK_ResourceLimit,
530                                        MaxAddressableNumSGPRs);
531       Ctx.diagnose(Diag);
532       ProgInfo.NumSGPR = MaxAddressableNumSGPRs;
533       ProgInfo.NumSGPRsForWavesPerEU = MaxAddressableNumSGPRs;
534     }
535   }
536 
537   if (STM.hasSGPRInitBug()) {
538     ProgInfo.NumSGPR =
539         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
540     ProgInfo.NumSGPRsForWavesPerEU =
541         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
542   }
543 
544   if (MFI->NumUserSGPRs > STM.getMaxNumUserSGPRs()) {
545     LLVMContext &Ctx = MF.getFunction()->getContext();
546     DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "user SGPRs",
547                                      MFI->NumUserSGPRs, DS_Error);
548     Ctx.diagnose(Diag);
549   }
550 
551   if (MFI->getLDSSize() > static_cast<unsigned>(STM.getLocalMemorySize())) {
552     LLVMContext &Ctx = MF.getFunction()->getContext();
553     DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "local memory",
554                                      MFI->getLDSSize(), DS_Error);
555     Ctx.diagnose(Diag);
556   }
557 
558   // SGPRBlocks is actual number of SGPR blocks minus 1.
559   ProgInfo.SGPRBlocks = alignTo(ProgInfo.NumSGPRsForWavesPerEU,
560                                 STM.getSGPREncodingGranule());
561   ProgInfo.SGPRBlocks = ProgInfo.SGPRBlocks / STM.getSGPREncodingGranule() - 1;
562 
563   // VGPRBlocks is actual number of VGPR blocks minus 1.
564   ProgInfo.VGPRBlocks = alignTo(ProgInfo.NumVGPRsForWavesPerEU,
565                                 STM.getVGPREncodingGranule());
566   ProgInfo.VGPRBlocks = ProgInfo.VGPRBlocks / STM.getVGPREncodingGranule() - 1;
567 
568   // Record first reserved VGPR and number of reserved VGPRs.
569   ProgInfo.ReservedVGPRFirst = STM.debuggerReserveRegs() ? MaxVGPR + 1 : 0;
570   ProgInfo.ReservedVGPRCount = STM.getReservedNumVGPRs(MF);
571 
572   // Update DebuggerWavefrontPrivateSegmentOffsetSGPR and
573   // DebuggerPrivateSegmentBufferSGPR fields if "amdgpu-debugger-emit-prologue"
574   // attribute was requested.
575   if (STM.debuggerEmitPrologue()) {
576     ProgInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR =
577       RI->getHWRegIndex(MFI->getScratchWaveOffsetReg());
578     ProgInfo.DebuggerPrivateSegmentBufferSGPR =
579       RI->getHWRegIndex(MFI->getScratchRSrcReg());
580   }
581 
582   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
583   // register.
584   ProgInfo.FloatMode = getFPMode(MF);
585 
586   ProgInfo.IEEEMode = STM.enableIEEEBit(MF);
587 
588   // Make clamp modifier on NaN input returns 0.
589   ProgInfo.DX10Clamp = STM.enableDX10Clamp();
590 
591   const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
592   ProgInfo.ScratchSize = FrameInfo.getStackSize();
593 
594   ProgInfo.FlatUsed = FlatUsed;
595   ProgInfo.VCCUsed = VCCUsed;
596   ProgInfo.CodeLen = CodeSize;
597 
598   unsigned LDSAlignShift;
599   if (STM.getGeneration() < SISubtarget::SEA_ISLANDS) {
600     // LDS is allocated in 64 dword blocks.
601     LDSAlignShift = 8;
602   } else {
603     // LDS is allocated in 128 dword blocks.
604     LDSAlignShift = 9;
605   }
606 
607   unsigned LDSSpillSize =
608     MFI->LDSWaveSpillSize * MFI->getMaxFlatWorkGroupSize();
609 
610   ProgInfo.LDSSize = MFI->getLDSSize() + LDSSpillSize;
611   ProgInfo.LDSBlocks =
612       alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
613 
614   // Scratch is allocated in 256 dword blocks.
615   unsigned ScratchAlignShift = 10;
616   // We need to program the hardware with the amount of scratch memory that
617   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
618   // scratch memory used per thread.
619   ProgInfo.ScratchBlocks =
620       alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
621               1ULL << ScratchAlignShift) >>
622       ScratchAlignShift;
623 
624   ProgInfo.ComputePGMRSrc1 =
625       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
626       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
627       S_00B848_PRIORITY(ProgInfo.Priority) |
628       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
629       S_00B848_PRIV(ProgInfo.Priv) |
630       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
631       S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
632       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
633 
634   // 0 = X, 1 = XY, 2 = XYZ
635   unsigned TIDIGCompCnt = 0;
636   if (MFI->hasWorkItemIDZ())
637     TIDIGCompCnt = 2;
638   else if (MFI->hasWorkItemIDY())
639     TIDIGCompCnt = 1;
640 
641   ProgInfo.ComputePGMRSrc2 =
642       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
643       S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
644       S_00B84C_TRAP_HANDLER(STM.isTrapHandlerEnabled()) |
645       S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
646       S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
647       S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
648       S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
649       S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
650       S_00B84C_EXCP_EN_MSB(0) |
651       S_00B84C_LDS_SIZE(ProgInfo.LDSBlocks) |
652       S_00B84C_EXCP_EN(0);
653 }
654 
655 static unsigned getRsrcReg(CallingConv::ID CallConv) {
656   switch (CallConv) {
657   default: LLVM_FALLTHROUGH;
658   case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
659   case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
660   case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
661   case CallingConv::AMDGPU_VS: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
662   }
663 }
664 
665 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
666                                          const SIProgramInfo &KernelInfo) {
667   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
668   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
669   unsigned RsrcReg = getRsrcReg(MF.getFunction()->getCallingConv());
670 
671   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
672     OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
673 
674     OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc1, 4);
675 
676     OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
677     OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc2, 4);
678 
679     OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
680     OutStreamer->EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4);
681 
682     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
683     // 0" comment but I don't see a corresponding field in the register spec.
684   } else {
685     OutStreamer->EmitIntValue(RsrcReg, 4);
686     OutStreamer->EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
687                               S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4);
688     if (STM.isVGPRSpillingEnabled(*MF.getFunction())) {
689       OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
690       OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(KernelInfo.ScratchBlocks), 4);
691     }
692   }
693 
694   if (MF.getFunction()->getCallingConv() == CallingConv::AMDGPU_PS) {
695     OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
696     OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4);
697     OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
698     OutStreamer->EmitIntValue(MFI->PSInputEna, 4);
699     OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
700     OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4);
701   }
702 
703   OutStreamer->EmitIntValue(R_SPILLED_SGPRS, 4);
704   OutStreamer->EmitIntValue(MFI->getNumSpilledSGPRs(), 4);
705   OutStreamer->EmitIntValue(R_SPILLED_VGPRS, 4);
706   OutStreamer->EmitIntValue(MFI->getNumSpilledVGPRs(), 4);
707 }
708 
709 // This is supposed to be log2(Size)
710 static amd_element_byte_size_t getElementByteSizeValue(unsigned Size) {
711   switch (Size) {
712   case 4:
713     return AMD_ELEMENT_4_BYTES;
714   case 8:
715     return AMD_ELEMENT_8_BYTES;
716   case 16:
717     return AMD_ELEMENT_16_BYTES;
718   default:
719     llvm_unreachable("invalid private_element_size");
720   }
721 }
722 
723 void AMDGPUAsmPrinter::EmitAmdKernelCodeT(const MachineFunction &MF,
724                                          const SIProgramInfo &KernelInfo) const {
725   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
726   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
727   amd_kernel_code_t header;
728 
729   AMDGPU::initDefaultAMDKernelCodeT(header, STM.getFeatureBits());
730 
731   header.compute_pgm_resource_registers =
732       KernelInfo.ComputePGMRSrc1 |
733       (KernelInfo.ComputePGMRSrc2 << 32);
734   header.code_properties = AMD_CODE_PROPERTY_IS_PTR64;
735 
736 
737   AMD_HSA_BITS_SET(header.code_properties,
738                    AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE,
739                    getElementByteSizeValue(STM.getMaxPrivateElementSize()));
740 
741   if (MFI->hasPrivateSegmentBuffer()) {
742     header.code_properties |=
743       AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
744   }
745 
746   if (MFI->hasDispatchPtr())
747     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
748 
749   if (MFI->hasQueuePtr())
750     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
751 
752   if (MFI->hasKernargSegmentPtr())
753     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
754 
755   if (MFI->hasDispatchID())
756     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
757 
758   if (MFI->hasFlatScratchInit())
759     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
760 
761   // TODO: Private segment size
762 
763   if (MFI->hasGridWorkgroupCountX()) {
764     header.code_properties |=
765       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X;
766   }
767 
768   if (MFI->hasGridWorkgroupCountY()) {
769     header.code_properties |=
770       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y;
771   }
772 
773   if (MFI->hasGridWorkgroupCountZ()) {
774     header.code_properties |=
775       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z;
776   }
777 
778   if (MFI->hasDispatchPtr())
779     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
780 
781   if (STM.debuggerSupported())
782     header.code_properties |= AMD_CODE_PROPERTY_IS_DEBUG_SUPPORTED;
783 
784   if (STM.isXNACKEnabled())
785     header.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED;
786 
787   // FIXME: Should use getKernArgSize
788   header.kernarg_segment_byte_size =
789     STM.getKernArgSegmentSize(MF, MFI->getABIArgOffset());
790   header.wavefront_sgpr_count = KernelInfo.NumSGPR;
791   header.workitem_vgpr_count = KernelInfo.NumVGPR;
792   header.workitem_private_segment_byte_size = KernelInfo.ScratchSize;
793   header.workgroup_group_segment_byte_size = KernelInfo.LDSSize;
794   header.reserved_vgpr_first = KernelInfo.ReservedVGPRFirst;
795   header.reserved_vgpr_count = KernelInfo.ReservedVGPRCount;
796 
797   // These alignment values are specified in powers of two, so alignment =
798   // 2^n.  The minimum alignment is 2^4 = 16.
799   header.kernarg_segment_alignment = std::max((size_t)4,
800       countTrailingZeros(MFI->getMaxKernArgAlign()));
801 
802   if (STM.debuggerEmitPrologue()) {
803     header.debug_wavefront_private_segment_offset_sgpr =
804       KernelInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR;
805     header.debug_private_segment_buffer_sgpr =
806       KernelInfo.DebuggerPrivateSegmentBufferSGPR;
807   }
808 
809   AMDGPUTargetStreamer *TS =
810       static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
811 
812   OutStreamer->SwitchSection(getObjFileLowering().getTextSection());
813   TS->EmitAMDKernelCodeT(header);
814 }
815 
816 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
817                                        unsigned AsmVariant,
818                                        const char *ExtraCode, raw_ostream &O) {
819   if (ExtraCode && ExtraCode[0]) {
820     if (ExtraCode[1] != 0)
821       return true; // Unknown modifier.
822 
823     switch (ExtraCode[0]) {
824     default:
825       // See if this is a generic print operand
826       return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
827     case 'r':
828       break;
829     }
830   }
831 
832   AMDGPUInstPrinter::printRegOperand(MI->getOperand(OpNo).getReg(), O,
833                    *TM.getSubtargetImpl(*MF->getFunction())->getRegisterInfo());
834   return false;
835 }
836