1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
15 //
16 //===----------------------------------------------------------------------===//
17 //
18 
19 #include "AMDGPUAsmPrinter.h"
20 #include "AMDGPU.h"
21 #include "AMDGPUSubtarget.h"
22 #include "AMDGPUTargetMachine.h"
23 #include "InstPrinter/AMDGPUInstPrinter.h"
24 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
25 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
26 #include "R600Defines.h"
27 #include "R600MachineFunctionInfo.h"
28 #include "R600RegisterInfo.h"
29 #include "SIDefines.h"
30 #include "SIInstrInfo.h"
31 #include "SIMachineFunctionInfo.h"
32 #include "SIRegisterInfo.h"
33 #include "Utils/AMDGPUBaseInfo.h"
34 #include "llvm/BinaryFormat/ELF.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/IR/DiagnosticInfo.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCSectionELF.h"
39 #include "llvm/MC/MCStreamer.h"
40 #include "llvm/Support/AMDGPUMetadata.h"
41 #include "llvm/Support/MathExtras.h"
42 #include "llvm/Support/TargetRegistry.h"
43 #include "llvm/Target/TargetLoweringObjectFile.h"
44 
45 using namespace llvm;
46 using namespace llvm::AMDGPU;
47 
48 // TODO: This should get the default rounding mode from the kernel. We just set
49 // the default here, but this could change if the OpenCL rounding mode pragmas
50 // are used.
51 //
52 // The denormal mode here should match what is reported by the OpenCL runtime
53 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
54 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
55 //
56 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
57 // precision, and leaves single precision to flush all and does not report
58 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
59 // CL_FP_DENORM for both.
60 //
61 // FIXME: It seems some instructions do not support single precision denormals
62 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
63 // and sin_f32, cos_f32 on most parts).
64 
65 // We want to use these instructions, and using fp32 denormals also causes
66 // instructions to run at the double precision rate for the device so it's
67 // probably best to just report no single precision denormals.
68 static uint32_t getFPMode(const MachineFunction &F) {
69   const SISubtarget& ST = F.getSubtarget<SISubtarget>();
70   // TODO: Is there any real use for the flush in only / flush out only modes?
71 
72   uint32_t FP32Denormals =
73     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
74 
75   uint32_t FP64Denormals =
76     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
77 
78   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
79          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
80          FP_DENORM_MODE_SP(FP32Denormals) |
81          FP_DENORM_MODE_DP(FP64Denormals);
82 }
83 
84 static AsmPrinter *
85 createAMDGPUAsmPrinterPass(TargetMachine &tm,
86                            std::unique_ptr<MCStreamer> &&Streamer) {
87   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
88 }
89 
90 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
91   TargetRegistry::RegisterAsmPrinter(getTheAMDGPUTarget(),
92                                      createAMDGPUAsmPrinterPass);
93   TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(),
94                                      createAMDGPUAsmPrinterPass);
95 }
96 
97 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
98                                    std::unique_ptr<MCStreamer> Streamer)
99   : AsmPrinter(TM, std::move(Streamer)) {
100     AMDGPUASI = static_cast<AMDGPUTargetMachine*>(&TM)->getAMDGPUAS();
101   }
102 
103 StringRef AMDGPUAsmPrinter::getPassName() const {
104   return "AMDGPU Assembly Printer";
105 }
106 
107 const MCSubtargetInfo* AMDGPUAsmPrinter::getSTI() const {
108   return TM.getMCSubtargetInfo();
109 }
110 
111 AMDGPUTargetStreamer* AMDGPUAsmPrinter::getTargetStreamer() const {
112   if (!OutStreamer)
113     return nullptr;
114   return static_cast<AMDGPUTargetStreamer*>(OutStreamer->getTargetStreamer());
115 }
116 
117 void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) {
118   if (TM.getTargetTriple().getArch() != Triple::amdgcn)
119     return;
120 
121   if (TM.getTargetTriple().getOS() != Triple::AMDHSA &&
122       TM.getTargetTriple().getOS() != Triple::AMDPAL)
123     return;
124 
125   if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
126     HSAMetadataStream.begin(M);
127 
128   if (TM.getTargetTriple().getOS() == Triple::AMDPAL)
129     readPALMetadata(M);
130 
131   // Deprecated notes are not emitted for code object v3.
132   if (IsaInfo::hasCodeObjectV3(getSTI()->getFeatureBits()))
133     return;
134 
135   // HSA emits NT_AMDGPU_HSA_CODE_OBJECT_VERSION for code objects v2.
136   if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
137     getTargetStreamer()->EmitDirectiveHSACodeObjectVersion(2, 1);
138 
139   // HSA and PAL emit NT_AMDGPU_HSA_ISA for code objects v2.
140   IsaInfo::IsaVersion ISA = IsaInfo::getIsaVersion(getSTI()->getFeatureBits());
141   getTargetStreamer()->EmitDirectiveHSACodeObjectISA(
142       ISA.Major, ISA.Minor, ISA.Stepping, "AMD", "AMDGPU");
143 }
144 
145 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
146   if (TM.getTargetTriple().getArch() != Triple::amdgcn)
147     return;
148 
149   // Following code requires TargetStreamer to be present.
150   if (!getTargetStreamer())
151     return;
152 
153   // Emit ISA Version (NT_AMD_AMDGPU_ISA).
154   std::string ISAVersionString;
155   raw_string_ostream ISAVersionStream(ISAVersionString);
156   IsaInfo::streamIsaVersion(getSTI(), ISAVersionStream);
157   getTargetStreamer()->EmitISAVersion(ISAVersionStream.str());
158 
159   // Emit HSA Metadata (NT_AMD_AMDGPU_HSA_METADATA).
160   if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
161     HSAMetadataStream.end();
162     getTargetStreamer()->EmitHSAMetadata(HSAMetadataStream.getHSAMetadata());
163   }
164 
165   // Emit PAL Metadata (NT_AMD_AMDGPU_PAL_METADATA).
166   if (TM.getTargetTriple().getOS() == Triple::AMDPAL) {
167     // Copy the PAL metadata from the map where we collected it into a vector,
168     // then write it as a .note.
169     PALMD::Metadata PALMetadataVector;
170     for (auto i : PALMetadataMap) {
171       PALMetadataVector.push_back(i.first);
172       PALMetadataVector.push_back(i.second);
173     }
174     getTargetStreamer()->EmitPALMetadata(PALMetadataVector);
175   }
176 }
177 
178 bool AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough(
179   const MachineBasicBlock *MBB) const {
180   if (!AsmPrinter::isBlockOnlyReachableByFallthrough(MBB))
181     return false;
182 
183   if (MBB->empty())
184     return true;
185 
186   // If this is a block implementing a long branch, an expression relative to
187   // the start of the block is needed.  to the start of the block.
188   // XXX - Is there a smarter way to check this?
189   return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
190 }
191 
192 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
193   const AMDGPUMachineFunction *MFI = MF->getInfo<AMDGPUMachineFunction>();
194   if (!MFI->isEntryFunction())
195     return;
196 
197   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
198   amd_kernel_code_t KernelCode;
199   if (STM.isAmdCodeObjectV2(*MF)) {
200     getAmdKernelCode(KernelCode, CurrentProgramInfo, *MF);
201     getTargetStreamer()->EmitAMDKernelCodeT(KernelCode);
202   }
203 
204   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
205     return;
206 
207   HSAMetadataStream.emitKernel(MF->getFunction(),
208                                getHSACodeProps(*MF, CurrentProgramInfo),
209                                getHSADebugProps(*MF, CurrentProgramInfo));
210 }
211 
212 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
213   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
214   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
215   if (MFI->isEntryFunction() && STM.isAmdCodeObjectV2(*MF)) {
216     SmallString<128> SymbolName;
217     getNameWithPrefix(SymbolName, &MF->getFunction()),
218     getTargetStreamer()->EmitAMDGPUSymbolType(
219         SymbolName, ELF::STT_AMDGPU_HSA_KERNEL);
220   }
221   const AMDGPUSubtarget &STI = MF->getSubtarget<AMDGPUSubtarget>();
222   if (STI.dumpCode()) {
223     // Disassemble function name label to text.
224     DisasmLines.push_back(MF->getName().str() + ":");
225     DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size());
226     HexLines.push_back("");
227   }
228 
229   AsmPrinter::EmitFunctionEntryLabel();
230 }
231 
232 void AMDGPUAsmPrinter::EmitBasicBlockStart(const MachineBasicBlock &MBB) const {
233   const AMDGPUSubtarget &STI = MBB.getParent()->getSubtarget<AMDGPUSubtarget>();
234   if (STI.dumpCode() && !isBlockOnlyReachableByFallthrough(&MBB)) {
235     // Write a line for the basic block label if it is not only fallthrough.
236     DisasmLines.push_back(
237         (Twine("BB") + Twine(getFunctionNumber())
238          + "_" + Twine(MBB.getNumber()) + ":").str());
239     DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size());
240     HexLines.push_back("");
241   }
242   AsmPrinter::EmitBasicBlockStart(MBB);
243 }
244 
245 void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
246 
247   // Group segment variables aren't emitted in HSA.
248   if (AMDGPU::isGroupSegment(GV))
249     return;
250 
251   AsmPrinter::EmitGlobalVariable(GV);
252 }
253 
254 bool AMDGPUAsmPrinter::doFinalization(Module &M) {
255   CallGraphResourceInfo.clear();
256   return AsmPrinter::doFinalization(M);
257 }
258 
259 // For the amdpal OS type, read the amdgpu.pal.metadata supplied by the
260 // frontend into our PALMetadataMap, ready for per-function modification.  It
261 // is a NamedMD containing an MDTuple containing a number of MDNodes each of
262 // which is an integer value, and each two integer values forms a key=value
263 // pair that we store as PALMetadataMap[key]=value in the map.
264 void AMDGPUAsmPrinter::readPALMetadata(Module &M) {
265   auto NamedMD = M.getNamedMetadata("amdgpu.pal.metadata");
266   if (!NamedMD || !NamedMD->getNumOperands())
267     return;
268   auto Tuple = dyn_cast<MDTuple>(NamedMD->getOperand(0));
269   if (!Tuple)
270     return;
271   for (unsigned I = 0, E = Tuple->getNumOperands() & -2; I != E; I += 2) {
272     auto Key = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I));
273     auto Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I + 1));
274     if (!Key || !Val)
275       continue;
276     PALMetadataMap[Key->getZExtValue()] = Val->getZExtValue();
277   }
278 }
279 
280 // Print comments that apply to both callable functions and entry points.
281 void AMDGPUAsmPrinter::emitCommonFunctionComments(
282   uint32_t NumVGPR,
283   uint32_t NumSGPR,
284   uint64_t ScratchSize,
285   uint64_t CodeSize) {
286   OutStreamer->emitRawComment(" codeLenInByte = " + Twine(CodeSize), false);
287   OutStreamer->emitRawComment(" NumSgprs: " + Twine(NumSGPR), false);
288   OutStreamer->emitRawComment(" NumVgprs: " + Twine(NumVGPR), false);
289   OutStreamer->emitRawComment(" ScratchSize: " + Twine(ScratchSize), false);
290 }
291 
292 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
293   CurrentProgramInfo = SIProgramInfo();
294 
295   const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
296 
297   // The starting address of all shader programs must be 256 bytes aligned.
298   // Regular functions just need the basic required instruction alignment.
299   MF.setAlignment(MFI->isEntryFunction() ? 8 : 2);
300 
301   SetupMachineFunction(MF);
302 
303   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
304   MCContext &Context = getObjFileLowering().getContext();
305   // FIXME: This should be an explicit check for Mesa.
306   if (!STM.isAmdHsaOS() && !STM.isAmdPalOS()) {
307     MCSectionELF *ConfigSection =
308         Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
309     OutStreamer->SwitchSection(ConfigSection);
310   }
311 
312   if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
313     if (MFI->isEntryFunction()) {
314       getSIProgramInfo(CurrentProgramInfo, MF);
315     } else {
316       auto I = CallGraphResourceInfo.insert(
317         std::make_pair(&MF.getFunction(), SIFunctionResourceInfo()));
318       SIFunctionResourceInfo &Info = I.first->second;
319       assert(I.second && "should only be called once per function");
320       Info = analyzeResourceUsage(MF);
321     }
322 
323     if (STM.isAmdPalOS())
324       EmitPALMetadata(MF, CurrentProgramInfo);
325     else if (!STM.isAmdHsaOS()) {
326       EmitProgramInfoSI(MF, CurrentProgramInfo);
327     }
328   } else {
329     EmitProgramInfoR600(MF);
330   }
331 
332   DisasmLines.clear();
333   HexLines.clear();
334   DisasmLineMaxLen = 0;
335 
336   EmitFunctionBody();
337 
338   if (isVerbose()) {
339     MCSectionELF *CommentSection =
340         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
341     OutStreamer->SwitchSection(CommentSection);
342 
343     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
344       if (!MFI->isEntryFunction()) {
345         OutStreamer->emitRawComment(" Function info:", false);
346         SIFunctionResourceInfo &Info = CallGraphResourceInfo[&MF.getFunction()];
347         emitCommonFunctionComments(
348           Info.NumVGPR,
349           Info.getTotalNumSGPRs(MF.getSubtarget<SISubtarget>()),
350           Info.PrivateSegmentSize,
351           getFunctionCodeSize(MF));
352         return false;
353       }
354 
355       OutStreamer->emitRawComment(" Kernel info:", false);
356       emitCommonFunctionComments(CurrentProgramInfo.NumVGPR,
357                                  CurrentProgramInfo.NumSGPR,
358                                  CurrentProgramInfo.ScratchSize,
359                                  getFunctionCodeSize(MF));
360 
361       OutStreamer->emitRawComment(
362         " FloatMode: " + Twine(CurrentProgramInfo.FloatMode), false);
363       OutStreamer->emitRawComment(
364         " IeeeMode: " + Twine(CurrentProgramInfo.IEEEMode), false);
365       OutStreamer->emitRawComment(
366         " LDSByteSize: " + Twine(CurrentProgramInfo.LDSSize) +
367         " bytes/workgroup (compile time only)", false);
368 
369       OutStreamer->emitRawComment(
370         " SGPRBlocks: " + Twine(CurrentProgramInfo.SGPRBlocks), false);
371       OutStreamer->emitRawComment(
372         " VGPRBlocks: " + Twine(CurrentProgramInfo.VGPRBlocks), false);
373 
374       OutStreamer->emitRawComment(
375         " NumSGPRsForWavesPerEU: " +
376         Twine(CurrentProgramInfo.NumSGPRsForWavesPerEU), false);
377       OutStreamer->emitRawComment(
378         " NumVGPRsForWavesPerEU: " +
379         Twine(CurrentProgramInfo.NumVGPRsForWavesPerEU), false);
380 
381       OutStreamer->emitRawComment(
382         " ReservedVGPRFirst: " + Twine(CurrentProgramInfo.ReservedVGPRFirst),
383         false);
384       OutStreamer->emitRawComment(
385         " ReservedVGPRCount: " + Twine(CurrentProgramInfo.ReservedVGPRCount),
386         false);
387 
388       if (MF.getSubtarget<SISubtarget>().debuggerEmitPrologue()) {
389         OutStreamer->emitRawComment(
390           " DebuggerWavefrontPrivateSegmentOffsetSGPR: s" +
391           Twine(CurrentProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR), false);
392         OutStreamer->emitRawComment(
393           " DebuggerPrivateSegmentBufferSGPR: s" +
394           Twine(CurrentProgramInfo.DebuggerPrivateSegmentBufferSGPR), false);
395       }
396 
397       OutStreamer->emitRawComment(
398         " COMPUTE_PGM_RSRC2:USER_SGPR: " +
399         Twine(G_00B84C_USER_SGPR(CurrentProgramInfo.ComputePGMRSrc2)), false);
400       OutStreamer->emitRawComment(
401         " COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
402         Twine(G_00B84C_TRAP_HANDLER(CurrentProgramInfo.ComputePGMRSrc2)), false);
403       OutStreamer->emitRawComment(
404         " COMPUTE_PGM_RSRC2:TGID_X_EN: " +
405         Twine(G_00B84C_TGID_X_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
406       OutStreamer->emitRawComment(
407         " COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
408         Twine(G_00B84C_TGID_Y_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
409       OutStreamer->emitRawComment(
410         " COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
411         Twine(G_00B84C_TGID_Z_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
412       OutStreamer->emitRawComment(
413         " COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
414         Twine(G_00B84C_TIDIG_COMP_CNT(CurrentProgramInfo.ComputePGMRSrc2)),
415         false);
416     } else {
417       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
418       OutStreamer->emitRawComment(
419         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->CFStackSize)));
420     }
421   }
422 
423   if (STM.dumpCode()) {
424 
425     OutStreamer->SwitchSection(
426         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
427 
428     for (size_t i = 0; i < DisasmLines.size(); ++i) {
429       std::string Comment = "\n";
430       if (!HexLines[i].empty()) {
431         Comment = std::string(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
432         Comment += " ; " + HexLines[i] + "\n";
433       }
434 
435       OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
436       OutStreamer->EmitBytes(StringRef(Comment));
437     }
438   }
439 
440   return false;
441 }
442 
443 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
444   unsigned MaxGPR = 0;
445   bool killPixel = false;
446   const R600Subtarget &STM = MF.getSubtarget<R600Subtarget>();
447   const R600RegisterInfo *RI = STM.getRegisterInfo();
448   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
449 
450   for (const MachineBasicBlock &MBB : MF) {
451     for (const MachineInstr &MI : MBB) {
452       if (MI.getOpcode() == AMDGPU::KILLGT)
453         killPixel = true;
454       unsigned numOperands = MI.getNumOperands();
455       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
456         const MachineOperand &MO = MI.getOperand(op_idx);
457         if (!MO.isReg())
458           continue;
459         unsigned HWReg = RI->getHWRegIndex(MO.getReg());
460 
461         // Register with value > 127 aren't GPR
462         if (HWReg > 127)
463           continue;
464         MaxGPR = std::max(MaxGPR, HWReg);
465       }
466     }
467   }
468 
469   unsigned RsrcReg;
470   if (STM.getGeneration() >= R600Subtarget::EVERGREEN) {
471     // Evergreen / Northern Islands
472     switch (MF.getFunction().getCallingConv()) {
473     default: LLVM_FALLTHROUGH;
474     case CallingConv::AMDGPU_CS: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
475     case CallingConv::AMDGPU_GS: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
476     case CallingConv::AMDGPU_PS: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
477     case CallingConv::AMDGPU_VS: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
478     }
479   } else {
480     // R600 / R700
481     switch (MF.getFunction().getCallingConv()) {
482     default: LLVM_FALLTHROUGH;
483     case CallingConv::AMDGPU_GS: LLVM_FALLTHROUGH;
484     case CallingConv::AMDGPU_CS: LLVM_FALLTHROUGH;
485     case CallingConv::AMDGPU_VS: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
486     case CallingConv::AMDGPU_PS: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
487     }
488   }
489 
490   OutStreamer->EmitIntValue(RsrcReg, 4);
491   OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
492                            S_STACK_SIZE(MFI->CFStackSize), 4);
493   OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
494   OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
495 
496   if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
497     OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
498     OutStreamer->EmitIntValue(alignTo(MFI->getLDSSize(), 4) >> 2, 4);
499   }
500 }
501 
502 uint64_t AMDGPUAsmPrinter::getFunctionCodeSize(const MachineFunction &MF) const {
503   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
504   const SIInstrInfo *TII = STM.getInstrInfo();
505 
506   uint64_t CodeSize = 0;
507 
508   for (const MachineBasicBlock &MBB : MF) {
509     for (const MachineInstr &MI : MBB) {
510       // TODO: CodeSize should account for multiple functions.
511 
512       // TODO: Should we count size of debug info?
513       if (MI.isDebugInstr())
514         continue;
515 
516       CodeSize += TII->getInstSizeInBytes(MI);
517     }
518   }
519 
520   return CodeSize;
521 }
522 
523 static bool hasAnyNonFlatUseOfReg(const MachineRegisterInfo &MRI,
524                                   const SIInstrInfo &TII,
525                                   unsigned Reg) {
526   for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) {
527     if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent()))
528       return true;
529   }
530 
531   return false;
532 }
533 
534 static unsigned getNumExtraSGPRs(const SISubtarget &ST,
535                                  bool VCCUsed,
536                                  bool FlatScrUsed) {
537   unsigned ExtraSGPRs = 0;
538   if (VCCUsed)
539     ExtraSGPRs = 2;
540 
541   if (ST.getGeneration() < SISubtarget::VOLCANIC_ISLANDS) {
542     if (FlatScrUsed)
543       ExtraSGPRs = 4;
544   } else {
545     if (ST.isXNACKEnabled())
546       ExtraSGPRs = 4;
547 
548     if (FlatScrUsed)
549       ExtraSGPRs = 6;
550   }
551 
552   return ExtraSGPRs;
553 }
554 
555 int32_t AMDGPUAsmPrinter::SIFunctionResourceInfo::getTotalNumSGPRs(
556   const SISubtarget &ST) const {
557   return NumExplicitSGPR + getNumExtraSGPRs(ST, UsesVCC, UsesFlatScratch);
558 }
559 
560 AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
561   const MachineFunction &MF) const {
562   SIFunctionResourceInfo Info;
563 
564   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
565   const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
566   const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
567   const MachineRegisterInfo &MRI = MF.getRegInfo();
568   const SIInstrInfo *TII = ST.getInstrInfo();
569   const SIRegisterInfo &TRI = TII->getRegisterInfo();
570 
571   Info.UsesFlatScratch = MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_LO) ||
572                          MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_HI);
573 
574   // Even if FLAT_SCRATCH is implicitly used, it has no effect if flat
575   // instructions aren't used to access the scratch buffer. Inline assembly may
576   // need it though.
577   //
578   // If we only have implicit uses of flat_scr on flat instructions, it is not
579   // really needed.
580   if (Info.UsesFlatScratch && !MFI->hasFlatScratchInit() &&
581       (!hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR) &&
582        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_LO) &&
583        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_HI))) {
584     Info.UsesFlatScratch = false;
585   }
586 
587   Info.HasDynamicallySizedStack = FrameInfo.hasVarSizedObjects();
588   Info.PrivateSegmentSize = FrameInfo.getStackSize();
589   if (MFI->isStackRealigned())
590     Info.PrivateSegmentSize += FrameInfo.getMaxAlignment();
591 
592 
593   Info.UsesVCC = MRI.isPhysRegUsed(AMDGPU::VCC_LO) ||
594                  MRI.isPhysRegUsed(AMDGPU::VCC_HI);
595 
596   // If there are no calls, MachineRegisterInfo can tell us the used register
597   // count easily.
598   // A tail call isn't considered a call for MachineFrameInfo's purposes.
599   if (!FrameInfo.hasCalls() && !FrameInfo.hasTailCall()) {
600     MCPhysReg HighestVGPRReg = AMDGPU::NoRegister;
601     for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) {
602       if (MRI.isPhysRegUsed(Reg)) {
603         HighestVGPRReg = Reg;
604         break;
605       }
606     }
607 
608     MCPhysReg HighestSGPRReg = AMDGPU::NoRegister;
609     for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) {
610       if (MRI.isPhysRegUsed(Reg)) {
611         HighestSGPRReg = Reg;
612         break;
613       }
614     }
615 
616     // We found the maximum register index. They start at 0, so add one to get the
617     // number of registers.
618     Info.NumVGPR = HighestVGPRReg == AMDGPU::NoRegister ? 0 :
619       TRI.getHWRegIndex(HighestVGPRReg) + 1;
620     Info.NumExplicitSGPR = HighestSGPRReg == AMDGPU::NoRegister ? 0 :
621       TRI.getHWRegIndex(HighestSGPRReg) + 1;
622 
623     return Info;
624   }
625 
626   int32_t MaxVGPR = -1;
627   int32_t MaxSGPR = -1;
628   uint64_t CalleeFrameSize = 0;
629 
630   for (const MachineBasicBlock &MBB : MF) {
631     for (const MachineInstr &MI : MBB) {
632       // TODO: Check regmasks? Do they occur anywhere except calls?
633       for (const MachineOperand &MO : MI.operands()) {
634         unsigned Width = 0;
635         bool IsSGPR = false;
636 
637         if (!MO.isReg())
638           continue;
639 
640         unsigned Reg = MO.getReg();
641         switch (Reg) {
642         case AMDGPU::EXEC:
643         case AMDGPU::EXEC_LO:
644         case AMDGPU::EXEC_HI:
645         case AMDGPU::SCC:
646         case AMDGPU::M0:
647         case AMDGPU::SRC_SHARED_BASE:
648         case AMDGPU::SRC_SHARED_LIMIT:
649         case AMDGPU::SRC_PRIVATE_BASE:
650         case AMDGPU::SRC_PRIVATE_LIMIT:
651           continue;
652 
653         case AMDGPU::NoRegister:
654           assert(MI.isDebugInstr());
655           continue;
656 
657         case AMDGPU::VCC:
658         case AMDGPU::VCC_LO:
659         case AMDGPU::VCC_HI:
660           Info.UsesVCC = true;
661           continue;
662 
663         case AMDGPU::FLAT_SCR:
664         case AMDGPU::FLAT_SCR_LO:
665         case AMDGPU::FLAT_SCR_HI:
666           continue;
667 
668         case AMDGPU::XNACK_MASK:
669         case AMDGPU::XNACK_MASK_LO:
670         case AMDGPU::XNACK_MASK_HI:
671           llvm_unreachable("xnack_mask registers should not be used");
672 
673         case AMDGPU::TBA:
674         case AMDGPU::TBA_LO:
675         case AMDGPU::TBA_HI:
676         case AMDGPU::TMA:
677         case AMDGPU::TMA_LO:
678         case AMDGPU::TMA_HI:
679           llvm_unreachable("trap handler registers should not be used");
680 
681         default:
682           break;
683         }
684 
685         if (AMDGPU::SReg_32RegClass.contains(Reg)) {
686           assert(!AMDGPU::TTMP_32RegClass.contains(Reg) &&
687                  "trap handler registers should not be used");
688           IsSGPR = true;
689           Width = 1;
690         } else if (AMDGPU::VGPR_32RegClass.contains(Reg)) {
691           IsSGPR = false;
692           Width = 1;
693         } else if (AMDGPU::SReg_64RegClass.contains(Reg)) {
694           assert(!AMDGPU::TTMP_64RegClass.contains(Reg) &&
695                  "trap handler registers should not be used");
696           IsSGPR = true;
697           Width = 2;
698         } else if (AMDGPU::VReg_64RegClass.contains(Reg)) {
699           IsSGPR = false;
700           Width = 2;
701         } else if (AMDGPU::VReg_96RegClass.contains(Reg)) {
702           IsSGPR = false;
703           Width = 3;
704         } else if (AMDGPU::SReg_128RegClass.contains(Reg)) {
705           assert(!AMDGPU::TTMP_128RegClass.contains(Reg) &&
706             "trap handler registers should not be used");
707           IsSGPR = true;
708           Width = 4;
709         } else if (AMDGPU::VReg_128RegClass.contains(Reg)) {
710           IsSGPR = false;
711           Width = 4;
712         } else if (AMDGPU::SReg_256RegClass.contains(Reg)) {
713           assert(!AMDGPU::TTMP_256RegClass.contains(Reg) &&
714             "trap handler registers should not be used");
715           IsSGPR = true;
716           Width = 8;
717         } else if (AMDGPU::VReg_256RegClass.contains(Reg)) {
718           IsSGPR = false;
719           Width = 8;
720         } else if (AMDGPU::SReg_512RegClass.contains(Reg)) {
721           assert(!AMDGPU::TTMP_512RegClass.contains(Reg) &&
722             "trap handler registers should not be used");
723           IsSGPR = true;
724           Width = 16;
725         } else if (AMDGPU::VReg_512RegClass.contains(Reg)) {
726           IsSGPR = false;
727           Width = 16;
728         } else {
729           llvm_unreachable("Unknown register class");
730         }
731         unsigned HWReg = TRI.getHWRegIndex(Reg);
732         int MaxUsed = HWReg + Width - 1;
733         if (IsSGPR) {
734           MaxSGPR = MaxUsed > MaxSGPR ? MaxUsed : MaxSGPR;
735         } else {
736           MaxVGPR = MaxUsed > MaxVGPR ? MaxUsed : MaxVGPR;
737         }
738       }
739 
740       if (MI.isCall()) {
741         // Pseudo used just to encode the underlying global. Is there a better
742         // way to track this?
743 
744         const MachineOperand *CalleeOp
745           = TII->getNamedOperand(MI, AMDGPU::OpName::callee);
746         const Function *Callee = cast<Function>(CalleeOp->getGlobal());
747         if (Callee->isDeclaration()) {
748           // If this is a call to an external function, we can't do much. Make
749           // conservative guesses.
750 
751           // 48 SGPRs - vcc, - flat_scr, -xnack
752           int MaxSGPRGuess = 47 - getNumExtraSGPRs(ST, true,
753                                                    ST.hasFlatAddressSpace());
754           MaxSGPR = std::max(MaxSGPR, MaxSGPRGuess);
755           MaxVGPR = std::max(MaxVGPR, 23);
756 
757           CalleeFrameSize = std::max(CalleeFrameSize, UINT64_C(16384));
758           Info.UsesVCC = true;
759           Info.UsesFlatScratch = ST.hasFlatAddressSpace();
760           Info.HasDynamicallySizedStack = true;
761         } else {
762           // We force CodeGen to run in SCC order, so the callee's register
763           // usage etc. should be the cumulative usage of all callees.
764           auto I = CallGraphResourceInfo.find(Callee);
765           assert(I != CallGraphResourceInfo.end() &&
766                  "callee should have been handled before caller");
767 
768           MaxSGPR = std::max(I->second.NumExplicitSGPR - 1, MaxSGPR);
769           MaxVGPR = std::max(I->second.NumVGPR - 1, MaxVGPR);
770           CalleeFrameSize
771             = std::max(I->second.PrivateSegmentSize, CalleeFrameSize);
772           Info.UsesVCC |= I->second.UsesVCC;
773           Info.UsesFlatScratch |= I->second.UsesFlatScratch;
774           Info.HasDynamicallySizedStack |= I->second.HasDynamicallySizedStack;
775           Info.HasRecursion |= I->second.HasRecursion;
776         }
777 
778         if (!Callee->doesNotRecurse())
779           Info.HasRecursion = true;
780       }
781     }
782   }
783 
784   Info.NumExplicitSGPR = MaxSGPR + 1;
785   Info.NumVGPR = MaxVGPR + 1;
786   Info.PrivateSegmentSize += CalleeFrameSize;
787 
788   return Info;
789 }
790 
791 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
792                                         const MachineFunction &MF) {
793   SIFunctionResourceInfo Info = analyzeResourceUsage(MF);
794 
795   ProgInfo.NumVGPR = Info.NumVGPR;
796   ProgInfo.NumSGPR = Info.NumExplicitSGPR;
797   ProgInfo.ScratchSize = Info.PrivateSegmentSize;
798   ProgInfo.VCCUsed = Info.UsesVCC;
799   ProgInfo.FlatUsed = Info.UsesFlatScratch;
800   ProgInfo.DynamicCallStack = Info.HasDynamicallySizedStack || Info.HasRecursion;
801 
802   if (!isUInt<32>(ProgInfo.ScratchSize)) {
803     DiagnosticInfoStackSize DiagStackSize(MF.getFunction(),
804                                           ProgInfo.ScratchSize, DS_Error);
805     MF.getFunction().getContext().diagnose(DiagStackSize);
806   }
807 
808   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
809   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
810   const SIInstrInfo *TII = STM.getInstrInfo();
811   const SIRegisterInfo *RI = &TII->getRegisterInfo();
812 
813   unsigned ExtraSGPRs = getNumExtraSGPRs(STM,
814                                          ProgInfo.VCCUsed,
815                                          ProgInfo.FlatUsed);
816   unsigned ExtraVGPRs = STM.getReservedNumVGPRs(MF);
817 
818   // Check the addressable register limit before we add ExtraSGPRs.
819   if (STM.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
820       !STM.hasSGPRInitBug()) {
821     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
822     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
823       // This can happen due to a compiler bug or when using inline asm.
824       LLVMContext &Ctx = MF.getFunction().getContext();
825       DiagnosticInfoResourceLimit Diag(MF.getFunction(),
826                                        "addressable scalar registers",
827                                        ProgInfo.NumSGPR, DS_Error,
828                                        DK_ResourceLimit,
829                                        MaxAddressableNumSGPRs);
830       Ctx.diagnose(Diag);
831       ProgInfo.NumSGPR = MaxAddressableNumSGPRs - 1;
832     }
833   }
834 
835   // Account for extra SGPRs and VGPRs reserved for debugger use.
836   ProgInfo.NumSGPR += ExtraSGPRs;
837   ProgInfo.NumVGPR += ExtraVGPRs;
838 
839   // Ensure there are enough SGPRs and VGPRs for wave dispatch, where wave
840   // dispatch registers are function args.
841   unsigned WaveDispatchNumSGPR = 0, WaveDispatchNumVGPR = 0;
842   for (auto &Arg : MF.getFunction().args()) {
843     unsigned NumRegs = (Arg.getType()->getPrimitiveSizeInBits() + 31) / 32;
844     if (Arg.hasAttribute(Attribute::InReg))
845       WaveDispatchNumSGPR += NumRegs;
846     else
847       WaveDispatchNumVGPR += NumRegs;
848   }
849   ProgInfo.NumSGPR = std::max(ProgInfo.NumSGPR, WaveDispatchNumSGPR);
850   ProgInfo.NumVGPR = std::max(ProgInfo.NumVGPR, WaveDispatchNumVGPR);
851 
852   // Adjust number of registers used to meet default/requested minimum/maximum
853   // number of waves per execution unit request.
854   ProgInfo.NumSGPRsForWavesPerEU = std::max(
855     std::max(ProgInfo.NumSGPR, 1u), STM.getMinNumSGPRs(MFI->getMaxWavesPerEU()));
856   ProgInfo.NumVGPRsForWavesPerEU = std::max(
857     std::max(ProgInfo.NumVGPR, 1u), STM.getMinNumVGPRs(MFI->getMaxWavesPerEU()));
858 
859   if (STM.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ||
860       STM.hasSGPRInitBug()) {
861     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
862     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
863       // This can happen due to a compiler bug or when using inline asm to use
864       // the registers which are usually reserved for vcc etc.
865       LLVMContext &Ctx = MF.getFunction().getContext();
866       DiagnosticInfoResourceLimit Diag(MF.getFunction(),
867                                        "scalar registers",
868                                        ProgInfo.NumSGPR, DS_Error,
869                                        DK_ResourceLimit,
870                                        MaxAddressableNumSGPRs);
871       Ctx.diagnose(Diag);
872       ProgInfo.NumSGPR = MaxAddressableNumSGPRs;
873       ProgInfo.NumSGPRsForWavesPerEU = MaxAddressableNumSGPRs;
874     }
875   }
876 
877   if (STM.hasSGPRInitBug()) {
878     ProgInfo.NumSGPR =
879         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
880     ProgInfo.NumSGPRsForWavesPerEU =
881         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
882   }
883 
884   if (MFI->getNumUserSGPRs() > STM.getMaxNumUserSGPRs()) {
885     LLVMContext &Ctx = MF.getFunction().getContext();
886     DiagnosticInfoResourceLimit Diag(MF.getFunction(), "user SGPRs",
887                                      MFI->getNumUserSGPRs(), DS_Error);
888     Ctx.diagnose(Diag);
889   }
890 
891   if (MFI->getLDSSize() > static_cast<unsigned>(STM.getLocalMemorySize())) {
892     LLVMContext &Ctx = MF.getFunction().getContext();
893     DiagnosticInfoResourceLimit Diag(MF.getFunction(), "local memory",
894                                      MFI->getLDSSize(), DS_Error);
895     Ctx.diagnose(Diag);
896   }
897 
898   // SGPRBlocks is actual number of SGPR blocks minus 1.
899   ProgInfo.SGPRBlocks = alignTo(ProgInfo.NumSGPRsForWavesPerEU,
900                                 STM.getSGPREncodingGranule());
901   ProgInfo.SGPRBlocks = ProgInfo.SGPRBlocks / STM.getSGPREncodingGranule() - 1;
902 
903   // VGPRBlocks is actual number of VGPR blocks minus 1.
904   ProgInfo.VGPRBlocks = alignTo(ProgInfo.NumVGPRsForWavesPerEU,
905                                 STM.getVGPREncodingGranule());
906   ProgInfo.VGPRBlocks = ProgInfo.VGPRBlocks / STM.getVGPREncodingGranule() - 1;
907 
908   // Record first reserved VGPR and number of reserved VGPRs.
909   ProgInfo.ReservedVGPRFirst = STM.debuggerReserveRegs() ? ProgInfo.NumVGPR : 0;
910   ProgInfo.ReservedVGPRCount = STM.getReservedNumVGPRs(MF);
911 
912   // Update DebuggerWavefrontPrivateSegmentOffsetSGPR and
913   // DebuggerPrivateSegmentBufferSGPR fields if "amdgpu-debugger-emit-prologue"
914   // attribute was requested.
915   if (STM.debuggerEmitPrologue()) {
916     ProgInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR =
917       RI->getHWRegIndex(MFI->getScratchWaveOffsetReg());
918     ProgInfo.DebuggerPrivateSegmentBufferSGPR =
919       RI->getHWRegIndex(MFI->getScratchRSrcReg());
920   }
921 
922   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
923   // register.
924   ProgInfo.FloatMode = getFPMode(MF);
925 
926   ProgInfo.IEEEMode = STM.enableIEEEBit(MF);
927 
928   // Make clamp modifier on NaN input returns 0.
929   ProgInfo.DX10Clamp = STM.enableDX10Clamp();
930 
931   unsigned LDSAlignShift;
932   if (STM.getGeneration() < SISubtarget::SEA_ISLANDS) {
933     // LDS is allocated in 64 dword blocks.
934     LDSAlignShift = 8;
935   } else {
936     // LDS is allocated in 128 dword blocks.
937     LDSAlignShift = 9;
938   }
939 
940   unsigned LDSSpillSize =
941     MFI->getLDSWaveSpillSize() * MFI->getMaxFlatWorkGroupSize();
942 
943   ProgInfo.LDSSize = MFI->getLDSSize() + LDSSpillSize;
944   ProgInfo.LDSBlocks =
945       alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
946 
947   // Scratch is allocated in 256 dword blocks.
948   unsigned ScratchAlignShift = 10;
949   // We need to program the hardware with the amount of scratch memory that
950   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
951   // scratch memory used per thread.
952   ProgInfo.ScratchBlocks =
953       alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
954               1ULL << ScratchAlignShift) >>
955       ScratchAlignShift;
956 
957   ProgInfo.ComputePGMRSrc1 =
958       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
959       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
960       S_00B848_PRIORITY(ProgInfo.Priority) |
961       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
962       S_00B848_PRIV(ProgInfo.Priv) |
963       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
964       S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
965       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
966 
967   // 0 = X, 1 = XY, 2 = XYZ
968   unsigned TIDIGCompCnt = 0;
969   if (MFI->hasWorkItemIDZ())
970     TIDIGCompCnt = 2;
971   else if (MFI->hasWorkItemIDY())
972     TIDIGCompCnt = 1;
973 
974   ProgInfo.ComputePGMRSrc2 =
975       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
976       S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
977       S_00B84C_TRAP_HANDLER(STM.isTrapHandlerEnabled()) |
978       S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
979       S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
980       S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
981       S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
982       S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
983       S_00B84C_EXCP_EN_MSB(0) |
984       // For AMDHSA, LDS_SIZE must be zero, as it is populated by the CP.
985       S_00B84C_LDS_SIZE(STM.isAmdHsaOS() ? 0 : ProgInfo.LDSBlocks) |
986       S_00B84C_EXCP_EN(0);
987 }
988 
989 static unsigned getRsrcReg(CallingConv::ID CallConv) {
990   switch (CallConv) {
991   default: LLVM_FALLTHROUGH;
992   case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
993   case CallingConv::AMDGPU_LS: return R_00B528_SPI_SHADER_PGM_RSRC1_LS;
994   case CallingConv::AMDGPU_HS: return R_00B428_SPI_SHADER_PGM_RSRC1_HS;
995   case CallingConv::AMDGPU_ES: return R_00B328_SPI_SHADER_PGM_RSRC1_ES;
996   case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
997   case CallingConv::AMDGPU_VS: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
998   case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
999   }
1000 }
1001 
1002 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
1003                                          const SIProgramInfo &CurrentProgramInfo) {
1004   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
1005   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1006   unsigned RsrcReg = getRsrcReg(MF.getFunction().getCallingConv());
1007 
1008   if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
1009     OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
1010 
1011     OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc1, 4);
1012 
1013     OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
1014     OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc2, 4);
1015 
1016     OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
1017     OutStreamer->EmitIntValue(S_00B860_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
1018 
1019     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
1020     // 0" comment but I don't see a corresponding field in the register spec.
1021   } else {
1022     OutStreamer->EmitIntValue(RsrcReg, 4);
1023     OutStreamer->EmitIntValue(S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
1024                               S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks), 4);
1025     if (STM.isVGPRSpillingEnabled(MF.getFunction())) {
1026       OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
1027       OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
1028     }
1029   }
1030 
1031   if (MF.getFunction().getCallingConv() == CallingConv::AMDGPU_PS) {
1032     OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
1033     OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks), 4);
1034     OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
1035     OutStreamer->EmitIntValue(MFI->getPSInputEnable(), 4);
1036     OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
1037     OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4);
1038   }
1039 
1040   OutStreamer->EmitIntValue(R_SPILLED_SGPRS, 4);
1041   OutStreamer->EmitIntValue(MFI->getNumSpilledSGPRs(), 4);
1042   OutStreamer->EmitIntValue(R_SPILLED_VGPRS, 4);
1043   OutStreamer->EmitIntValue(MFI->getNumSpilledVGPRs(), 4);
1044 }
1045 
1046 // This is the equivalent of EmitProgramInfoSI above, but for when the OS type
1047 // is AMDPAL.  It stores each compute/SPI register setting and other PAL
1048 // metadata items into the PALMetadataMap, combining with any provided by the
1049 // frontend as LLVM metadata. Once all functions are written, PALMetadataMap is
1050 // then written as a single block in the .note section.
1051 void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
1052        const SIProgramInfo &CurrentProgramInfo) {
1053   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1054   // Given the calling convention, calculate the register number for rsrc1. In
1055   // principle the register number could change in future hardware, but we know
1056   // it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so
1057   // we can use the same fixed value that .AMDGPU.config has for Mesa. Note
1058   // that we use a register number rather than a byte offset, so we need to
1059   // divide by 4.
1060   unsigned Rsrc1Reg = getRsrcReg(MF.getFunction().getCallingConv()) / 4;
1061   unsigned Rsrc2Reg = Rsrc1Reg + 1;
1062   // Also calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used
1063   // with a constant offset to access any non-register shader-specific PAL
1064   // metadata key.
1065   unsigned ScratchSizeKey = PALMD::Key::CS_SCRATCH_SIZE;
1066   switch (MF.getFunction().getCallingConv()) {
1067     case CallingConv::AMDGPU_PS:
1068       ScratchSizeKey = PALMD::Key::PS_SCRATCH_SIZE;
1069       break;
1070     case CallingConv::AMDGPU_VS:
1071       ScratchSizeKey = PALMD::Key::VS_SCRATCH_SIZE;
1072       break;
1073     case CallingConv::AMDGPU_GS:
1074       ScratchSizeKey = PALMD::Key::GS_SCRATCH_SIZE;
1075       break;
1076     case CallingConv::AMDGPU_ES:
1077       ScratchSizeKey = PALMD::Key::ES_SCRATCH_SIZE;
1078       break;
1079     case CallingConv::AMDGPU_HS:
1080       ScratchSizeKey = PALMD::Key::HS_SCRATCH_SIZE;
1081       break;
1082     case CallingConv::AMDGPU_LS:
1083       ScratchSizeKey = PALMD::Key::LS_SCRATCH_SIZE;
1084       break;
1085   }
1086   unsigned NumUsedVgprsKey = ScratchSizeKey +
1087       PALMD::Key::VS_NUM_USED_VGPRS - PALMD::Key::VS_SCRATCH_SIZE;
1088   unsigned NumUsedSgprsKey = ScratchSizeKey +
1089       PALMD::Key::VS_NUM_USED_SGPRS - PALMD::Key::VS_SCRATCH_SIZE;
1090   PALMetadataMap[NumUsedVgprsKey] = CurrentProgramInfo.NumVGPRsForWavesPerEU;
1091   PALMetadataMap[NumUsedSgprsKey] = CurrentProgramInfo.NumSGPRsForWavesPerEU;
1092   if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
1093     PALMetadataMap[Rsrc1Reg] |= CurrentProgramInfo.ComputePGMRSrc1;
1094     PALMetadataMap[Rsrc2Reg] |= CurrentProgramInfo.ComputePGMRSrc2;
1095     // ScratchSize is in bytes, 16 aligned.
1096     PALMetadataMap[ScratchSizeKey] |=
1097         alignTo(CurrentProgramInfo.ScratchSize, 16);
1098   } else {
1099     PALMetadataMap[Rsrc1Reg] |= S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
1100         S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks);
1101     if (CurrentProgramInfo.ScratchBlocks > 0)
1102       PALMetadataMap[Rsrc2Reg] |= S_00B84C_SCRATCH_EN(1);
1103     // ScratchSize is in bytes, 16 aligned.
1104     PALMetadataMap[ScratchSizeKey] |=
1105         alignTo(CurrentProgramInfo.ScratchSize, 16);
1106   }
1107   if (MF.getFunction().getCallingConv() == CallingConv::AMDGPU_PS) {
1108     PALMetadataMap[Rsrc2Reg] |=
1109         S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks);
1110     PALMetadataMap[R_0286CC_SPI_PS_INPUT_ENA / 4] |= MFI->getPSInputEnable();
1111     PALMetadataMap[R_0286D0_SPI_PS_INPUT_ADDR / 4] |= MFI->getPSInputAddr();
1112   }
1113 }
1114 
1115 // This is supposed to be log2(Size)
1116 static amd_element_byte_size_t getElementByteSizeValue(unsigned Size) {
1117   switch (Size) {
1118   case 4:
1119     return AMD_ELEMENT_4_BYTES;
1120   case 8:
1121     return AMD_ELEMENT_8_BYTES;
1122   case 16:
1123     return AMD_ELEMENT_16_BYTES;
1124   default:
1125     llvm_unreachable("invalid private_element_size");
1126   }
1127 }
1128 
1129 void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out,
1130                                         const SIProgramInfo &CurrentProgramInfo,
1131                                         const MachineFunction &MF) const {
1132   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1133   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
1134 
1135   AMDGPU::initDefaultAMDKernelCodeT(Out, STM.getFeatureBits());
1136 
1137   Out.compute_pgm_resource_registers =
1138       CurrentProgramInfo.ComputePGMRSrc1 |
1139       (CurrentProgramInfo.ComputePGMRSrc2 << 32);
1140   Out.code_properties = AMD_CODE_PROPERTY_IS_PTR64;
1141 
1142   if (CurrentProgramInfo.DynamicCallStack)
1143     Out.code_properties |= AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK;
1144 
1145   AMD_HSA_BITS_SET(Out.code_properties,
1146                    AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE,
1147                    getElementByteSizeValue(STM.getMaxPrivateElementSize()));
1148 
1149   if (MFI->hasPrivateSegmentBuffer()) {
1150     Out.code_properties |=
1151       AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
1152   }
1153 
1154   if (MFI->hasDispatchPtr())
1155     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
1156 
1157   if (MFI->hasQueuePtr())
1158     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
1159 
1160   if (MFI->hasKernargSegmentPtr())
1161     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
1162 
1163   if (MFI->hasDispatchID())
1164     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
1165 
1166   if (MFI->hasFlatScratchInit())
1167     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
1168 
1169   if (MFI->hasGridWorkgroupCountX()) {
1170     Out.code_properties |=
1171       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X;
1172   }
1173 
1174   if (MFI->hasGridWorkgroupCountY()) {
1175     Out.code_properties |=
1176       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y;
1177   }
1178 
1179   if (MFI->hasGridWorkgroupCountZ()) {
1180     Out.code_properties |=
1181       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z;
1182   }
1183 
1184   if (MFI->hasDispatchPtr())
1185     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
1186 
1187   if (STM.debuggerSupported())
1188     Out.code_properties |= AMD_CODE_PROPERTY_IS_DEBUG_SUPPORTED;
1189 
1190   if (STM.isXNACKEnabled())
1191     Out.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED;
1192 
1193   // FIXME: Should use getKernArgSize
1194   Out.kernarg_segment_byte_size =
1195     STM.getKernArgSegmentSize(MF, MFI->getABIArgOffset());
1196   Out.wavefront_sgpr_count = CurrentProgramInfo.NumSGPR;
1197   Out.workitem_vgpr_count = CurrentProgramInfo.NumVGPR;
1198   Out.workitem_private_segment_byte_size = CurrentProgramInfo.ScratchSize;
1199   Out.workgroup_group_segment_byte_size = CurrentProgramInfo.LDSSize;
1200   Out.reserved_vgpr_first = CurrentProgramInfo.ReservedVGPRFirst;
1201   Out.reserved_vgpr_count = CurrentProgramInfo.ReservedVGPRCount;
1202 
1203   // These alignment values are specified in powers of two, so alignment =
1204   // 2^n.  The minimum alignment is 2^4 = 16.
1205   Out.kernarg_segment_alignment = std::max((size_t)4,
1206       countTrailingZeros(MFI->getMaxKernArgAlign()));
1207 
1208   if (STM.debuggerEmitPrologue()) {
1209     Out.debug_wavefront_private_segment_offset_sgpr =
1210       CurrentProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR;
1211     Out.debug_private_segment_buffer_sgpr =
1212       CurrentProgramInfo.DebuggerPrivateSegmentBufferSGPR;
1213   }
1214 }
1215 
1216 AMDGPU::HSAMD::Kernel::CodeProps::Metadata AMDGPUAsmPrinter::getHSACodeProps(
1217     const MachineFunction &MF,
1218     const SIProgramInfo &ProgramInfo) const {
1219   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
1220   const SIMachineFunctionInfo &MFI = *MF.getInfo<SIMachineFunctionInfo>();
1221   HSAMD::Kernel::CodeProps::Metadata HSACodeProps;
1222 
1223   HSACodeProps.mKernargSegmentSize =
1224       STM.getKernArgSegmentSize(MF, MFI.getABIArgOffset());
1225   HSACodeProps.mGroupSegmentFixedSize = ProgramInfo.LDSSize;
1226   HSACodeProps.mPrivateSegmentFixedSize = ProgramInfo.ScratchSize;
1227   HSACodeProps.mKernargSegmentAlign =
1228       std::max(uint32_t(4), MFI.getMaxKernArgAlign());
1229   HSACodeProps.mWavefrontSize = STM.getWavefrontSize();
1230   HSACodeProps.mNumSGPRs = CurrentProgramInfo.NumSGPR;
1231   HSACodeProps.mNumVGPRs = CurrentProgramInfo.NumVGPR;
1232   HSACodeProps.mMaxFlatWorkGroupSize = MFI.getMaxFlatWorkGroupSize();
1233   HSACodeProps.mIsDynamicCallStack = ProgramInfo.DynamicCallStack;
1234   HSACodeProps.mIsXNACKEnabled = STM.isXNACKEnabled();
1235   HSACodeProps.mNumSpilledSGPRs = MFI.getNumSpilledSGPRs();
1236   HSACodeProps.mNumSpilledVGPRs = MFI.getNumSpilledVGPRs();
1237 
1238   return HSACodeProps;
1239 }
1240 
1241 AMDGPU::HSAMD::Kernel::DebugProps::Metadata AMDGPUAsmPrinter::getHSADebugProps(
1242     const MachineFunction &MF,
1243     const SIProgramInfo &ProgramInfo) const {
1244   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
1245   HSAMD::Kernel::DebugProps::Metadata HSADebugProps;
1246 
1247   if (!STM.debuggerSupported())
1248     return HSADebugProps;
1249 
1250   HSADebugProps.mDebuggerABIVersion.push_back(1);
1251   HSADebugProps.mDebuggerABIVersion.push_back(0);
1252   HSADebugProps.mReservedNumVGPRs = ProgramInfo.ReservedVGPRCount;
1253   HSADebugProps.mReservedFirstVGPR = ProgramInfo.ReservedVGPRFirst;
1254 
1255   if (STM.debuggerEmitPrologue()) {
1256     HSADebugProps.mPrivateSegmentBufferSGPR =
1257         ProgramInfo.DebuggerPrivateSegmentBufferSGPR;
1258     HSADebugProps.mWavefrontPrivateSegmentOffsetSGPR =
1259         ProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR;
1260   }
1261 
1262   return HSADebugProps;
1263 }
1264 
1265 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
1266                                        unsigned AsmVariant,
1267                                        const char *ExtraCode, raw_ostream &O) {
1268   // First try the generic code, which knows about modifiers like 'c' and 'n'.
1269   if (!AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O))
1270     return false;
1271 
1272   if (ExtraCode && ExtraCode[0]) {
1273     if (ExtraCode[1] != 0)
1274       return true; // Unknown modifier.
1275 
1276     switch (ExtraCode[0]) {
1277     case 'r':
1278       break;
1279     default:
1280       return true;
1281     }
1282   }
1283 
1284   // TODO: Should be able to support other operand types like globals.
1285   const MachineOperand &MO = MI->getOperand(OpNo);
1286   if (MO.isReg()) {
1287     AMDGPUInstPrinter::printRegOperand(MO.getReg(), O,
1288                                        *MF->getSubtarget().getRegisterInfo());
1289     return false;
1290   }
1291 
1292   return true;
1293 }
1294