1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
15 //
16 //===----------------------------------------------------------------------===//
17 //
18 
19 #include "AMDGPUAsmPrinter.h"
20 #include "AMDGPU.h"
21 #include "AMDGPUSubtarget.h"
22 #include "AMDGPUTargetMachine.h"
23 #include "InstPrinter/AMDGPUInstPrinter.h"
24 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
25 #include "R600Defines.h"
26 #include "R600MachineFunctionInfo.h"
27 #include "R600RegisterInfo.h"
28 #include "SIDefines.h"
29 #include "SIInstrInfo.h"
30 #include "SIMachineFunctionInfo.h"
31 #include "SIRegisterInfo.h"
32 #include "Utils/AMDGPUBaseInfo.h"
33 #include "llvm/BinaryFormat/ELF.h"
34 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/CodeGen/TargetLoweringObjectFile.h"
36 #include "llvm/IR/DiagnosticInfo.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCSectionELF.h"
39 #include "llvm/MC/MCStreamer.h"
40 #include "llvm/Support/AMDGPUMetadata.h"
41 #include "llvm/Support/MathExtras.h"
42 #include "llvm/Support/TargetRegistry.h"
43 
44 using namespace llvm;
45 using namespace llvm::AMDGPU;
46 
47 // TODO: This should get the default rounding mode from the kernel. We just set
48 // the default here, but this could change if the OpenCL rounding mode pragmas
49 // are used.
50 //
51 // The denormal mode here should match what is reported by the OpenCL runtime
52 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
53 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
54 //
55 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
56 // precision, and leaves single precision to flush all and does not report
57 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
58 // CL_FP_DENORM for both.
59 //
60 // FIXME: It seems some instructions do not support single precision denormals
61 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
62 // and sin_f32, cos_f32 on most parts).
63 
64 // We want to use these instructions, and using fp32 denormals also causes
65 // instructions to run at the double precision rate for the device so it's
66 // probably best to just report no single precision denormals.
67 static uint32_t getFPMode(const MachineFunction &F) {
68   const SISubtarget& ST = F.getSubtarget<SISubtarget>();
69   // TODO: Is there any real use for the flush in only / flush out only modes?
70 
71   uint32_t FP32Denormals =
72     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
73 
74   uint32_t FP64Denormals =
75     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
76 
77   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
78          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
79          FP_DENORM_MODE_SP(FP32Denormals) |
80          FP_DENORM_MODE_DP(FP64Denormals);
81 }
82 
83 static AsmPrinter *
84 createAMDGPUAsmPrinterPass(TargetMachine &tm,
85                            std::unique_ptr<MCStreamer> &&Streamer) {
86   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
87 }
88 
89 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
90   TargetRegistry::RegisterAsmPrinter(getTheAMDGPUTarget(),
91                                      createAMDGPUAsmPrinterPass);
92   TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(),
93                                      createAMDGPUAsmPrinterPass);
94 }
95 
96 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
97                                    std::unique_ptr<MCStreamer> Streamer)
98   : AsmPrinter(TM, std::move(Streamer)) {
99     AMDGPUASI = static_cast<AMDGPUTargetMachine*>(&TM)->getAMDGPUAS();
100   }
101 
102 StringRef AMDGPUAsmPrinter::getPassName() const {
103   return "AMDGPU Assembly Printer";
104 }
105 
106 const MCSubtargetInfo* AMDGPUAsmPrinter::getSTI() const {
107   return TM.getMCSubtargetInfo();
108 }
109 
110 AMDGPUTargetStreamer* AMDGPUAsmPrinter::getTargetStreamer() const {
111   if (!OutStreamer)
112     return nullptr;
113   return static_cast<AMDGPUTargetStreamer*>(OutStreamer->getTargetStreamer());
114 }
115 
116 void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) {
117   if (TM.getTargetTriple().getArch() != Triple::amdgcn)
118     return;
119 
120   if (TM.getTargetTriple().getOS() != Triple::AMDHSA &&
121       TM.getTargetTriple().getOS() != Triple::AMDPAL)
122     return;
123 
124   if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
125     HSAMetadataStream.begin(M);
126 
127   if (TM.getTargetTriple().getOS() == Triple::AMDPAL)
128     readPALMetadata(M);
129 
130   // Deprecated notes are not emitted for code object v3.
131   if (IsaInfo::hasCodeObjectV3(getSTI()->getFeatureBits()))
132     return;
133 
134   // HSA emits NT_AMDGPU_HSA_CODE_OBJECT_VERSION for code objects v2.
135   if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
136     getTargetStreamer()->EmitDirectiveHSACodeObjectVersion(2, 1);
137 
138   // HSA and PAL emit NT_AMDGPU_HSA_ISA for code objects v2.
139   IsaInfo::IsaVersion ISA = IsaInfo::getIsaVersion(getSTI()->getFeatureBits());
140   getTargetStreamer()->EmitDirectiveHSACodeObjectISA(
141       ISA.Major, ISA.Minor, ISA.Stepping, "AMD", "AMDGPU");
142 }
143 
144 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
145   if (TM.getTargetTriple().getArch() != Triple::amdgcn)
146     return;
147 
148   // Following code requires TargetStreamer to be present.
149   if (!getTargetStreamer())
150     return;
151 
152   // Emit ISA Version (NT_AMD_AMDGPU_ISA).
153   std::string ISAVersionString;
154   raw_string_ostream ISAVersionStream(ISAVersionString);
155   IsaInfo::streamIsaVersion(getSTI(), ISAVersionStream);
156   getTargetStreamer()->EmitISAVersion(ISAVersionStream.str());
157 
158   // Emit HSA Metadata (NT_AMD_AMDGPU_HSA_METADATA).
159   if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
160     HSAMetadataStream.end();
161     getTargetStreamer()->EmitHSAMetadata(HSAMetadataStream.getHSAMetadata());
162   }
163 
164   // Emit PAL Metadata (NT_AMD_AMDGPU_PAL_METADATA).
165   if (TM.getTargetTriple().getOS() == Triple::AMDPAL) {
166     // Copy the PAL metadata from the map where we collected it into a vector,
167     // then write it as a .note.
168     PALMD::Metadata PALMetadataVector;
169     for (auto i : PALMetadataMap) {
170       PALMetadataVector.push_back(i.first);
171       PALMetadataVector.push_back(i.second);
172     }
173     getTargetStreamer()->EmitPALMetadata(PALMetadataVector);
174   }
175 }
176 
177 bool AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough(
178   const MachineBasicBlock *MBB) const {
179   if (!AsmPrinter::isBlockOnlyReachableByFallthrough(MBB))
180     return false;
181 
182   if (MBB->empty())
183     return true;
184 
185   // If this is a block implementing a long branch, an expression relative to
186   // the start of the block is needed.  to the start of the block.
187   // XXX - Is there a smarter way to check this?
188   return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
189 }
190 
191 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
192   const AMDGPUMachineFunction *MFI = MF->getInfo<AMDGPUMachineFunction>();
193   if (!MFI->isEntryFunction())
194     return;
195 
196   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
197   amd_kernel_code_t KernelCode;
198   if (STM.isAmdCodeObjectV2(*MF)) {
199     getAmdKernelCode(KernelCode, CurrentProgramInfo, *MF);
200 
201     OutStreamer->SwitchSection(getObjFileLowering().getTextSection());
202     getTargetStreamer()->EmitAMDKernelCodeT(KernelCode);
203   }
204 
205   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
206     return;
207 
208   HSAMetadataStream.emitKernel(*MF->getFunction(),
209                                getHSACodeProps(*MF, CurrentProgramInfo),
210                                getHSADebugProps(*MF, CurrentProgramInfo));
211 }
212 
213 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
214   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
215   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
216   if (MFI->isEntryFunction() && STM.isAmdCodeObjectV2(*MF)) {
217     SmallString<128> SymbolName;
218     getNameWithPrefix(SymbolName, MF->getFunction()),
219     getTargetStreamer()->EmitAMDGPUSymbolType(
220         SymbolName, ELF::STT_AMDGPU_HSA_KERNEL);
221   }
222   const AMDGPUSubtarget &STI = MF->getSubtarget<AMDGPUSubtarget>();
223   if (STI.dumpCode()) {
224     // Disassemble function name label to text.
225     DisasmLines.push_back(MF->getFunction()->getName().str() + ":");
226     DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size());
227     HexLines.push_back("");
228   }
229 
230   AsmPrinter::EmitFunctionEntryLabel();
231 }
232 
233 void AMDGPUAsmPrinter::EmitBasicBlockStart(const MachineBasicBlock &MBB) const {
234   const AMDGPUSubtarget &STI = MBB.getParent()->getSubtarget<AMDGPUSubtarget>();
235   if (STI.dumpCode() && !isBlockOnlyReachableByFallthrough(&MBB)) {
236     // Write a line for the basic block label if it is not only fallthrough.
237     DisasmLines.push_back(
238         (Twine("BB") + Twine(getFunctionNumber())
239          + "_" + Twine(MBB.getNumber()) + ":").str());
240     DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size());
241     HexLines.push_back("");
242   }
243   AsmPrinter::EmitBasicBlockStart(MBB);
244 }
245 
246 void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
247 
248   // Group segment variables aren't emitted in HSA.
249   if (AMDGPU::isGroupSegment(GV))
250     return;
251 
252   AsmPrinter::EmitGlobalVariable(GV);
253 }
254 
255 bool AMDGPUAsmPrinter::doFinalization(Module &M) {
256   CallGraphResourceInfo.clear();
257   return AsmPrinter::doFinalization(M);
258 }
259 
260 // For the amdpal OS type, read the amdgpu.pal.metadata supplied by the
261 // frontend into our PALMetadataMap, ready for per-function modification.  It
262 // is a NamedMD containing an MDTuple containing a number of MDNodes each of
263 // which is an integer value, and each two integer values forms a key=value
264 // pair that we store as PALMetadataMap[key]=value in the map.
265 void AMDGPUAsmPrinter::readPALMetadata(Module &M) {
266   auto NamedMD = M.getNamedMetadata("amdgpu.pal.metadata");
267   if (!NamedMD || !NamedMD->getNumOperands())
268     return;
269   auto Tuple = dyn_cast<MDTuple>(NamedMD->getOperand(0));
270   if (!Tuple)
271     return;
272   for (unsigned I = 0, E = Tuple->getNumOperands() & -2; I != E; I += 2) {
273     auto Key = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I));
274     auto Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I + 1));
275     if (!Key || !Val)
276       continue;
277     PALMetadataMap[Key->getZExtValue()] = Val->getZExtValue();
278   }
279 }
280 
281 // Print comments that apply to both callable functions and entry points.
282 void AMDGPUAsmPrinter::emitCommonFunctionComments(
283   uint32_t NumVGPR,
284   uint32_t NumSGPR,
285   uint64_t ScratchSize,
286   uint64_t CodeSize) {
287   OutStreamer->emitRawComment(" codeLenInByte = " + Twine(CodeSize), false);
288   OutStreamer->emitRawComment(" NumSgprs: " + Twine(NumSGPR), false);
289   OutStreamer->emitRawComment(" NumVgprs: " + Twine(NumVGPR), false);
290   OutStreamer->emitRawComment(" ScratchSize: " + Twine(ScratchSize), false);
291 }
292 
293 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
294   CurrentProgramInfo = SIProgramInfo();
295 
296   const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
297 
298   // The starting address of all shader programs must be 256 bytes aligned.
299   // Regular functions just need the basic required instruction alignment.
300   MF.setAlignment(MFI->isEntryFunction() ? 8 : 2);
301 
302   SetupMachineFunction(MF);
303 
304   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
305   MCContext &Context = getObjFileLowering().getContext();
306   if (!STM.isAmdHsaOS()) {
307     MCSectionELF *ConfigSection =
308         Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
309     OutStreamer->SwitchSection(ConfigSection);
310   }
311 
312   if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
313     if (MFI->isEntryFunction()) {
314       getSIProgramInfo(CurrentProgramInfo, MF);
315     } else {
316       auto I = CallGraphResourceInfo.insert(
317         std::make_pair(MF.getFunction(), SIFunctionResourceInfo()));
318       SIFunctionResourceInfo &Info = I.first->second;
319       assert(I.second && "should only be called once per function");
320       Info = analyzeResourceUsage(MF);
321     }
322 
323     if (STM.isAmdPalOS())
324       EmitPALMetadata(MF, CurrentProgramInfo);
325     if (!STM.isAmdHsaOS()) {
326       EmitProgramInfoSI(MF, CurrentProgramInfo);
327     }
328   } else {
329     EmitProgramInfoR600(MF);
330   }
331 
332   DisasmLines.clear();
333   HexLines.clear();
334   DisasmLineMaxLen = 0;
335 
336   EmitFunctionBody();
337 
338   if (isVerbose()) {
339     MCSectionELF *CommentSection =
340         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
341     OutStreamer->SwitchSection(CommentSection);
342 
343     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
344       if (!MFI->isEntryFunction()) {
345         OutStreamer->emitRawComment(" Function info:", false);
346         SIFunctionResourceInfo &Info = CallGraphResourceInfo[MF.getFunction()];
347         emitCommonFunctionComments(
348           Info.NumVGPR,
349           Info.getTotalNumSGPRs(MF.getSubtarget<SISubtarget>()),
350           Info.PrivateSegmentSize,
351           getFunctionCodeSize(MF));
352         return false;
353       }
354 
355       OutStreamer->emitRawComment(" Kernel info:", false);
356       emitCommonFunctionComments(CurrentProgramInfo.NumVGPR,
357                                  CurrentProgramInfo.NumSGPR,
358                                  CurrentProgramInfo.ScratchSize,
359                                  getFunctionCodeSize(MF));
360 
361       OutStreamer->emitRawComment(
362         " FloatMode: " + Twine(CurrentProgramInfo.FloatMode), false);
363       OutStreamer->emitRawComment(
364         " IeeeMode: " + Twine(CurrentProgramInfo.IEEEMode), false);
365       OutStreamer->emitRawComment(
366         " LDSByteSize: " + Twine(CurrentProgramInfo.LDSSize) +
367         " bytes/workgroup (compile time only)", false);
368 
369       OutStreamer->emitRawComment(
370         " SGPRBlocks: " + Twine(CurrentProgramInfo.SGPRBlocks), false);
371       OutStreamer->emitRawComment(
372         " VGPRBlocks: " + Twine(CurrentProgramInfo.VGPRBlocks), false);
373 
374       OutStreamer->emitRawComment(
375         " NumSGPRsForWavesPerEU: " +
376         Twine(CurrentProgramInfo.NumSGPRsForWavesPerEU), false);
377       OutStreamer->emitRawComment(
378         " NumVGPRsForWavesPerEU: " +
379         Twine(CurrentProgramInfo.NumVGPRsForWavesPerEU), false);
380 
381       OutStreamer->emitRawComment(
382         " ReservedVGPRFirst: " + Twine(CurrentProgramInfo.ReservedVGPRFirst),
383         false);
384       OutStreamer->emitRawComment(
385         " ReservedVGPRCount: " + Twine(CurrentProgramInfo.ReservedVGPRCount),
386         false);
387 
388       if (MF.getSubtarget<SISubtarget>().debuggerEmitPrologue()) {
389         OutStreamer->emitRawComment(
390           " DebuggerWavefrontPrivateSegmentOffsetSGPR: s" +
391           Twine(CurrentProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR), false);
392         OutStreamer->emitRawComment(
393           " DebuggerPrivateSegmentBufferSGPR: s" +
394           Twine(CurrentProgramInfo.DebuggerPrivateSegmentBufferSGPR), false);
395       }
396 
397       OutStreamer->emitRawComment(
398         " COMPUTE_PGM_RSRC2:USER_SGPR: " +
399         Twine(G_00B84C_USER_SGPR(CurrentProgramInfo.ComputePGMRSrc2)), false);
400       OutStreamer->emitRawComment(
401         " COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
402         Twine(G_00B84C_TRAP_HANDLER(CurrentProgramInfo.ComputePGMRSrc2)), false);
403       OutStreamer->emitRawComment(
404         " COMPUTE_PGM_RSRC2:TGID_X_EN: " +
405         Twine(G_00B84C_TGID_X_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
406       OutStreamer->emitRawComment(
407         " COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
408         Twine(G_00B84C_TGID_Y_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
409       OutStreamer->emitRawComment(
410         " COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
411         Twine(G_00B84C_TGID_Z_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
412       OutStreamer->emitRawComment(
413         " COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
414         Twine(G_00B84C_TIDIG_COMP_CNT(CurrentProgramInfo.ComputePGMRSrc2)),
415         false);
416     } else {
417       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
418       OutStreamer->emitRawComment(
419         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->CFStackSize)));
420     }
421   }
422 
423   if (STM.dumpCode()) {
424 
425     OutStreamer->SwitchSection(
426         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
427 
428     for (size_t i = 0; i < DisasmLines.size(); ++i) {
429       std::string Comment = "\n";
430       if (!HexLines[i].empty()) {
431         Comment = std::string(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
432         Comment += " ; " + HexLines[i] + "\n";
433       }
434 
435       OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
436       OutStreamer->EmitBytes(StringRef(Comment));
437     }
438   }
439 
440   return false;
441 }
442 
443 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
444   unsigned MaxGPR = 0;
445   bool killPixel = false;
446   const R600Subtarget &STM = MF.getSubtarget<R600Subtarget>();
447   const R600RegisterInfo *RI = STM.getRegisterInfo();
448   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
449 
450   for (const MachineBasicBlock &MBB : MF) {
451     for (const MachineInstr &MI : MBB) {
452       if (MI.getOpcode() == AMDGPU::KILLGT)
453         killPixel = true;
454       unsigned numOperands = MI.getNumOperands();
455       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
456         const MachineOperand &MO = MI.getOperand(op_idx);
457         if (!MO.isReg())
458           continue;
459         unsigned HWReg = RI->getHWRegIndex(MO.getReg());
460 
461         // Register with value > 127 aren't GPR
462         if (HWReg > 127)
463           continue;
464         MaxGPR = std::max(MaxGPR, HWReg);
465       }
466     }
467   }
468 
469   unsigned RsrcReg;
470   if (STM.getGeneration() >= R600Subtarget::EVERGREEN) {
471     // Evergreen / Northern Islands
472     switch (MF.getFunction()->getCallingConv()) {
473     default: LLVM_FALLTHROUGH;
474     case CallingConv::AMDGPU_CS: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
475     case CallingConv::AMDGPU_GS: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
476     case CallingConv::AMDGPU_PS: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
477     case CallingConv::AMDGPU_VS: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
478     }
479   } else {
480     // R600 / R700
481     switch (MF.getFunction()->getCallingConv()) {
482     default: LLVM_FALLTHROUGH;
483     case CallingConv::AMDGPU_GS: LLVM_FALLTHROUGH;
484     case CallingConv::AMDGPU_CS: LLVM_FALLTHROUGH;
485     case CallingConv::AMDGPU_VS: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
486     case CallingConv::AMDGPU_PS: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
487     }
488   }
489 
490   OutStreamer->EmitIntValue(RsrcReg, 4);
491   OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
492                            S_STACK_SIZE(MFI->CFStackSize), 4);
493   OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
494   OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
495 
496   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
497     OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
498     OutStreamer->EmitIntValue(alignTo(MFI->getLDSSize(), 4) >> 2, 4);
499   }
500 }
501 
502 uint64_t AMDGPUAsmPrinter::getFunctionCodeSize(const MachineFunction &MF) const {
503   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
504   const SIInstrInfo *TII = STM.getInstrInfo();
505 
506   uint64_t CodeSize = 0;
507 
508   for (const MachineBasicBlock &MBB : MF) {
509     for (const MachineInstr &MI : MBB) {
510       // TODO: CodeSize should account for multiple functions.
511 
512       // TODO: Should we count size of debug info?
513       if (MI.isDebugValue())
514         continue;
515 
516       CodeSize += TII->getInstSizeInBytes(MI);
517     }
518   }
519 
520   return CodeSize;
521 }
522 
523 static bool hasAnyNonFlatUseOfReg(const MachineRegisterInfo &MRI,
524                                   const SIInstrInfo &TII,
525                                   unsigned Reg) {
526   for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) {
527     if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent()))
528       return true;
529   }
530 
531   return false;
532 }
533 
534 static unsigned getNumExtraSGPRs(const SISubtarget &ST,
535                                  bool VCCUsed,
536                                  bool FlatScrUsed) {
537   unsigned ExtraSGPRs = 0;
538   if (VCCUsed)
539     ExtraSGPRs = 2;
540 
541   if (ST.getGeneration() < SISubtarget::VOLCANIC_ISLANDS) {
542     if (FlatScrUsed)
543       ExtraSGPRs = 4;
544   } else {
545     if (ST.isXNACKEnabled())
546       ExtraSGPRs = 4;
547 
548     if (FlatScrUsed)
549       ExtraSGPRs = 6;
550   }
551 
552   return ExtraSGPRs;
553 }
554 
555 int32_t AMDGPUAsmPrinter::SIFunctionResourceInfo::getTotalNumSGPRs(
556   const SISubtarget &ST) const {
557   return NumExplicitSGPR + getNumExtraSGPRs(ST, UsesVCC, UsesFlatScratch);
558 }
559 
560 AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
561   const MachineFunction &MF) const {
562   SIFunctionResourceInfo Info;
563 
564   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
565   const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
566   const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
567   const MachineRegisterInfo &MRI = MF.getRegInfo();
568   const SIInstrInfo *TII = ST.getInstrInfo();
569   const SIRegisterInfo &TRI = TII->getRegisterInfo();
570 
571   Info.UsesFlatScratch = MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_LO) ||
572                          MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_HI);
573 
574   // Even if FLAT_SCRATCH is implicitly used, it has no effect if flat
575   // instructions aren't used to access the scratch buffer. Inline assembly may
576   // need it though.
577   //
578   // If we only have implicit uses of flat_scr on flat instructions, it is not
579   // really needed.
580   if (Info.UsesFlatScratch && !MFI->hasFlatScratchInit() &&
581       (!hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR) &&
582        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_LO) &&
583        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_HI))) {
584     Info.UsesFlatScratch = false;
585   }
586 
587   Info.HasDynamicallySizedStack = FrameInfo.hasVarSizedObjects();
588   Info.PrivateSegmentSize = FrameInfo.getStackSize();
589 
590 
591   Info.UsesVCC = MRI.isPhysRegUsed(AMDGPU::VCC_LO) ||
592                  MRI.isPhysRegUsed(AMDGPU::VCC_HI);
593 
594   // If there are no calls, MachineRegisterInfo can tell us the used register
595   // count easily.
596   // A tail call isn't considered a call for MachineFrameInfo's purposes.
597   if (!FrameInfo.hasCalls() && !FrameInfo.hasTailCall()) {
598     MCPhysReg HighestVGPRReg = AMDGPU::NoRegister;
599     for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) {
600       if (MRI.isPhysRegUsed(Reg)) {
601         HighestVGPRReg = Reg;
602         break;
603       }
604     }
605 
606     MCPhysReg HighestSGPRReg = AMDGPU::NoRegister;
607     for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) {
608       if (MRI.isPhysRegUsed(Reg)) {
609         HighestSGPRReg = Reg;
610         break;
611       }
612     }
613 
614     // We found the maximum register index. They start at 0, so add one to get the
615     // number of registers.
616     Info.NumVGPR = HighestVGPRReg == AMDGPU::NoRegister ? 0 :
617       TRI.getHWRegIndex(HighestVGPRReg) + 1;
618     Info.NumExplicitSGPR = HighestSGPRReg == AMDGPU::NoRegister ? 0 :
619       TRI.getHWRegIndex(HighestSGPRReg) + 1;
620 
621     return Info;
622   }
623 
624   int32_t MaxVGPR = -1;
625   int32_t MaxSGPR = -1;
626   uint64_t CalleeFrameSize = 0;
627 
628   for (const MachineBasicBlock &MBB : MF) {
629     for (const MachineInstr &MI : MBB) {
630       // TODO: Check regmasks? Do they occur anywhere except calls?
631       for (const MachineOperand &MO : MI.operands()) {
632         unsigned Width = 0;
633         bool IsSGPR = false;
634 
635         if (!MO.isReg())
636           continue;
637 
638         unsigned Reg = MO.getReg();
639         switch (Reg) {
640         case AMDGPU::EXEC:
641         case AMDGPU::EXEC_LO:
642         case AMDGPU::EXEC_HI:
643         case AMDGPU::SCC:
644         case AMDGPU::M0:
645         case AMDGPU::SRC_SHARED_BASE:
646         case AMDGPU::SRC_SHARED_LIMIT:
647         case AMDGPU::SRC_PRIVATE_BASE:
648         case AMDGPU::SRC_PRIVATE_LIMIT:
649           continue;
650 
651         case AMDGPU::NoRegister:
652           assert(MI.isDebugValue());
653           continue;
654 
655         case AMDGPU::VCC:
656         case AMDGPU::VCC_LO:
657         case AMDGPU::VCC_HI:
658           Info.UsesVCC = true;
659           continue;
660 
661         case AMDGPU::FLAT_SCR:
662         case AMDGPU::FLAT_SCR_LO:
663         case AMDGPU::FLAT_SCR_HI:
664           continue;
665 
666         case AMDGPU::TBA:
667         case AMDGPU::TBA_LO:
668         case AMDGPU::TBA_HI:
669         case AMDGPU::TMA:
670         case AMDGPU::TMA_LO:
671         case AMDGPU::TMA_HI:
672           llvm_unreachable("trap handler registers should not be used");
673 
674         default:
675           break;
676         }
677 
678         if (AMDGPU::SReg_32RegClass.contains(Reg)) {
679           assert(!AMDGPU::TTMP_32RegClass.contains(Reg) &&
680                  "trap handler registers should not be used");
681           IsSGPR = true;
682           Width = 1;
683         } else if (AMDGPU::VGPR_32RegClass.contains(Reg)) {
684           IsSGPR = false;
685           Width = 1;
686         } else if (AMDGPU::SReg_64RegClass.contains(Reg)) {
687           assert(!AMDGPU::TTMP_64RegClass.contains(Reg) &&
688                  "trap handler registers should not be used");
689           IsSGPR = true;
690           Width = 2;
691         } else if (AMDGPU::VReg_64RegClass.contains(Reg)) {
692           IsSGPR = false;
693           Width = 2;
694         } else if (AMDGPU::VReg_96RegClass.contains(Reg)) {
695           IsSGPR = false;
696           Width = 3;
697         } else if (AMDGPU::SReg_128RegClass.contains(Reg)) {
698           IsSGPR = true;
699           Width = 4;
700         } else if (AMDGPU::VReg_128RegClass.contains(Reg)) {
701           IsSGPR = false;
702           Width = 4;
703         } else if (AMDGPU::SReg_256RegClass.contains(Reg)) {
704           IsSGPR = true;
705           Width = 8;
706         } else if (AMDGPU::VReg_256RegClass.contains(Reg)) {
707           IsSGPR = false;
708           Width = 8;
709         } else if (AMDGPU::SReg_512RegClass.contains(Reg)) {
710           IsSGPR = true;
711           Width = 16;
712         } else if (AMDGPU::VReg_512RegClass.contains(Reg)) {
713           IsSGPR = false;
714           Width = 16;
715         } else {
716           llvm_unreachable("Unknown register class");
717         }
718         unsigned HWReg = TRI.getHWRegIndex(Reg);
719         int MaxUsed = HWReg + Width - 1;
720         if (IsSGPR) {
721           MaxSGPR = MaxUsed > MaxSGPR ? MaxUsed : MaxSGPR;
722         } else {
723           MaxVGPR = MaxUsed > MaxVGPR ? MaxUsed : MaxVGPR;
724         }
725       }
726 
727       if (MI.isCall()) {
728         // Pseudo used just to encode the underlying global. Is there a better
729         // way to track this?
730 
731         const MachineOperand *CalleeOp
732           = TII->getNamedOperand(MI, AMDGPU::OpName::callee);
733         const Function *Callee = cast<Function>(CalleeOp->getGlobal());
734         if (Callee->isDeclaration()) {
735           // If this is a call to an external function, we can't do much. Make
736           // conservative guesses.
737 
738           // 48 SGPRs - vcc, - flat_scr, -xnack
739           int MaxSGPRGuess = 47 - getNumExtraSGPRs(ST, true,
740                                                    ST.hasFlatAddressSpace());
741           MaxSGPR = std::max(MaxSGPR, MaxSGPRGuess);
742           MaxVGPR = std::max(MaxVGPR, 23);
743 
744           CalleeFrameSize = std::max(CalleeFrameSize, UINT64_C(16384));
745           Info.UsesVCC = true;
746           Info.UsesFlatScratch = ST.hasFlatAddressSpace();
747           Info.HasDynamicallySizedStack = true;
748         } else {
749           // We force CodeGen to run in SCC order, so the callee's register
750           // usage etc. should be the cumulative usage of all callees.
751           auto I = CallGraphResourceInfo.find(Callee);
752           assert(I != CallGraphResourceInfo.end() &&
753                  "callee should have been handled before caller");
754 
755           MaxSGPR = std::max(I->second.NumExplicitSGPR - 1, MaxSGPR);
756           MaxVGPR = std::max(I->second.NumVGPR - 1, MaxVGPR);
757           CalleeFrameSize
758             = std::max(I->second.PrivateSegmentSize, CalleeFrameSize);
759           Info.UsesVCC |= I->second.UsesVCC;
760           Info.UsesFlatScratch |= I->second.UsesFlatScratch;
761           Info.HasDynamicallySizedStack |= I->second.HasDynamicallySizedStack;
762           Info.HasRecursion |= I->second.HasRecursion;
763         }
764 
765         if (!Callee->doesNotRecurse())
766           Info.HasRecursion = true;
767       }
768     }
769   }
770 
771   Info.NumExplicitSGPR = MaxSGPR + 1;
772   Info.NumVGPR = MaxVGPR + 1;
773   Info.PrivateSegmentSize += CalleeFrameSize;
774 
775   return Info;
776 }
777 
778 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
779                                         const MachineFunction &MF) {
780   SIFunctionResourceInfo Info = analyzeResourceUsage(MF);
781 
782   ProgInfo.NumVGPR = Info.NumVGPR;
783   ProgInfo.NumSGPR = Info.NumExplicitSGPR;
784   ProgInfo.ScratchSize = Info.PrivateSegmentSize;
785   ProgInfo.VCCUsed = Info.UsesVCC;
786   ProgInfo.FlatUsed = Info.UsesFlatScratch;
787   ProgInfo.DynamicCallStack = Info.HasDynamicallySizedStack || Info.HasRecursion;
788 
789   if (!isUInt<32>(ProgInfo.ScratchSize)) {
790     DiagnosticInfoStackSize DiagStackSize(*MF.getFunction(),
791                                           ProgInfo.ScratchSize, DS_Error);
792     MF.getFunction()->getContext().diagnose(DiagStackSize);
793   }
794 
795   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
796   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
797   const SIInstrInfo *TII = STM.getInstrInfo();
798   const SIRegisterInfo *RI = &TII->getRegisterInfo();
799 
800   unsigned ExtraSGPRs = getNumExtraSGPRs(STM,
801                                          ProgInfo.VCCUsed,
802                                          ProgInfo.FlatUsed);
803   unsigned ExtraVGPRs = STM.getReservedNumVGPRs(MF);
804 
805   // Check the addressable register limit before we add ExtraSGPRs.
806   if (STM.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
807       !STM.hasSGPRInitBug()) {
808     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
809     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
810       // This can happen due to a compiler bug or when using inline asm.
811       LLVMContext &Ctx = MF.getFunction()->getContext();
812       DiagnosticInfoResourceLimit Diag(*MF.getFunction(),
813                                        "addressable scalar registers",
814                                        ProgInfo.NumSGPR, DS_Error,
815                                        DK_ResourceLimit,
816                                        MaxAddressableNumSGPRs);
817       Ctx.diagnose(Diag);
818       ProgInfo.NumSGPR = MaxAddressableNumSGPRs - 1;
819     }
820   }
821 
822   // Account for extra SGPRs and VGPRs reserved for debugger use.
823   ProgInfo.NumSGPR += ExtraSGPRs;
824   ProgInfo.NumVGPR += ExtraVGPRs;
825 
826   // Adjust number of registers used to meet default/requested minimum/maximum
827   // number of waves per execution unit request.
828   ProgInfo.NumSGPRsForWavesPerEU = std::max(
829     std::max(ProgInfo.NumSGPR, 1u), STM.getMinNumSGPRs(MFI->getMaxWavesPerEU()));
830   ProgInfo.NumVGPRsForWavesPerEU = std::max(
831     std::max(ProgInfo.NumVGPR, 1u), STM.getMinNumVGPRs(MFI->getMaxWavesPerEU()));
832 
833   if (STM.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ||
834       STM.hasSGPRInitBug()) {
835     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
836     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
837       // This can happen due to a compiler bug or when using inline asm to use
838       // the registers which are usually reserved for vcc etc.
839       LLVMContext &Ctx = MF.getFunction()->getContext();
840       DiagnosticInfoResourceLimit Diag(*MF.getFunction(),
841                                        "scalar registers",
842                                        ProgInfo.NumSGPR, DS_Error,
843                                        DK_ResourceLimit,
844                                        MaxAddressableNumSGPRs);
845       Ctx.diagnose(Diag);
846       ProgInfo.NumSGPR = MaxAddressableNumSGPRs;
847       ProgInfo.NumSGPRsForWavesPerEU = MaxAddressableNumSGPRs;
848     }
849   }
850 
851   if (STM.hasSGPRInitBug()) {
852     ProgInfo.NumSGPR =
853         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
854     ProgInfo.NumSGPRsForWavesPerEU =
855         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
856   }
857 
858   if (MFI->getNumUserSGPRs() > STM.getMaxNumUserSGPRs()) {
859     LLVMContext &Ctx = MF.getFunction()->getContext();
860     DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "user SGPRs",
861                                      MFI->getNumUserSGPRs(), DS_Error);
862     Ctx.diagnose(Diag);
863   }
864 
865   if (MFI->getLDSSize() > static_cast<unsigned>(STM.getLocalMemorySize())) {
866     LLVMContext &Ctx = MF.getFunction()->getContext();
867     DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "local memory",
868                                      MFI->getLDSSize(), DS_Error);
869     Ctx.diagnose(Diag);
870   }
871 
872   // SGPRBlocks is actual number of SGPR blocks minus 1.
873   ProgInfo.SGPRBlocks = alignTo(ProgInfo.NumSGPRsForWavesPerEU,
874                                 STM.getSGPREncodingGranule());
875   ProgInfo.SGPRBlocks = ProgInfo.SGPRBlocks / STM.getSGPREncodingGranule() - 1;
876 
877   // VGPRBlocks is actual number of VGPR blocks minus 1.
878   ProgInfo.VGPRBlocks = alignTo(ProgInfo.NumVGPRsForWavesPerEU,
879                                 STM.getVGPREncodingGranule());
880   ProgInfo.VGPRBlocks = ProgInfo.VGPRBlocks / STM.getVGPREncodingGranule() - 1;
881 
882   // Record first reserved VGPR and number of reserved VGPRs.
883   ProgInfo.ReservedVGPRFirst = STM.debuggerReserveRegs() ? ProgInfo.NumVGPR : 0;
884   ProgInfo.ReservedVGPRCount = STM.getReservedNumVGPRs(MF);
885 
886   // Update DebuggerWavefrontPrivateSegmentOffsetSGPR and
887   // DebuggerPrivateSegmentBufferSGPR fields if "amdgpu-debugger-emit-prologue"
888   // attribute was requested.
889   if (STM.debuggerEmitPrologue()) {
890     ProgInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR =
891       RI->getHWRegIndex(MFI->getScratchWaveOffsetReg());
892     ProgInfo.DebuggerPrivateSegmentBufferSGPR =
893       RI->getHWRegIndex(MFI->getScratchRSrcReg());
894   }
895 
896   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
897   // register.
898   ProgInfo.FloatMode = getFPMode(MF);
899 
900   ProgInfo.IEEEMode = STM.enableIEEEBit(MF);
901 
902   // Make clamp modifier on NaN input returns 0.
903   ProgInfo.DX10Clamp = STM.enableDX10Clamp();
904 
905   unsigned LDSAlignShift;
906   if (STM.getGeneration() < SISubtarget::SEA_ISLANDS) {
907     // LDS is allocated in 64 dword blocks.
908     LDSAlignShift = 8;
909   } else {
910     // LDS is allocated in 128 dword blocks.
911     LDSAlignShift = 9;
912   }
913 
914   unsigned LDSSpillSize =
915     MFI->getLDSWaveSpillSize() * MFI->getMaxFlatWorkGroupSize();
916 
917   ProgInfo.LDSSize = MFI->getLDSSize() + LDSSpillSize;
918   ProgInfo.LDSBlocks =
919       alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
920 
921   // Scratch is allocated in 256 dword blocks.
922   unsigned ScratchAlignShift = 10;
923   // We need to program the hardware with the amount of scratch memory that
924   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
925   // scratch memory used per thread.
926   ProgInfo.ScratchBlocks =
927       alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
928               1ULL << ScratchAlignShift) >>
929       ScratchAlignShift;
930 
931   ProgInfo.ComputePGMRSrc1 =
932       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
933       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
934       S_00B848_PRIORITY(ProgInfo.Priority) |
935       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
936       S_00B848_PRIV(ProgInfo.Priv) |
937       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
938       S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
939       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
940 
941   // 0 = X, 1 = XY, 2 = XYZ
942   unsigned TIDIGCompCnt = 0;
943   if (MFI->hasWorkItemIDZ())
944     TIDIGCompCnt = 2;
945   else if (MFI->hasWorkItemIDY())
946     TIDIGCompCnt = 1;
947 
948   ProgInfo.ComputePGMRSrc2 =
949       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
950       S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
951       S_00B84C_TRAP_HANDLER(STM.isTrapHandlerEnabled()) |
952       S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
953       S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
954       S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
955       S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
956       S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
957       S_00B84C_EXCP_EN_MSB(0) |
958       // For AMDHSA, LDS_SIZE must be zero, as it is populated by the CP.
959       S_00B84C_LDS_SIZE(STM.isAmdHsaOS() ? 0 : ProgInfo.LDSBlocks) |
960       S_00B84C_EXCP_EN(0);
961 }
962 
963 static unsigned getRsrcReg(CallingConv::ID CallConv) {
964   switch (CallConv) {
965   default: LLVM_FALLTHROUGH;
966   case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
967   case CallingConv::AMDGPU_LS: return R_00B528_SPI_SHADER_PGM_RSRC1_LS;
968   case CallingConv::AMDGPU_HS: return R_00B428_SPI_SHADER_PGM_RSRC1_HS;
969   case CallingConv::AMDGPU_ES: return R_00B328_SPI_SHADER_PGM_RSRC1_ES;
970   case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
971   case CallingConv::AMDGPU_VS: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
972   case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
973   }
974 }
975 
976 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
977                                          const SIProgramInfo &CurrentProgramInfo) {
978   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
979   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
980   unsigned RsrcReg = getRsrcReg(MF.getFunction()->getCallingConv());
981 
982   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
983     OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
984 
985     OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc1, 4);
986 
987     OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
988     OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc2, 4);
989 
990     OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
991     OutStreamer->EmitIntValue(S_00B860_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
992 
993     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
994     // 0" comment but I don't see a corresponding field in the register spec.
995   } else {
996     OutStreamer->EmitIntValue(RsrcReg, 4);
997     OutStreamer->EmitIntValue(S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
998                               S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks), 4);
999     unsigned Rsrc2Val = 0;
1000     if (STM.isVGPRSpillingEnabled(*MF.getFunction())) {
1001       OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
1002       OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
1003       if (TM.getTargetTriple().getOS() == Triple::AMDPAL)
1004         Rsrc2Val = S_00B84C_SCRATCH_EN(CurrentProgramInfo.ScratchBlocks > 0);
1005     }
1006     if (MF.getFunction()->getCallingConv() == CallingConv::AMDGPU_PS) {
1007       OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
1008       OutStreamer->EmitIntValue(MFI->getPSInputEnable(), 4);
1009       OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
1010       OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4);
1011       Rsrc2Val |= S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks);
1012     }
1013     if (Rsrc2Val) {
1014       OutStreamer->EmitIntValue(RsrcReg + 4 /*rsrc2*/, 4);
1015       OutStreamer->EmitIntValue(Rsrc2Val, 4);
1016     }
1017   }
1018 
1019   OutStreamer->EmitIntValue(R_SPILLED_SGPRS, 4);
1020   OutStreamer->EmitIntValue(MFI->getNumSpilledSGPRs(), 4);
1021   OutStreamer->EmitIntValue(R_SPILLED_VGPRS, 4);
1022   OutStreamer->EmitIntValue(MFI->getNumSpilledVGPRs(), 4);
1023 }
1024 
1025 // This is the equivalent of EmitProgramInfoSI above, but for when the OS type
1026 // is AMDPAL.  It stores each compute/SPI register setting and other PAL
1027 // metadata items into the PALMetadataMap, combining with any provided by the
1028 // frontend as LLVM metadata. Once all functions are written, PALMetadataMap is
1029 // then written as a single block in the .note section.
1030 void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
1031        const SIProgramInfo &CurrentProgramInfo) {
1032   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1033   // Given the calling convention, calculate the register number for rsrc1. In
1034   // principle the register number could change in future hardware, but we know
1035   // it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so
1036   // we can use the same fixed value that .AMDGPU.config has for Mesa. Note
1037   // that we use a register number rather than a byte offset, so we need to
1038   // divide by 4.
1039   unsigned Rsrc1Reg = getRsrcReg(MF.getFunction()->getCallingConv()) / 4;
1040   unsigned Rsrc2Reg = Rsrc1Reg + 1;
1041   // Also calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used
1042   // with a constant offset to access any non-register shader-specific PAL
1043   // metadata key.
1044   unsigned ScratchSizeKey = PALMD::Key::CS_SCRATCH_SIZE;
1045   switch (MF.getFunction()->getCallingConv()) {
1046     case CallingConv::AMDGPU_PS:
1047       ScratchSizeKey = PALMD::Key::PS_SCRATCH_SIZE;
1048       break;
1049     case CallingConv::AMDGPU_VS:
1050       ScratchSizeKey = PALMD::Key::VS_SCRATCH_SIZE;
1051       break;
1052     case CallingConv::AMDGPU_GS:
1053       ScratchSizeKey = PALMD::Key::GS_SCRATCH_SIZE;
1054       break;
1055     case CallingConv::AMDGPU_ES:
1056       ScratchSizeKey = PALMD::Key::ES_SCRATCH_SIZE;
1057       break;
1058     case CallingConv::AMDGPU_HS:
1059       ScratchSizeKey = PALMD::Key::HS_SCRATCH_SIZE;
1060       break;
1061     case CallingConv::AMDGPU_LS:
1062       ScratchSizeKey = PALMD::Key::LS_SCRATCH_SIZE;
1063       break;
1064   }
1065   unsigned NumUsedVgprsKey = ScratchSizeKey +
1066       PALMD::Key::VS_NUM_USED_VGPRS - PALMD::Key::VS_SCRATCH_SIZE;
1067   unsigned NumUsedSgprsKey = ScratchSizeKey +
1068       PALMD::Key::VS_NUM_USED_SGPRS - PALMD::Key::VS_SCRATCH_SIZE;
1069   PALMetadataMap[NumUsedVgprsKey] = CurrentProgramInfo.NumVGPRsForWavesPerEU;
1070   PALMetadataMap[NumUsedSgprsKey] = CurrentProgramInfo.NumSGPRsForWavesPerEU;
1071   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
1072     PALMetadataMap[Rsrc1Reg] |= CurrentProgramInfo.ComputePGMRSrc1;
1073     PALMetadataMap[Rsrc2Reg] |= CurrentProgramInfo.ComputePGMRSrc2;
1074     // ScratchSize is in bytes, 16 aligned.
1075     PALMetadataMap[ScratchSizeKey] |=
1076         alignTo(CurrentProgramInfo.ScratchSize, 16);
1077   } else {
1078     PALMetadataMap[Rsrc1Reg] |= S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
1079         S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks);
1080     if (CurrentProgramInfo.ScratchBlocks > 0)
1081       PALMetadataMap[Rsrc2Reg] |= S_00B84C_SCRATCH_EN(1);
1082     // ScratchSize is in bytes, 16 aligned.
1083     PALMetadataMap[ScratchSizeKey] |=
1084         alignTo(CurrentProgramInfo.ScratchSize, 16);
1085   }
1086   if (MF.getFunction()->getCallingConv() == CallingConv::AMDGPU_PS) {
1087     PALMetadataMap[Rsrc2Reg] |=
1088         S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks);
1089     PALMetadataMap[R_0286CC_SPI_PS_INPUT_ENA / 4] |= MFI->getPSInputEnable();
1090     PALMetadataMap[R_0286D0_SPI_PS_INPUT_ADDR / 4] |= MFI->getPSInputAddr();
1091   }
1092 }
1093 
1094 // This is supposed to be log2(Size)
1095 static amd_element_byte_size_t getElementByteSizeValue(unsigned Size) {
1096   switch (Size) {
1097   case 4:
1098     return AMD_ELEMENT_4_BYTES;
1099   case 8:
1100     return AMD_ELEMENT_8_BYTES;
1101   case 16:
1102     return AMD_ELEMENT_16_BYTES;
1103   default:
1104     llvm_unreachable("invalid private_element_size");
1105   }
1106 }
1107 
1108 void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out,
1109                                         const SIProgramInfo &CurrentProgramInfo,
1110                                         const MachineFunction &MF) const {
1111   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1112   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
1113 
1114   AMDGPU::initDefaultAMDKernelCodeT(Out, STM.getFeatureBits());
1115 
1116   Out.compute_pgm_resource_registers =
1117       CurrentProgramInfo.ComputePGMRSrc1 |
1118       (CurrentProgramInfo.ComputePGMRSrc2 << 32);
1119   Out.code_properties = AMD_CODE_PROPERTY_IS_PTR64;
1120 
1121   if (CurrentProgramInfo.DynamicCallStack)
1122     Out.code_properties |= AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK;
1123 
1124   AMD_HSA_BITS_SET(Out.code_properties,
1125                    AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE,
1126                    getElementByteSizeValue(STM.getMaxPrivateElementSize()));
1127 
1128   if (MFI->hasPrivateSegmentBuffer()) {
1129     Out.code_properties |=
1130       AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
1131   }
1132 
1133   if (MFI->hasDispatchPtr())
1134     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
1135 
1136   if (MFI->hasQueuePtr())
1137     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
1138 
1139   if (MFI->hasKernargSegmentPtr())
1140     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
1141 
1142   if (MFI->hasDispatchID())
1143     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
1144 
1145   if (MFI->hasFlatScratchInit())
1146     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
1147 
1148   if (MFI->hasGridWorkgroupCountX()) {
1149     Out.code_properties |=
1150       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X;
1151   }
1152 
1153   if (MFI->hasGridWorkgroupCountY()) {
1154     Out.code_properties |=
1155       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y;
1156   }
1157 
1158   if (MFI->hasGridWorkgroupCountZ()) {
1159     Out.code_properties |=
1160       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z;
1161   }
1162 
1163   if (MFI->hasDispatchPtr())
1164     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
1165 
1166   if (STM.debuggerSupported())
1167     Out.code_properties |= AMD_CODE_PROPERTY_IS_DEBUG_SUPPORTED;
1168 
1169   if (STM.isXNACKEnabled())
1170     Out.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED;
1171 
1172   // FIXME: Should use getKernArgSize
1173   Out.kernarg_segment_byte_size =
1174     STM.getKernArgSegmentSize(MF, MFI->getABIArgOffset());
1175   Out.wavefront_sgpr_count = CurrentProgramInfo.NumSGPR;
1176   Out.workitem_vgpr_count = CurrentProgramInfo.NumVGPR;
1177   Out.workitem_private_segment_byte_size = CurrentProgramInfo.ScratchSize;
1178   Out.workgroup_group_segment_byte_size = CurrentProgramInfo.LDSSize;
1179   Out.reserved_vgpr_first = CurrentProgramInfo.ReservedVGPRFirst;
1180   Out.reserved_vgpr_count = CurrentProgramInfo.ReservedVGPRCount;
1181 
1182   // These alignment values are specified in powers of two, so alignment =
1183   // 2^n.  The minimum alignment is 2^4 = 16.
1184   Out.kernarg_segment_alignment = std::max((size_t)4,
1185       countTrailingZeros(MFI->getMaxKernArgAlign()));
1186 
1187   if (STM.debuggerEmitPrologue()) {
1188     Out.debug_wavefront_private_segment_offset_sgpr =
1189       CurrentProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR;
1190     Out.debug_private_segment_buffer_sgpr =
1191       CurrentProgramInfo.DebuggerPrivateSegmentBufferSGPR;
1192   }
1193 }
1194 
1195 AMDGPU::HSAMD::Kernel::CodeProps::Metadata AMDGPUAsmPrinter::getHSACodeProps(
1196     const MachineFunction &MF,
1197     const SIProgramInfo &ProgramInfo) const {
1198   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
1199   const SIMachineFunctionInfo &MFI = *MF.getInfo<SIMachineFunctionInfo>();
1200   HSAMD::Kernel::CodeProps::Metadata HSACodeProps;
1201 
1202   HSACodeProps.mKernargSegmentSize =
1203       STM.getKernArgSegmentSize(MF, MFI.getABIArgOffset());
1204   HSACodeProps.mGroupSegmentFixedSize = ProgramInfo.LDSSize;
1205   HSACodeProps.mPrivateSegmentFixedSize = ProgramInfo.ScratchSize;
1206   HSACodeProps.mKernargSegmentAlign =
1207       std::max(uint32_t(4), MFI.getMaxKernArgAlign());
1208   HSACodeProps.mWavefrontSize = STM.getWavefrontSize();
1209   HSACodeProps.mNumSGPRs = CurrentProgramInfo.NumSGPR;
1210   HSACodeProps.mNumVGPRs = CurrentProgramInfo.NumVGPR;
1211   HSACodeProps.mMaxFlatWorkGroupSize = MFI.getMaxFlatWorkGroupSize();
1212   HSACodeProps.mIsDynamicCallStack = ProgramInfo.DynamicCallStack;
1213   HSACodeProps.mIsXNACKEnabled = STM.isXNACKEnabled();
1214   HSACodeProps.mNumSpilledSGPRs = MFI.getNumSpilledSGPRs();
1215   HSACodeProps.mNumSpilledVGPRs = MFI.getNumSpilledVGPRs();
1216 
1217   return HSACodeProps;
1218 }
1219 
1220 AMDGPU::HSAMD::Kernel::DebugProps::Metadata AMDGPUAsmPrinter::getHSADebugProps(
1221     const MachineFunction &MF,
1222     const SIProgramInfo &ProgramInfo) const {
1223   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
1224   HSAMD::Kernel::DebugProps::Metadata HSADebugProps;
1225 
1226   if (!STM.debuggerSupported())
1227     return HSADebugProps;
1228 
1229   HSADebugProps.mDebuggerABIVersion.push_back(1);
1230   HSADebugProps.mDebuggerABIVersion.push_back(0);
1231   HSADebugProps.mReservedNumVGPRs = ProgramInfo.ReservedVGPRCount;
1232   HSADebugProps.mReservedFirstVGPR = ProgramInfo.ReservedVGPRFirst;
1233 
1234   if (STM.debuggerEmitPrologue()) {
1235     HSADebugProps.mPrivateSegmentBufferSGPR =
1236         ProgramInfo.DebuggerPrivateSegmentBufferSGPR;
1237     HSADebugProps.mWavefrontPrivateSegmentOffsetSGPR =
1238         ProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR;
1239   }
1240 
1241   return HSADebugProps;
1242 }
1243 
1244 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
1245                                        unsigned AsmVariant,
1246                                        const char *ExtraCode, raw_ostream &O) {
1247   // First try the generic code, which knows about modifiers like 'c' and 'n'.
1248   if (!AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O))
1249     return false;
1250 
1251   if (ExtraCode && ExtraCode[0]) {
1252     if (ExtraCode[1] != 0)
1253       return true; // Unknown modifier.
1254 
1255     switch (ExtraCode[0]) {
1256     case 'r':
1257       break;
1258     default:
1259       return true;
1260     }
1261   }
1262 
1263   // TODO: Should be able to support other operand types like globals.
1264   const MachineOperand &MO = MI->getOperand(OpNo);
1265   if (MO.isReg()) {
1266     AMDGPUInstPrinter::printRegOperand(MO.getReg(), O,
1267                                        *MF->getSubtarget().getRegisterInfo());
1268     return false;
1269   }
1270 
1271   return true;
1272 }
1273