1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
15 //
16 //===----------------------------------------------------------------------===//
17 //
18 
19 #include "AMDGPUAsmPrinter.h"
20 #include "AMDGPUTargetMachine.h"
21 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
22 #include "InstPrinter/AMDGPUInstPrinter.h"
23 #include "Utils/AMDGPUBaseInfo.h"
24 #include "AMDGPU.h"
25 #include "AMDGPUSubtarget.h"
26 #include "R600Defines.h"
27 #include "R600MachineFunctionInfo.h"
28 #include "R600RegisterInfo.h"
29 #include "SIDefines.h"
30 #include "SIMachineFunctionInfo.h"
31 #include "SIInstrInfo.h"
32 #include "SIRegisterInfo.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/IR/DiagnosticInfo.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCSectionELF.h"
37 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/Support/ELF.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Target/TargetLoweringObjectFile.h"
42 
43 using namespace llvm;
44 
45 // TODO: This should get the default rounding mode from the kernel. We just set
46 // the default here, but this could change if the OpenCL rounding mode pragmas
47 // are used.
48 //
49 // The denormal mode here should match what is reported by the OpenCL runtime
50 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
51 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
52 //
53 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
54 // precision, and leaves single precision to flush all and does not report
55 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
56 // CL_FP_DENORM for both.
57 //
58 // FIXME: It seems some instructions do not support single precision denormals
59 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
60 // and sin_f32, cos_f32 on most parts).
61 
62 // We want to use these instructions, and using fp32 denormals also causes
63 // instructions to run at the double precision rate for the device so it's
64 // probably best to just report no single precision denormals.
65 static uint32_t getFPMode(const MachineFunction &F) {
66   const SISubtarget& ST = F.getSubtarget<SISubtarget>();
67   // TODO: Is there any real use for the flush in only / flush out only modes?
68 
69   uint32_t FP32Denormals =
70     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
71 
72   uint32_t FP64Denormals =
73     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
74 
75   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
76          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
77          FP_DENORM_MODE_SP(FP32Denormals) |
78          FP_DENORM_MODE_DP(FP64Denormals);
79 }
80 
81 static AsmPrinter *
82 createAMDGPUAsmPrinterPass(TargetMachine &tm,
83                            std::unique_ptr<MCStreamer> &&Streamer) {
84   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
85 }
86 
87 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
88   TargetRegistry::RegisterAsmPrinter(getTheAMDGPUTarget(),
89                                      createAMDGPUAsmPrinterPass);
90   TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(),
91                                      createAMDGPUAsmPrinterPass);
92 }
93 
94 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
95                                    std::unique_ptr<MCStreamer> Streamer)
96   : AsmPrinter(TM, std::move(Streamer)) {
97     AMDGPUASI = static_cast<AMDGPUTargetMachine*>(&TM)->getAMDGPUAS();
98   }
99 
100 StringRef AMDGPUAsmPrinter::getPassName() const {
101   return "AMDGPU Assembly Printer";
102 }
103 
104 const MCSubtargetInfo* AMDGPUAsmPrinter::getSTI() const {
105   return TM.getMCSubtargetInfo();
106 }
107 
108 AMDGPUTargetStreamer& AMDGPUAsmPrinter::getTargetStreamer() const {
109   return static_cast<AMDGPUTargetStreamer&>(*OutStreamer->getTargetStreamer());
110 }
111 
112 void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) {
113   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
114     return;
115 
116   AMDGPU::IsaInfo::IsaVersion ISA =
117       AMDGPU::IsaInfo::getIsaVersion(getSTI()->getFeatureBits());
118 
119   getTargetStreamer().EmitDirectiveHSACodeObjectVersion(2, 1);
120   getTargetStreamer().EmitDirectiveHSACodeObjectISA(
121       ISA.Major, ISA.Minor, ISA.Stepping, "AMD", "AMDGPU");
122   getTargetStreamer().EmitStartOfCodeObjectMetadata(M);
123 }
124 
125 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
126   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
127     return;
128 
129   getTargetStreamer().EmitEndOfCodeObjectMetadata();
130 }
131 
132 bool AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough(
133   const MachineBasicBlock *MBB) const {
134   if (!AsmPrinter::isBlockOnlyReachableByFallthrough(MBB))
135     return false;
136 
137   if (MBB->empty())
138     return true;
139 
140   // If this is a block implementing a long branch, an expression relative to
141   // the start of the block is needed.  to the start of the block.
142   // XXX - Is there a smarter way to check this?
143   return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
144 }
145 
146 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
147   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
148   SIProgramInfo KernelInfo;
149   amd_kernel_code_t KernelCode;
150   if (STM.isAmdCodeObjectV2(*MF)) {
151     getSIProgramInfo(KernelInfo, *MF);
152     getAmdKernelCode(KernelCode, KernelInfo, *MF);
153 
154     OutStreamer->SwitchSection(getObjFileLowering().getTextSection());
155     getTargetStreamer().EmitAMDKernelCodeT(KernelCode);
156   }
157 
158   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
159     return;
160   getTargetStreamer().EmitKernelCodeObjectMetadata(*MF->getFunction(),
161                                                    KernelCode);
162 }
163 
164 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
165   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
166   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
167   if (MFI->isEntryFunction() && STM.isAmdCodeObjectV2(*MF)) {
168     SmallString<128> SymbolName;
169     getNameWithPrefix(SymbolName, MF->getFunction()),
170     getTargetStreamer().EmitAMDGPUSymbolType(
171         SymbolName, ELF::STT_AMDGPU_HSA_KERNEL);
172   }
173 
174   AsmPrinter::EmitFunctionEntryLabel();
175 }
176 
177 void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
178 
179   // Group segment variables aren't emitted in HSA.
180   if (AMDGPU::isGroupSegment(GV, AMDGPUASI))
181     return;
182 
183   AsmPrinter::EmitGlobalVariable(GV);
184 }
185 
186 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
187 
188   // The starting address of all shader programs must be 256 bytes aligned.
189   MF.setAlignment(8);
190 
191   SetupMachineFunction(MF);
192 
193   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
194   MCContext &Context = getObjFileLowering().getContext();
195   if (!STM.isAmdHsaOS()) {
196     MCSectionELF *ConfigSection =
197         Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
198     OutStreamer->SwitchSection(ConfigSection);
199   }
200 
201   SIProgramInfo KernelInfo;
202   if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
203     getSIProgramInfo(KernelInfo, MF);
204     if (!STM.isAmdHsaOS()) {
205       EmitProgramInfoSI(MF, KernelInfo);
206     }
207   } else {
208     EmitProgramInfoR600(MF);
209   }
210 
211   DisasmLines.clear();
212   HexLines.clear();
213   DisasmLineMaxLen = 0;
214 
215   EmitFunctionBody();
216 
217   if (isVerbose()) {
218     MCSectionELF *CommentSection =
219         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
220     OutStreamer->SwitchSection(CommentSection);
221 
222     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
223       OutStreamer->emitRawComment(" Kernel info:", false);
224       OutStreamer->emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
225                                   false);
226       OutStreamer->emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
227                                   false);
228       OutStreamer->emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
229                                   false);
230       OutStreamer->emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
231                                   false);
232       OutStreamer->emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
233                                   false);
234       OutStreamer->emitRawComment(" ScratchSize: " + Twine(KernelInfo.ScratchSize),
235                                   false);
236       OutStreamer->emitRawComment(" LDSByteSize: " + Twine(KernelInfo.LDSSize) +
237                                   " bytes/workgroup (compile time only)", false);
238 
239       OutStreamer->emitRawComment(" SGPRBlocks: " +
240                                   Twine(KernelInfo.SGPRBlocks), false);
241       OutStreamer->emitRawComment(" VGPRBlocks: " +
242                                   Twine(KernelInfo.VGPRBlocks), false);
243 
244       OutStreamer->emitRawComment(" NumSGPRsForWavesPerEU: " +
245                                   Twine(KernelInfo.NumSGPRsForWavesPerEU), false);
246       OutStreamer->emitRawComment(" NumVGPRsForWavesPerEU: " +
247                                   Twine(KernelInfo.NumVGPRsForWavesPerEU), false);
248 
249       OutStreamer->emitRawComment(" ReservedVGPRFirst: " + Twine(KernelInfo.ReservedVGPRFirst),
250                                   false);
251       OutStreamer->emitRawComment(" ReservedVGPRCount: " + Twine(KernelInfo.ReservedVGPRCount),
252                                   false);
253 
254       if (MF.getSubtarget<SISubtarget>().debuggerEmitPrologue()) {
255         OutStreamer->emitRawComment(" DebuggerWavefrontPrivateSegmentOffsetSGPR: s" +
256                                     Twine(KernelInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR), false);
257         OutStreamer->emitRawComment(" DebuggerPrivateSegmentBufferSGPR: s" +
258                                     Twine(KernelInfo.DebuggerPrivateSegmentBufferSGPR), false);
259       }
260 
261       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:USER_SGPR: " +
262                                   Twine(G_00B84C_USER_SGPR(KernelInfo.ComputePGMRSrc2)),
263                                   false);
264       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
265                                   Twine(G_00B84C_TRAP_HANDLER(KernelInfo.ComputePGMRSrc2)),
266                                   false);
267       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_X_EN: " +
268                                   Twine(G_00B84C_TGID_X_EN(KernelInfo.ComputePGMRSrc2)),
269                                   false);
270       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
271                                   Twine(G_00B84C_TGID_Y_EN(KernelInfo.ComputePGMRSrc2)),
272                                   false);
273       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
274                                   Twine(G_00B84C_TGID_Z_EN(KernelInfo.ComputePGMRSrc2)),
275                                   false);
276       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
277                                   Twine(G_00B84C_TIDIG_COMP_CNT(KernelInfo.ComputePGMRSrc2)),
278                                   false);
279 
280     } else {
281       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
282       OutStreamer->emitRawComment(
283         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->CFStackSize)));
284     }
285   }
286 
287   if (STM.dumpCode()) {
288 
289     OutStreamer->SwitchSection(
290         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
291 
292     for (size_t i = 0; i < DisasmLines.size(); ++i) {
293       std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
294       Comment += " ; " + HexLines[i] + "\n";
295 
296       OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
297       OutStreamer->EmitBytes(StringRef(Comment));
298     }
299   }
300 
301   return false;
302 }
303 
304 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
305   unsigned MaxGPR = 0;
306   bool killPixel = false;
307   const R600Subtarget &STM = MF.getSubtarget<R600Subtarget>();
308   const R600RegisterInfo *RI = STM.getRegisterInfo();
309   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
310 
311   for (const MachineBasicBlock &MBB : MF) {
312     for (const MachineInstr &MI : MBB) {
313       if (MI.getOpcode() == AMDGPU::KILLGT)
314         killPixel = true;
315       unsigned numOperands = MI.getNumOperands();
316       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
317         const MachineOperand &MO = MI.getOperand(op_idx);
318         if (!MO.isReg())
319           continue;
320         unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
321 
322         // Register with value > 127 aren't GPR
323         if (HWReg > 127)
324           continue;
325         MaxGPR = std::max(MaxGPR, HWReg);
326       }
327     }
328   }
329 
330   unsigned RsrcReg;
331   if (STM.getGeneration() >= R600Subtarget::EVERGREEN) {
332     // Evergreen / Northern Islands
333     switch (MF.getFunction()->getCallingConv()) {
334     default: LLVM_FALLTHROUGH;
335     case CallingConv::AMDGPU_CS: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
336     case CallingConv::AMDGPU_GS: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
337     case CallingConv::AMDGPU_PS: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
338     case CallingConv::AMDGPU_VS: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
339     }
340   } else {
341     // R600 / R700
342     switch (MF.getFunction()->getCallingConv()) {
343     default: LLVM_FALLTHROUGH;
344     case CallingConv::AMDGPU_GS: LLVM_FALLTHROUGH;
345     case CallingConv::AMDGPU_CS: LLVM_FALLTHROUGH;
346     case CallingConv::AMDGPU_VS: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
347     case CallingConv::AMDGPU_PS: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
348     }
349   }
350 
351   OutStreamer->EmitIntValue(RsrcReg, 4);
352   OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
353                            S_STACK_SIZE(MFI->CFStackSize), 4);
354   OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
355   OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
356 
357   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
358     OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
359     OutStreamer->EmitIntValue(alignTo(MFI->getLDSSize(), 4) >> 2, 4);
360   }
361 }
362 
363 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
364                                         const MachineFunction &MF) const {
365   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
366   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
367   uint64_t CodeSize = 0;
368   unsigned MaxSGPR = 0;
369   unsigned MaxVGPR = 0;
370   bool VCCUsed = false;
371   bool FlatUsed = false;
372   const SIRegisterInfo *RI = STM.getRegisterInfo();
373   const SIInstrInfo *TII = STM.getInstrInfo();
374 
375   for (const MachineBasicBlock &MBB : MF) {
376     for (const MachineInstr &MI : MBB) {
377       // TODO: CodeSize should account for multiple functions.
378 
379       // TODO: Should we count size of debug info?
380       if (MI.isDebugValue())
381         continue;
382 
383       if (isVerbose())
384         CodeSize += TII->getInstSizeInBytes(MI);
385 
386       unsigned numOperands = MI.getNumOperands();
387       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
388         const MachineOperand &MO = MI.getOperand(op_idx);
389         unsigned width = 0;
390         bool isSGPR = false;
391 
392         if (!MO.isReg())
393           continue;
394 
395         unsigned reg = MO.getReg();
396         switch (reg) {
397         case AMDGPU::EXEC:
398         case AMDGPU::EXEC_LO:
399         case AMDGPU::EXEC_HI:
400         case AMDGPU::SCC:
401         case AMDGPU::M0:
402         case AMDGPU::SRC_SHARED_BASE:
403         case AMDGPU::SRC_SHARED_LIMIT:
404         case AMDGPU::SRC_PRIVATE_BASE:
405         case AMDGPU::SRC_PRIVATE_LIMIT:
406           continue;
407 
408         case AMDGPU::VCC:
409         case AMDGPU::VCC_LO:
410         case AMDGPU::VCC_HI:
411           VCCUsed = true;
412           continue;
413 
414         case AMDGPU::FLAT_SCR:
415         case AMDGPU::FLAT_SCR_LO:
416         case AMDGPU::FLAT_SCR_HI:
417           // Even if FLAT_SCRATCH is implicitly used, it has no effect if flat
418           // instructions aren't used to access the scratch buffer.
419           if (MFI->hasFlatScratchInit())
420             FlatUsed = true;
421           continue;
422 
423         case AMDGPU::TBA:
424         case AMDGPU::TBA_LO:
425         case AMDGPU::TBA_HI:
426         case AMDGPU::TMA:
427         case AMDGPU::TMA_LO:
428         case AMDGPU::TMA_HI:
429           llvm_unreachable("trap handler registers should not be used");
430 
431         default:
432           break;
433         }
434 
435         if (AMDGPU::SReg_32RegClass.contains(reg)) {
436           assert(!AMDGPU::TTMP_32RegClass.contains(reg) &&
437                  "trap handler registers should not be used");
438           isSGPR = true;
439           width = 1;
440         } else if (AMDGPU::VGPR_32RegClass.contains(reg)) {
441           isSGPR = false;
442           width = 1;
443         } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
444           assert(!AMDGPU::TTMP_64RegClass.contains(reg) &&
445                  "trap handler registers should not be used");
446           isSGPR = true;
447           width = 2;
448         } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
449           isSGPR = false;
450           width = 2;
451         } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
452           isSGPR = false;
453           width = 3;
454         } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
455           isSGPR = true;
456           width = 4;
457         } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
458           isSGPR = false;
459           width = 4;
460         } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
461           isSGPR = true;
462           width = 8;
463         } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
464           isSGPR = false;
465           width = 8;
466         } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
467           isSGPR = true;
468           width = 16;
469         } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
470           isSGPR = false;
471           width = 16;
472         } else {
473           llvm_unreachable("Unknown register class");
474         }
475         unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
476         unsigned maxUsed = hwReg + width - 1;
477         if (isSGPR) {
478           MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
479         } else {
480           MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
481         }
482       }
483     }
484   }
485 
486   unsigned ExtraSGPRs = 0;
487 
488   if (VCCUsed)
489     ExtraSGPRs = 2;
490 
491   if (STM.getGeneration() < SISubtarget::VOLCANIC_ISLANDS) {
492     if (FlatUsed)
493       ExtraSGPRs = 4;
494   } else {
495     if (STM.isXNACKEnabled())
496       ExtraSGPRs = 4;
497 
498     if (FlatUsed)
499       ExtraSGPRs = 6;
500   }
501 
502   unsigned ExtraVGPRs = STM.getReservedNumVGPRs(MF);
503 
504   // Check the addressable register limit before we add ExtraSGPRs.
505   if (STM.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
506       !STM.hasSGPRInitBug()) {
507     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
508     if (MaxSGPR + 1 > MaxAddressableNumSGPRs) {
509       // This can happen due to a compiler bug or when using inline asm.
510       LLVMContext &Ctx = MF.getFunction()->getContext();
511       DiagnosticInfoResourceLimit Diag(*MF.getFunction(),
512                                        "addressable scalar registers",
513                                        MaxSGPR + 1, DS_Error,
514                                        DK_ResourceLimit,
515                                        MaxAddressableNumSGPRs);
516       Ctx.diagnose(Diag);
517       MaxSGPR = MaxAddressableNumSGPRs - 1;
518     }
519   }
520 
521   // Account for extra SGPRs and VGPRs reserved for debugger use.
522   MaxSGPR += ExtraSGPRs;
523   MaxVGPR += ExtraVGPRs;
524 
525   // We found the maximum register index. They start at 0, so add one to get the
526   // number of registers.
527   ProgInfo.NumSGPR = MaxSGPR + 1;
528   ProgInfo.NumVGPR = MaxVGPR + 1;
529 
530   // Adjust number of registers used to meet default/requested minimum/maximum
531   // number of waves per execution unit request.
532   ProgInfo.NumSGPRsForWavesPerEU = std::max(
533     ProgInfo.NumSGPR, STM.getMinNumSGPRs(MFI->getMaxWavesPerEU()));
534   ProgInfo.NumVGPRsForWavesPerEU = std::max(
535     ProgInfo.NumVGPR, STM.getMinNumVGPRs(MFI->getMaxWavesPerEU()));
536 
537   if (STM.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ||
538       STM.hasSGPRInitBug()) {
539     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
540     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
541       // This can happen due to a compiler bug or when using inline asm to use
542       // the registers which are usually reserved for vcc etc.
543       LLVMContext &Ctx = MF.getFunction()->getContext();
544       DiagnosticInfoResourceLimit Diag(*MF.getFunction(),
545                                        "scalar registers",
546                                        ProgInfo.NumSGPR, DS_Error,
547                                        DK_ResourceLimit,
548                                        MaxAddressableNumSGPRs);
549       Ctx.diagnose(Diag);
550       ProgInfo.NumSGPR = MaxAddressableNumSGPRs;
551       ProgInfo.NumSGPRsForWavesPerEU = MaxAddressableNumSGPRs;
552     }
553   }
554 
555   if (STM.hasSGPRInitBug()) {
556     ProgInfo.NumSGPR =
557         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
558     ProgInfo.NumSGPRsForWavesPerEU =
559         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
560   }
561 
562   if (MFI->NumUserSGPRs > STM.getMaxNumUserSGPRs()) {
563     LLVMContext &Ctx = MF.getFunction()->getContext();
564     DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "user SGPRs",
565                                      MFI->NumUserSGPRs, DS_Error);
566     Ctx.diagnose(Diag);
567   }
568 
569   if (MFI->getLDSSize() > static_cast<unsigned>(STM.getLocalMemorySize())) {
570     LLVMContext &Ctx = MF.getFunction()->getContext();
571     DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "local memory",
572                                      MFI->getLDSSize(), DS_Error);
573     Ctx.diagnose(Diag);
574   }
575 
576   // SGPRBlocks is actual number of SGPR blocks minus 1.
577   ProgInfo.SGPRBlocks = alignTo(ProgInfo.NumSGPRsForWavesPerEU,
578                                 STM.getSGPREncodingGranule());
579   ProgInfo.SGPRBlocks = ProgInfo.SGPRBlocks / STM.getSGPREncodingGranule() - 1;
580 
581   // VGPRBlocks is actual number of VGPR blocks minus 1.
582   ProgInfo.VGPRBlocks = alignTo(ProgInfo.NumVGPRsForWavesPerEU,
583                                 STM.getVGPREncodingGranule());
584   ProgInfo.VGPRBlocks = ProgInfo.VGPRBlocks / STM.getVGPREncodingGranule() - 1;
585 
586   // Record first reserved VGPR and number of reserved VGPRs.
587   ProgInfo.ReservedVGPRFirst = STM.debuggerReserveRegs() ? MaxVGPR + 1 : 0;
588   ProgInfo.ReservedVGPRCount = STM.getReservedNumVGPRs(MF);
589 
590   // Update DebuggerWavefrontPrivateSegmentOffsetSGPR and
591   // DebuggerPrivateSegmentBufferSGPR fields if "amdgpu-debugger-emit-prologue"
592   // attribute was requested.
593   if (STM.debuggerEmitPrologue()) {
594     ProgInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR =
595       RI->getHWRegIndex(MFI->getScratchWaveOffsetReg());
596     ProgInfo.DebuggerPrivateSegmentBufferSGPR =
597       RI->getHWRegIndex(MFI->getScratchRSrcReg());
598   }
599 
600   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
601   // register.
602   ProgInfo.FloatMode = getFPMode(MF);
603 
604   ProgInfo.IEEEMode = STM.enableIEEEBit(MF);
605 
606   // Make clamp modifier on NaN input returns 0.
607   ProgInfo.DX10Clamp = STM.enableDX10Clamp();
608 
609   const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
610   ProgInfo.ScratchSize = FrameInfo.getStackSize();
611 
612   ProgInfo.FlatUsed = FlatUsed;
613   ProgInfo.VCCUsed = VCCUsed;
614   ProgInfo.CodeLen = CodeSize;
615 
616   unsigned LDSAlignShift;
617   if (STM.getGeneration() < SISubtarget::SEA_ISLANDS) {
618     // LDS is allocated in 64 dword blocks.
619     LDSAlignShift = 8;
620   } else {
621     // LDS is allocated in 128 dword blocks.
622     LDSAlignShift = 9;
623   }
624 
625   unsigned LDSSpillSize =
626     MFI->LDSWaveSpillSize * MFI->getMaxFlatWorkGroupSize();
627 
628   ProgInfo.LDSSize = MFI->getLDSSize() + LDSSpillSize;
629   ProgInfo.LDSBlocks =
630       alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
631 
632   // Scratch is allocated in 256 dword blocks.
633   unsigned ScratchAlignShift = 10;
634   // We need to program the hardware with the amount of scratch memory that
635   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
636   // scratch memory used per thread.
637   ProgInfo.ScratchBlocks =
638       alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
639               1ULL << ScratchAlignShift) >>
640       ScratchAlignShift;
641 
642   ProgInfo.ComputePGMRSrc1 =
643       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
644       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
645       S_00B848_PRIORITY(ProgInfo.Priority) |
646       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
647       S_00B848_PRIV(ProgInfo.Priv) |
648       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
649       S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
650       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
651 
652   // 0 = X, 1 = XY, 2 = XYZ
653   unsigned TIDIGCompCnt = 0;
654   if (MFI->hasWorkItemIDZ())
655     TIDIGCompCnt = 2;
656   else if (MFI->hasWorkItemIDY())
657     TIDIGCompCnt = 1;
658 
659   ProgInfo.ComputePGMRSrc2 =
660       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
661       S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
662       S_00B84C_TRAP_HANDLER(STM.isTrapHandlerEnabled()) |
663       S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
664       S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
665       S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
666       S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
667       S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
668       S_00B84C_EXCP_EN_MSB(0) |
669       S_00B84C_LDS_SIZE(ProgInfo.LDSBlocks) |
670       S_00B84C_EXCP_EN(0);
671 }
672 
673 static unsigned getRsrcReg(CallingConv::ID CallConv) {
674   switch (CallConv) {
675   default: LLVM_FALLTHROUGH;
676   case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
677   case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
678   case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
679   case CallingConv::AMDGPU_VS: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
680   }
681 }
682 
683 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
684                                          const SIProgramInfo &KernelInfo) {
685   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
686   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
687   unsigned RsrcReg = getRsrcReg(MF.getFunction()->getCallingConv());
688 
689   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
690     OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
691 
692     OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc1, 4);
693 
694     OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
695     OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc2, 4);
696 
697     OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
698     OutStreamer->EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4);
699 
700     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
701     // 0" comment but I don't see a corresponding field in the register spec.
702   } else {
703     OutStreamer->EmitIntValue(RsrcReg, 4);
704     OutStreamer->EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
705                               S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4);
706     if (STM.isVGPRSpillingEnabled(*MF.getFunction())) {
707       OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
708       OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(KernelInfo.ScratchBlocks), 4);
709     }
710   }
711 
712   if (MF.getFunction()->getCallingConv() == CallingConv::AMDGPU_PS) {
713     OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
714     OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4);
715     OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
716     OutStreamer->EmitIntValue(MFI->PSInputEna, 4);
717     OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
718     OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4);
719   }
720 
721   OutStreamer->EmitIntValue(R_SPILLED_SGPRS, 4);
722   OutStreamer->EmitIntValue(MFI->getNumSpilledSGPRs(), 4);
723   OutStreamer->EmitIntValue(R_SPILLED_VGPRS, 4);
724   OutStreamer->EmitIntValue(MFI->getNumSpilledVGPRs(), 4);
725 }
726 
727 // This is supposed to be log2(Size)
728 static amd_element_byte_size_t getElementByteSizeValue(unsigned Size) {
729   switch (Size) {
730   case 4:
731     return AMD_ELEMENT_4_BYTES;
732   case 8:
733     return AMD_ELEMENT_8_BYTES;
734   case 16:
735     return AMD_ELEMENT_16_BYTES;
736   default:
737     llvm_unreachable("invalid private_element_size");
738   }
739 }
740 
741 void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out,
742                                         const SIProgramInfo &KernelInfo,
743                                         const MachineFunction &MF) const {
744   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
745   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
746 
747   AMDGPU::initDefaultAMDKernelCodeT(Out, STM.getFeatureBits());
748 
749   Out.compute_pgm_resource_registers =
750       KernelInfo.ComputePGMRSrc1 |
751       (KernelInfo.ComputePGMRSrc2 << 32);
752   Out.code_properties = AMD_CODE_PROPERTY_IS_PTR64;
753 
754   AMD_HSA_BITS_SET(Out.code_properties,
755                    AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE,
756                    getElementByteSizeValue(STM.getMaxPrivateElementSize()));
757 
758   if (MFI->hasPrivateSegmentBuffer()) {
759     Out.code_properties |=
760       AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
761   }
762 
763   if (MFI->hasDispatchPtr())
764     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
765 
766   if (MFI->hasQueuePtr())
767     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
768 
769   if (MFI->hasKernargSegmentPtr())
770     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
771 
772   if (MFI->hasDispatchID())
773     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
774 
775   if (MFI->hasFlatScratchInit())
776     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
777 
778   if (MFI->hasGridWorkgroupCountX()) {
779     Out.code_properties |=
780       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X;
781   }
782 
783   if (MFI->hasGridWorkgroupCountY()) {
784     Out.code_properties |=
785       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y;
786   }
787 
788   if (MFI->hasGridWorkgroupCountZ()) {
789     Out.code_properties |=
790       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z;
791   }
792 
793   if (MFI->hasDispatchPtr())
794     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
795 
796   if (STM.debuggerSupported())
797     Out.code_properties |= AMD_CODE_PROPERTY_IS_DEBUG_SUPPORTED;
798 
799   if (STM.isXNACKEnabled())
800     Out.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED;
801 
802   // FIXME: Should use getKernArgSize
803   Out.kernarg_segment_byte_size =
804     STM.getKernArgSegmentSize(MF, MFI->getABIArgOffset());
805   Out.wavefront_sgpr_count = KernelInfo.NumSGPR;
806   Out.workitem_vgpr_count = KernelInfo.NumVGPR;
807   Out.workitem_private_segment_byte_size = KernelInfo.ScratchSize;
808   Out.workgroup_group_segment_byte_size = KernelInfo.LDSSize;
809   Out.reserved_vgpr_first = KernelInfo.ReservedVGPRFirst;
810   Out.reserved_vgpr_count = KernelInfo.ReservedVGPRCount;
811 
812   // These alignment values are specified in powers of two, so alignment =
813   // 2^n.  The minimum alignment is 2^4 = 16.
814   Out.kernarg_segment_alignment = std::max((size_t)4,
815       countTrailingZeros(MFI->getMaxKernArgAlign()));
816 
817   if (STM.debuggerEmitPrologue()) {
818     Out.debug_wavefront_private_segment_offset_sgpr =
819       KernelInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR;
820     Out.debug_private_segment_buffer_sgpr =
821       KernelInfo.DebuggerPrivateSegmentBufferSGPR;
822   }
823 }
824 
825 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
826                                        unsigned AsmVariant,
827                                        const char *ExtraCode, raw_ostream &O) {
828   if (ExtraCode && ExtraCode[0]) {
829     if (ExtraCode[1] != 0)
830       return true; // Unknown modifier.
831 
832     switch (ExtraCode[0]) {
833     default:
834       // See if this is a generic print operand
835       return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
836     case 'r':
837       break;
838     }
839   }
840 
841   AMDGPUInstPrinter::printRegOperand(MI->getOperand(OpNo).getReg(), O,
842                    *TM.getSubtargetImpl(*MF->getFunction())->getRegisterInfo());
843   return false;
844 }
845