1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
15 //
16 //===----------------------------------------------------------------------===//
17 //
18 
19 #include "AMDGPUAsmPrinter.h"
20 #include "AMDGPU.h"
21 #include "AMDGPUSubtarget.h"
22 #include "AMDGPUTargetMachine.h"
23 #include "InstPrinter/AMDGPUInstPrinter.h"
24 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
25 #include "R600Defines.h"
26 #include "R600MachineFunctionInfo.h"
27 #include "R600RegisterInfo.h"
28 #include "SIDefines.h"
29 #include "SIInstrInfo.h"
30 #include "SIMachineFunctionInfo.h"
31 #include "SIRegisterInfo.h"
32 #include "Utils/AMDGPUBaseInfo.h"
33 #include "llvm/BinaryFormat/ELF.h"
34 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/IR/DiagnosticInfo.h"
36 #include "llvm/MC/MCContext.h"
37 #include "llvm/MC/MCSectionELF.h"
38 #include "llvm/MC/MCStreamer.h"
39 #include "llvm/Support/AMDGPUMetadata.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Target/TargetLoweringObjectFile.h"
43 
44 using namespace llvm;
45 using namespace llvm::AMDGPU;
46 
47 // TODO: This should get the default rounding mode from the kernel. We just set
48 // the default here, but this could change if the OpenCL rounding mode pragmas
49 // are used.
50 //
51 // The denormal mode here should match what is reported by the OpenCL runtime
52 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
53 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
54 //
55 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
56 // precision, and leaves single precision to flush all and does not report
57 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
58 // CL_FP_DENORM for both.
59 //
60 // FIXME: It seems some instructions do not support single precision denormals
61 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
62 // and sin_f32, cos_f32 on most parts).
63 
64 // We want to use these instructions, and using fp32 denormals also causes
65 // instructions to run at the double precision rate for the device so it's
66 // probably best to just report no single precision denormals.
67 static uint32_t getFPMode(const MachineFunction &F) {
68   const SISubtarget& ST = F.getSubtarget<SISubtarget>();
69   // TODO: Is there any real use for the flush in only / flush out only modes?
70 
71   uint32_t FP32Denormals =
72     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
73 
74   uint32_t FP64Denormals =
75     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
76 
77   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
78          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
79          FP_DENORM_MODE_SP(FP32Denormals) |
80          FP_DENORM_MODE_DP(FP64Denormals);
81 }
82 
83 static AsmPrinter *
84 createAMDGPUAsmPrinterPass(TargetMachine &tm,
85                            std::unique_ptr<MCStreamer> &&Streamer) {
86   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
87 }
88 
89 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
90   TargetRegistry::RegisterAsmPrinter(getTheAMDGPUTarget(),
91                                      createAMDGPUAsmPrinterPass);
92   TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(),
93                                      createAMDGPUAsmPrinterPass);
94 }
95 
96 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
97                                    std::unique_ptr<MCStreamer> Streamer)
98   : AsmPrinter(TM, std::move(Streamer)) {
99     AMDGPUASI = static_cast<AMDGPUTargetMachine*>(&TM)->getAMDGPUAS();
100   }
101 
102 StringRef AMDGPUAsmPrinter::getPassName() const {
103   return "AMDGPU Assembly Printer";
104 }
105 
106 const MCSubtargetInfo* AMDGPUAsmPrinter::getSTI() const {
107   return TM.getMCSubtargetInfo();
108 }
109 
110 AMDGPUTargetStreamer& AMDGPUAsmPrinter::getTargetStreamer() const {
111   return static_cast<AMDGPUTargetStreamer&>(*OutStreamer->getTargetStreamer());
112 }
113 
114 void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) {
115   AMDGPU::IsaInfo::IsaVersion ISA =
116       AMDGPU::IsaInfo::getIsaVersion(getSTI()->getFeatureBits());
117 
118   if (TM.getTargetTriple().getOS() == Triple::AMDPAL) {
119     readPALMetadata(M);
120     // AMDPAL wants an HSA_ISA .note.
121     getTargetStreamer().EmitDirectiveHSACodeObjectISA(
122         ISA.Major, ISA.Minor, ISA.Stepping, "AMD", "AMDGPU");
123   }
124   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
125     return;
126 
127   getTargetStreamer().EmitDirectiveHSACodeObjectVersion(2, 1);
128   getTargetStreamer().EmitDirectiveHSACodeObjectISA(
129       ISA.Major, ISA.Minor, ISA.Stepping, "AMD", "AMDGPU");
130 
131   HSAMetadataStream.begin(M);
132 }
133 
134 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
135   if (TM.getTargetTriple().getArch() != Triple::amdgcn)
136     return;
137 
138   // Emit ISA Version (NT_AMD_AMDGPU_ISA).
139   std::string ISAVersionString;
140   raw_string_ostream ISAVersionStream(ISAVersionString);
141   IsaInfo::streamIsaVersion(getSTI(), ISAVersionStream);
142   getTargetStreamer().EmitISAVersion(ISAVersionStream.str());
143 
144   // Emit HSA Metadata (NT_AMD_AMDGPU_HSA_METADATA).
145   if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
146     HSAMetadataStream.end();
147     getTargetStreamer().EmitHSAMetadata(HSAMetadataStream.getHSAMetadata());
148   }
149 
150   // Emit PAL Metadata (NT_AMD_AMDGPU_PAL_METADATA).
151   if (TM.getTargetTriple().getOS() == Triple::AMDPAL) {
152     // Copy the PAL metadata from the map where we collected it into a vector,
153     // then write it as a .note.
154     PALMD::Metadata PALMetadataVector;
155     for (auto i : PALMetadataMap) {
156       PALMetadataVector.push_back(i.first);
157       PALMetadataVector.push_back(i.second);
158     }
159     getTargetStreamer().EmitPALMetadata(PALMetadataVector);
160   }
161 }
162 
163 bool AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough(
164   const MachineBasicBlock *MBB) const {
165   if (!AsmPrinter::isBlockOnlyReachableByFallthrough(MBB))
166     return false;
167 
168   if (MBB->empty())
169     return true;
170 
171   // If this is a block implementing a long branch, an expression relative to
172   // the start of the block is needed.  to the start of the block.
173   // XXX - Is there a smarter way to check this?
174   return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
175 }
176 
177 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
178   const AMDGPUMachineFunction *MFI = MF->getInfo<AMDGPUMachineFunction>();
179   if (!MFI->isEntryFunction())
180     return;
181 
182   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
183   amd_kernel_code_t KernelCode;
184   if (STM.isAmdCodeObjectV2(*MF)) {
185     getAmdKernelCode(KernelCode, CurrentProgramInfo, *MF);
186 
187     OutStreamer->SwitchSection(getObjFileLowering().getTextSection());
188     getTargetStreamer().EmitAMDKernelCodeT(KernelCode);
189   }
190 
191   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
192     return;
193 
194   HSAMetadataStream.emitKernel(*MF->getFunction(), KernelCode);
195 }
196 
197 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
198   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
199   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
200   if (MFI->isEntryFunction() && STM.isAmdCodeObjectV2(*MF)) {
201     SmallString<128> SymbolName;
202     getNameWithPrefix(SymbolName, MF->getFunction()),
203     getTargetStreamer().EmitAMDGPUSymbolType(
204         SymbolName, ELF::STT_AMDGPU_HSA_KERNEL);
205   }
206 
207   AsmPrinter::EmitFunctionEntryLabel();
208 }
209 
210 void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
211 
212   // Group segment variables aren't emitted in HSA.
213   if (AMDGPU::isGroupSegment(GV, AMDGPUASI))
214     return;
215 
216   AsmPrinter::EmitGlobalVariable(GV);
217 }
218 
219 bool AMDGPUAsmPrinter::doFinalization(Module &M) {
220   CallGraphResourceInfo.clear();
221   return AsmPrinter::doFinalization(M);
222 }
223 
224 // For the amdpal OS type, read the amdgpu.pal.metadata supplied by the
225 // frontend into our PALMetadataMap, ready for per-function modification.  It
226 // is a NamedMD containing an MDTuple containing a number of MDNodes each of
227 // which is an integer value, and each two integer values forms a key=value
228 // pair that we store as PALMetadataMap[key]=value in the map.
229 void AMDGPUAsmPrinter::readPALMetadata(Module &M) {
230   auto NamedMD = M.getNamedMetadata("amdgpu.pal.metadata");
231   if (!NamedMD || !NamedMD->getNumOperands())
232     return;
233   auto Tuple = dyn_cast<MDTuple>(NamedMD->getOperand(0));
234   if (!Tuple)
235     return;
236   for (unsigned I = 0, E = Tuple->getNumOperands() & -2; I != E; I += 2) {
237     auto Key = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I));
238     auto Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I + 1));
239     if (!Key || !Val)
240       continue;
241     PALMetadataMap[Key->getZExtValue()] = Val->getZExtValue();
242   }
243 }
244 
245 // Print comments that apply to both callable functions and entry points.
246 void AMDGPUAsmPrinter::emitCommonFunctionComments(
247   uint32_t NumVGPR,
248   uint32_t NumSGPR,
249   uint32_t ScratchSize,
250   uint64_t CodeSize) {
251   OutStreamer->emitRawComment(" codeLenInByte = " + Twine(CodeSize), false);
252   OutStreamer->emitRawComment(" NumSgprs: " + Twine(NumSGPR), false);
253   OutStreamer->emitRawComment(" NumVgprs: " + Twine(NumVGPR), false);
254   OutStreamer->emitRawComment(" ScratchSize: " + Twine(ScratchSize), false);
255 }
256 
257 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
258   CurrentProgramInfo = SIProgramInfo();
259 
260   const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
261 
262   // The starting address of all shader programs must be 256 bytes aligned.
263   // Regular functions just need the basic required instruction alignment.
264   MF.setAlignment(MFI->isEntryFunction() ? 8 : 2);
265 
266   SetupMachineFunction(MF);
267 
268   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
269   MCContext &Context = getObjFileLowering().getContext();
270   if (!STM.isAmdHsaOS()) {
271     MCSectionELF *ConfigSection =
272         Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
273     OutStreamer->SwitchSection(ConfigSection);
274   }
275 
276   if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
277     if (MFI->isEntryFunction()) {
278       getSIProgramInfo(CurrentProgramInfo, MF);
279     } else {
280       auto I = CallGraphResourceInfo.insert(
281         std::make_pair(MF.getFunction(), SIFunctionResourceInfo()));
282       SIFunctionResourceInfo &Info = I.first->second;
283       assert(I.second && "should only be called once per function");
284       Info = analyzeResourceUsage(MF);
285     }
286 
287     if (STM.isAmdPalOS())
288       EmitPALMetadata(MF, CurrentProgramInfo);
289     if (!STM.isAmdHsaOS()) {
290       EmitProgramInfoSI(MF, CurrentProgramInfo);
291     }
292   } else {
293     EmitProgramInfoR600(MF);
294   }
295 
296   DisasmLines.clear();
297   HexLines.clear();
298   DisasmLineMaxLen = 0;
299 
300   EmitFunctionBody();
301 
302   if (isVerbose()) {
303     MCSectionELF *CommentSection =
304         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
305     OutStreamer->SwitchSection(CommentSection);
306 
307     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
308       if (!MFI->isEntryFunction()) {
309         OutStreamer->emitRawComment(" Function info:", false);
310         SIFunctionResourceInfo &Info = CallGraphResourceInfo[MF.getFunction()];
311         emitCommonFunctionComments(
312           Info.NumVGPR,
313           Info.getTotalNumSGPRs(MF.getSubtarget<SISubtarget>()),
314           Info.PrivateSegmentSize,
315           getFunctionCodeSize(MF));
316         return false;
317       }
318 
319       OutStreamer->emitRawComment(" Kernel info:", false);
320       emitCommonFunctionComments(CurrentProgramInfo.NumVGPR,
321                                  CurrentProgramInfo.NumSGPR,
322                                  CurrentProgramInfo.ScratchSize,
323                                  getFunctionCodeSize(MF));
324 
325       OutStreamer->emitRawComment(
326         " FloatMode: " + Twine(CurrentProgramInfo.FloatMode), false);
327       OutStreamer->emitRawComment(
328         " IeeeMode: " + Twine(CurrentProgramInfo.IEEEMode), false);
329       OutStreamer->emitRawComment(
330         " LDSByteSize: " + Twine(CurrentProgramInfo.LDSSize) +
331         " bytes/workgroup (compile time only)", false);
332 
333       OutStreamer->emitRawComment(
334         " SGPRBlocks: " + Twine(CurrentProgramInfo.SGPRBlocks), false);
335       OutStreamer->emitRawComment(
336         " VGPRBlocks: " + Twine(CurrentProgramInfo.VGPRBlocks), false);
337 
338       OutStreamer->emitRawComment(
339         " NumSGPRsForWavesPerEU: " +
340         Twine(CurrentProgramInfo.NumSGPRsForWavesPerEU), false);
341       OutStreamer->emitRawComment(
342         " NumVGPRsForWavesPerEU: " +
343         Twine(CurrentProgramInfo.NumVGPRsForWavesPerEU), false);
344 
345       OutStreamer->emitRawComment(
346         " ReservedVGPRFirst: " + Twine(CurrentProgramInfo.ReservedVGPRFirst),
347         false);
348       OutStreamer->emitRawComment(
349         " ReservedVGPRCount: " + Twine(CurrentProgramInfo.ReservedVGPRCount),
350         false);
351 
352       if (MF.getSubtarget<SISubtarget>().debuggerEmitPrologue()) {
353         OutStreamer->emitRawComment(
354           " DebuggerWavefrontPrivateSegmentOffsetSGPR: s" +
355           Twine(CurrentProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR), false);
356         OutStreamer->emitRawComment(
357           " DebuggerPrivateSegmentBufferSGPR: s" +
358           Twine(CurrentProgramInfo.DebuggerPrivateSegmentBufferSGPR), false);
359       }
360 
361       OutStreamer->emitRawComment(
362         " COMPUTE_PGM_RSRC2:USER_SGPR: " +
363         Twine(G_00B84C_USER_SGPR(CurrentProgramInfo.ComputePGMRSrc2)), false);
364       OutStreamer->emitRawComment(
365         " COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
366         Twine(G_00B84C_TRAP_HANDLER(CurrentProgramInfo.ComputePGMRSrc2)), false);
367       OutStreamer->emitRawComment(
368         " COMPUTE_PGM_RSRC2:TGID_X_EN: " +
369         Twine(G_00B84C_TGID_X_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
370       OutStreamer->emitRawComment(
371         " COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
372         Twine(G_00B84C_TGID_Y_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
373       OutStreamer->emitRawComment(
374         " COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
375         Twine(G_00B84C_TGID_Z_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
376       OutStreamer->emitRawComment(
377         " COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
378         Twine(G_00B84C_TIDIG_COMP_CNT(CurrentProgramInfo.ComputePGMRSrc2)),
379         false);
380     } else {
381       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
382       OutStreamer->emitRawComment(
383         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->CFStackSize)));
384     }
385   }
386 
387   if (STM.dumpCode()) {
388 
389     OutStreamer->SwitchSection(
390         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
391 
392     for (size_t i = 0; i < DisasmLines.size(); ++i) {
393       std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
394       Comment += " ; " + HexLines[i] + "\n";
395 
396       OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
397       OutStreamer->EmitBytes(StringRef(Comment));
398     }
399   }
400 
401   return false;
402 }
403 
404 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
405   unsigned MaxGPR = 0;
406   bool killPixel = false;
407   const R600Subtarget &STM = MF.getSubtarget<R600Subtarget>();
408   const R600RegisterInfo *RI = STM.getRegisterInfo();
409   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
410 
411   for (const MachineBasicBlock &MBB : MF) {
412     for (const MachineInstr &MI : MBB) {
413       if (MI.getOpcode() == AMDGPU::KILLGT)
414         killPixel = true;
415       unsigned numOperands = MI.getNumOperands();
416       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
417         const MachineOperand &MO = MI.getOperand(op_idx);
418         if (!MO.isReg())
419           continue;
420         unsigned HWReg = RI->getHWRegIndex(MO.getReg());
421 
422         // Register with value > 127 aren't GPR
423         if (HWReg > 127)
424           continue;
425         MaxGPR = std::max(MaxGPR, HWReg);
426       }
427     }
428   }
429 
430   unsigned RsrcReg;
431   if (STM.getGeneration() >= R600Subtarget::EVERGREEN) {
432     // Evergreen / Northern Islands
433     switch (MF.getFunction()->getCallingConv()) {
434     default: LLVM_FALLTHROUGH;
435     case CallingConv::AMDGPU_CS: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
436     case CallingConv::AMDGPU_GS: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
437     case CallingConv::AMDGPU_PS: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
438     case CallingConv::AMDGPU_VS: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
439     }
440   } else {
441     // R600 / R700
442     switch (MF.getFunction()->getCallingConv()) {
443     default: LLVM_FALLTHROUGH;
444     case CallingConv::AMDGPU_GS: LLVM_FALLTHROUGH;
445     case CallingConv::AMDGPU_CS: LLVM_FALLTHROUGH;
446     case CallingConv::AMDGPU_VS: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
447     case CallingConv::AMDGPU_PS: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
448     }
449   }
450 
451   OutStreamer->EmitIntValue(RsrcReg, 4);
452   OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
453                            S_STACK_SIZE(MFI->CFStackSize), 4);
454   OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
455   OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
456 
457   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
458     OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
459     OutStreamer->EmitIntValue(alignTo(MFI->getLDSSize(), 4) >> 2, 4);
460   }
461 }
462 
463 uint64_t AMDGPUAsmPrinter::getFunctionCodeSize(const MachineFunction &MF) const {
464   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
465   const SIInstrInfo *TII = STM.getInstrInfo();
466 
467   uint64_t CodeSize = 0;
468 
469   for (const MachineBasicBlock &MBB : MF) {
470     for (const MachineInstr &MI : MBB) {
471       // TODO: CodeSize should account for multiple functions.
472 
473       // TODO: Should we count size of debug info?
474       if (MI.isDebugValue())
475         continue;
476 
477       CodeSize += TII->getInstSizeInBytes(MI);
478     }
479   }
480 
481   return CodeSize;
482 }
483 
484 static bool hasAnyNonFlatUseOfReg(const MachineRegisterInfo &MRI,
485                                   const SIInstrInfo &TII,
486                                   unsigned Reg) {
487   for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) {
488     if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent()))
489       return true;
490   }
491 
492   return false;
493 }
494 
495 static unsigned getNumExtraSGPRs(const SISubtarget &ST,
496                                  bool VCCUsed,
497                                  bool FlatScrUsed) {
498   unsigned ExtraSGPRs = 0;
499   if (VCCUsed)
500     ExtraSGPRs = 2;
501 
502   if (ST.getGeneration() < SISubtarget::VOLCANIC_ISLANDS) {
503     if (FlatScrUsed)
504       ExtraSGPRs = 4;
505   } else {
506     if (ST.isXNACKEnabled())
507       ExtraSGPRs = 4;
508 
509     if (FlatScrUsed)
510       ExtraSGPRs = 6;
511   }
512 
513   return ExtraSGPRs;
514 }
515 
516 int32_t AMDGPUAsmPrinter::SIFunctionResourceInfo::getTotalNumSGPRs(
517   const SISubtarget &ST) const {
518   return NumExplicitSGPR + getNumExtraSGPRs(ST, UsesVCC, UsesFlatScratch);
519 }
520 
521 AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
522   const MachineFunction &MF) const {
523   SIFunctionResourceInfo Info;
524 
525   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
526   const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
527   const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
528   const MachineRegisterInfo &MRI = MF.getRegInfo();
529   const SIInstrInfo *TII = ST.getInstrInfo();
530   const SIRegisterInfo &TRI = TII->getRegisterInfo();
531 
532   Info.UsesFlatScratch = MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_LO) ||
533                          MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_HI);
534 
535   // Even if FLAT_SCRATCH is implicitly used, it has no effect if flat
536   // instructions aren't used to access the scratch buffer. Inline assembly may
537   // need it though.
538   //
539   // If we only have implicit uses of flat_scr on flat instructions, it is not
540   // really needed.
541   if (Info.UsesFlatScratch && !MFI->hasFlatScratchInit() &&
542       (!hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR) &&
543        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_LO) &&
544        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_HI))) {
545     Info.UsesFlatScratch = false;
546   }
547 
548   Info.HasDynamicallySizedStack = FrameInfo.hasVarSizedObjects();
549   Info.PrivateSegmentSize = FrameInfo.getStackSize();
550 
551 
552   Info.UsesVCC = MRI.isPhysRegUsed(AMDGPU::VCC_LO) ||
553                  MRI.isPhysRegUsed(AMDGPU::VCC_HI);
554 
555   // If there are no calls, MachineRegisterInfo can tell us the used register
556   // count easily.
557   // A tail call isn't considered a call for MachineFrameInfo's purposes.
558   if (!FrameInfo.hasCalls() && !FrameInfo.hasTailCall()) {
559     MCPhysReg HighestVGPRReg = AMDGPU::NoRegister;
560     for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) {
561       if (MRI.isPhysRegUsed(Reg)) {
562         HighestVGPRReg = Reg;
563         break;
564       }
565     }
566 
567     MCPhysReg HighestSGPRReg = AMDGPU::NoRegister;
568     for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) {
569       if (MRI.isPhysRegUsed(Reg)) {
570         HighestSGPRReg = Reg;
571         break;
572       }
573     }
574 
575     // We found the maximum register index. They start at 0, so add one to get the
576     // number of registers.
577     Info.NumVGPR = HighestVGPRReg == AMDGPU::NoRegister ? 0 :
578       TRI.getHWRegIndex(HighestVGPRReg) + 1;
579     Info.NumExplicitSGPR = HighestSGPRReg == AMDGPU::NoRegister ? 0 :
580       TRI.getHWRegIndex(HighestSGPRReg) + 1;
581 
582     return Info;
583   }
584 
585   int32_t MaxVGPR = -1;
586   int32_t MaxSGPR = -1;
587   uint32_t CalleeFrameSize = 0;
588 
589   for (const MachineBasicBlock &MBB : MF) {
590     for (const MachineInstr &MI : MBB) {
591       // TODO: Check regmasks? Do they occur anywhere except calls?
592       for (const MachineOperand &MO : MI.operands()) {
593         unsigned Width = 0;
594         bool IsSGPR = false;
595 
596         if (!MO.isReg())
597           continue;
598 
599         unsigned Reg = MO.getReg();
600         switch (Reg) {
601         case AMDGPU::EXEC:
602         case AMDGPU::EXEC_LO:
603         case AMDGPU::EXEC_HI:
604         case AMDGPU::SCC:
605         case AMDGPU::M0:
606         case AMDGPU::SRC_SHARED_BASE:
607         case AMDGPU::SRC_SHARED_LIMIT:
608         case AMDGPU::SRC_PRIVATE_BASE:
609         case AMDGPU::SRC_PRIVATE_LIMIT:
610           continue;
611 
612         case AMDGPU::NoRegister:
613           assert(MI.isDebugValue());
614           continue;
615 
616         case AMDGPU::VCC:
617         case AMDGPU::VCC_LO:
618         case AMDGPU::VCC_HI:
619           Info.UsesVCC = true;
620           continue;
621 
622         case AMDGPU::FLAT_SCR:
623         case AMDGPU::FLAT_SCR_LO:
624         case AMDGPU::FLAT_SCR_HI:
625           continue;
626 
627         case AMDGPU::TBA:
628         case AMDGPU::TBA_LO:
629         case AMDGPU::TBA_HI:
630         case AMDGPU::TMA:
631         case AMDGPU::TMA_LO:
632         case AMDGPU::TMA_HI:
633           llvm_unreachable("trap handler registers should not be used");
634 
635         default:
636           break;
637         }
638 
639         if (AMDGPU::SReg_32RegClass.contains(Reg)) {
640           assert(!AMDGPU::TTMP_32RegClass.contains(Reg) &&
641                  "trap handler registers should not be used");
642           IsSGPR = true;
643           Width = 1;
644         } else if (AMDGPU::VGPR_32RegClass.contains(Reg)) {
645           IsSGPR = false;
646           Width = 1;
647         } else if (AMDGPU::SReg_64RegClass.contains(Reg)) {
648           assert(!AMDGPU::TTMP_64RegClass.contains(Reg) &&
649                  "trap handler registers should not be used");
650           IsSGPR = true;
651           Width = 2;
652         } else if (AMDGPU::VReg_64RegClass.contains(Reg)) {
653           IsSGPR = false;
654           Width = 2;
655         } else if (AMDGPU::VReg_96RegClass.contains(Reg)) {
656           IsSGPR = false;
657           Width = 3;
658         } else if (AMDGPU::SReg_128RegClass.contains(Reg)) {
659           IsSGPR = true;
660           Width = 4;
661         } else if (AMDGPU::VReg_128RegClass.contains(Reg)) {
662           IsSGPR = false;
663           Width = 4;
664         } else if (AMDGPU::SReg_256RegClass.contains(Reg)) {
665           IsSGPR = true;
666           Width = 8;
667         } else if (AMDGPU::VReg_256RegClass.contains(Reg)) {
668           IsSGPR = false;
669           Width = 8;
670         } else if (AMDGPU::SReg_512RegClass.contains(Reg)) {
671           IsSGPR = true;
672           Width = 16;
673         } else if (AMDGPU::VReg_512RegClass.contains(Reg)) {
674           IsSGPR = false;
675           Width = 16;
676         } else {
677           llvm_unreachable("Unknown register class");
678         }
679         unsigned HWReg = TRI.getHWRegIndex(Reg);
680         int MaxUsed = HWReg + Width - 1;
681         if (IsSGPR) {
682           MaxSGPR = MaxUsed > MaxSGPR ? MaxUsed : MaxSGPR;
683         } else {
684           MaxVGPR = MaxUsed > MaxVGPR ? MaxUsed : MaxVGPR;
685         }
686       }
687 
688       if (MI.isCall()) {
689         // Pseudo used just to encode the underlying global. Is there a better
690         // way to track this?
691 
692         const MachineOperand *CalleeOp
693           = TII->getNamedOperand(MI, AMDGPU::OpName::callee);
694         const Function *Callee = cast<Function>(CalleeOp->getGlobal());
695         if (Callee->isDeclaration()) {
696           // If this is a call to an external function, we can't do much. Make
697           // conservative guesses.
698 
699           // 48 SGPRs - vcc, - flat_scr, -xnack
700           int MaxSGPRGuess = 47 - getNumExtraSGPRs(ST, true,
701                                                    ST.hasFlatAddressSpace());
702           MaxSGPR = std::max(MaxSGPR, MaxSGPRGuess);
703           MaxVGPR = std::max(MaxVGPR, 23);
704 
705           CalleeFrameSize = std::max(CalleeFrameSize, 16384u);
706           Info.UsesVCC = true;
707           Info.UsesFlatScratch = ST.hasFlatAddressSpace();
708           Info.HasDynamicallySizedStack = true;
709         } else {
710           // We force CodeGen to run in SCC order, so the callee's register
711           // usage etc. should be the cumulative usage of all callees.
712           auto I = CallGraphResourceInfo.find(Callee);
713           assert(I != CallGraphResourceInfo.end() &&
714                  "callee should have been handled before caller");
715 
716           MaxSGPR = std::max(I->second.NumExplicitSGPR - 1, MaxSGPR);
717           MaxVGPR = std::max(I->second.NumVGPR - 1, MaxVGPR);
718           CalleeFrameSize
719             = std::max(I->second.PrivateSegmentSize, CalleeFrameSize);
720           Info.UsesVCC |= I->second.UsesVCC;
721           Info.UsesFlatScratch |= I->second.UsesFlatScratch;
722           Info.HasDynamicallySizedStack |= I->second.HasDynamicallySizedStack;
723           Info.HasRecursion |= I->second.HasRecursion;
724         }
725 
726         if (!Callee->doesNotRecurse())
727           Info.HasRecursion = true;
728       }
729     }
730   }
731 
732   Info.NumExplicitSGPR = MaxSGPR + 1;
733   Info.NumVGPR = MaxVGPR + 1;
734   Info.PrivateSegmentSize += CalleeFrameSize;
735 
736   return Info;
737 }
738 
739 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
740                                         const MachineFunction &MF) {
741   SIFunctionResourceInfo Info = analyzeResourceUsage(MF);
742 
743   ProgInfo.NumVGPR = Info.NumVGPR;
744   ProgInfo.NumSGPR = Info.NumExplicitSGPR;
745   ProgInfo.ScratchSize = Info.PrivateSegmentSize;
746   ProgInfo.VCCUsed = Info.UsesVCC;
747   ProgInfo.FlatUsed = Info.UsesFlatScratch;
748   ProgInfo.DynamicCallStack = Info.HasDynamicallySizedStack || Info.HasRecursion;
749 
750   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
751   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
752   const SIInstrInfo *TII = STM.getInstrInfo();
753   const SIRegisterInfo *RI = &TII->getRegisterInfo();
754 
755   unsigned ExtraSGPRs = getNumExtraSGPRs(STM,
756                                          ProgInfo.VCCUsed,
757                                          ProgInfo.FlatUsed);
758   unsigned ExtraVGPRs = STM.getReservedNumVGPRs(MF);
759 
760   // Check the addressable register limit before we add ExtraSGPRs.
761   if (STM.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
762       !STM.hasSGPRInitBug()) {
763     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
764     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
765       // This can happen due to a compiler bug or when using inline asm.
766       LLVMContext &Ctx = MF.getFunction()->getContext();
767       DiagnosticInfoResourceLimit Diag(*MF.getFunction(),
768                                        "addressable scalar registers",
769                                        ProgInfo.NumSGPR, DS_Error,
770                                        DK_ResourceLimit,
771                                        MaxAddressableNumSGPRs);
772       Ctx.diagnose(Diag);
773       ProgInfo.NumSGPR = MaxAddressableNumSGPRs - 1;
774     }
775   }
776 
777   // Account for extra SGPRs and VGPRs reserved for debugger use.
778   ProgInfo.NumSGPR += ExtraSGPRs;
779   ProgInfo.NumVGPR += ExtraVGPRs;
780 
781   // Adjust number of registers used to meet default/requested minimum/maximum
782   // number of waves per execution unit request.
783   ProgInfo.NumSGPRsForWavesPerEU = std::max(
784     std::max(ProgInfo.NumSGPR, 1u), STM.getMinNumSGPRs(MFI->getMaxWavesPerEU()));
785   ProgInfo.NumVGPRsForWavesPerEU = std::max(
786     std::max(ProgInfo.NumVGPR, 1u), STM.getMinNumVGPRs(MFI->getMaxWavesPerEU()));
787 
788   if (STM.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ||
789       STM.hasSGPRInitBug()) {
790     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
791     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
792       // This can happen due to a compiler bug or when using inline asm to use
793       // the registers which are usually reserved for vcc etc.
794       LLVMContext &Ctx = MF.getFunction()->getContext();
795       DiagnosticInfoResourceLimit Diag(*MF.getFunction(),
796                                        "scalar registers",
797                                        ProgInfo.NumSGPR, DS_Error,
798                                        DK_ResourceLimit,
799                                        MaxAddressableNumSGPRs);
800       Ctx.diagnose(Diag);
801       ProgInfo.NumSGPR = MaxAddressableNumSGPRs;
802       ProgInfo.NumSGPRsForWavesPerEU = MaxAddressableNumSGPRs;
803     }
804   }
805 
806   if (STM.hasSGPRInitBug()) {
807     ProgInfo.NumSGPR =
808         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
809     ProgInfo.NumSGPRsForWavesPerEU =
810         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
811   }
812 
813   if (MFI->getNumUserSGPRs() > STM.getMaxNumUserSGPRs()) {
814     LLVMContext &Ctx = MF.getFunction()->getContext();
815     DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "user SGPRs",
816                                      MFI->getNumUserSGPRs(), DS_Error);
817     Ctx.diagnose(Diag);
818   }
819 
820   if (MFI->getLDSSize() > static_cast<unsigned>(STM.getLocalMemorySize())) {
821     LLVMContext &Ctx = MF.getFunction()->getContext();
822     DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "local memory",
823                                      MFI->getLDSSize(), DS_Error);
824     Ctx.diagnose(Diag);
825   }
826 
827   // SGPRBlocks is actual number of SGPR blocks minus 1.
828   ProgInfo.SGPRBlocks = alignTo(ProgInfo.NumSGPRsForWavesPerEU,
829                                 STM.getSGPREncodingGranule());
830   ProgInfo.SGPRBlocks = ProgInfo.SGPRBlocks / STM.getSGPREncodingGranule() - 1;
831 
832   // VGPRBlocks is actual number of VGPR blocks minus 1.
833   ProgInfo.VGPRBlocks = alignTo(ProgInfo.NumVGPRsForWavesPerEU,
834                                 STM.getVGPREncodingGranule());
835   ProgInfo.VGPRBlocks = ProgInfo.VGPRBlocks / STM.getVGPREncodingGranule() - 1;
836 
837   // Record first reserved VGPR and number of reserved VGPRs.
838   ProgInfo.ReservedVGPRFirst = STM.debuggerReserveRegs() ? ProgInfo.NumVGPR : 0;
839   ProgInfo.ReservedVGPRCount = STM.getReservedNumVGPRs(MF);
840 
841   // Update DebuggerWavefrontPrivateSegmentOffsetSGPR and
842   // DebuggerPrivateSegmentBufferSGPR fields if "amdgpu-debugger-emit-prologue"
843   // attribute was requested.
844   if (STM.debuggerEmitPrologue()) {
845     ProgInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR =
846       RI->getHWRegIndex(MFI->getScratchWaveOffsetReg());
847     ProgInfo.DebuggerPrivateSegmentBufferSGPR =
848       RI->getHWRegIndex(MFI->getScratchRSrcReg());
849   }
850 
851   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
852   // register.
853   ProgInfo.FloatMode = getFPMode(MF);
854 
855   ProgInfo.IEEEMode = STM.enableIEEEBit(MF);
856 
857   // Make clamp modifier on NaN input returns 0.
858   ProgInfo.DX10Clamp = STM.enableDX10Clamp();
859 
860   unsigned LDSAlignShift;
861   if (STM.getGeneration() < SISubtarget::SEA_ISLANDS) {
862     // LDS is allocated in 64 dword blocks.
863     LDSAlignShift = 8;
864   } else {
865     // LDS is allocated in 128 dword blocks.
866     LDSAlignShift = 9;
867   }
868 
869   unsigned LDSSpillSize =
870     MFI->getLDSWaveSpillSize() * MFI->getMaxFlatWorkGroupSize();
871 
872   ProgInfo.LDSSize = MFI->getLDSSize() + LDSSpillSize;
873   ProgInfo.LDSBlocks =
874       alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
875 
876   // Scratch is allocated in 256 dword blocks.
877   unsigned ScratchAlignShift = 10;
878   // We need to program the hardware with the amount of scratch memory that
879   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
880   // scratch memory used per thread.
881   ProgInfo.ScratchBlocks =
882       alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
883               1ULL << ScratchAlignShift) >>
884       ScratchAlignShift;
885 
886   ProgInfo.ComputePGMRSrc1 =
887       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
888       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
889       S_00B848_PRIORITY(ProgInfo.Priority) |
890       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
891       S_00B848_PRIV(ProgInfo.Priv) |
892       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
893       S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
894       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
895 
896   // 0 = X, 1 = XY, 2 = XYZ
897   unsigned TIDIGCompCnt = 0;
898   if (MFI->hasWorkItemIDZ())
899     TIDIGCompCnt = 2;
900   else if (MFI->hasWorkItemIDY())
901     TIDIGCompCnt = 1;
902 
903   ProgInfo.ComputePGMRSrc2 =
904       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
905       S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
906       S_00B84C_TRAP_HANDLER(STM.isTrapHandlerEnabled()) |
907       S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
908       S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
909       S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
910       S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
911       S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
912       S_00B84C_EXCP_EN_MSB(0) |
913       // For AMDHSA, LDS_SIZE must be zero, as it is populated by the CP.
914       S_00B84C_LDS_SIZE(STM.isAmdHsaOS() ? 0 : ProgInfo.LDSBlocks) |
915       S_00B84C_EXCP_EN(0);
916 }
917 
918 static unsigned getRsrcReg(CallingConv::ID CallConv) {
919   switch (CallConv) {
920   default: LLVM_FALLTHROUGH;
921   case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
922   case CallingConv::AMDGPU_LS: return R_00B528_SPI_SHADER_PGM_RSRC1_LS;
923   case CallingConv::AMDGPU_HS: return R_00B428_SPI_SHADER_PGM_RSRC1_HS;
924   case CallingConv::AMDGPU_ES: return R_00B328_SPI_SHADER_PGM_RSRC1_ES;
925   case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
926   case CallingConv::AMDGPU_VS: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
927   case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
928   }
929 }
930 
931 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
932                                          const SIProgramInfo &CurrentProgramInfo) {
933   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
934   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
935   unsigned RsrcReg = getRsrcReg(MF.getFunction()->getCallingConv());
936 
937   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
938     OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
939 
940     OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc1, 4);
941 
942     OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
943     OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc2, 4);
944 
945     OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
946     OutStreamer->EmitIntValue(S_00B860_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
947 
948     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
949     // 0" comment but I don't see a corresponding field in the register spec.
950   } else {
951     OutStreamer->EmitIntValue(RsrcReg, 4);
952     OutStreamer->EmitIntValue(S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
953                               S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks), 4);
954     unsigned Rsrc2Val = 0;
955     if (STM.isVGPRSpillingEnabled(*MF.getFunction())) {
956       OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
957       OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
958       if (TM.getTargetTriple().getOS() == Triple::AMDPAL)
959         Rsrc2Val = S_00B84C_SCRATCH_EN(CurrentProgramInfo.ScratchBlocks > 0);
960     }
961     if (MF.getFunction()->getCallingConv() == CallingConv::AMDGPU_PS) {
962       OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
963       OutStreamer->EmitIntValue(MFI->getPSInputEnable(), 4);
964       OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
965       OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4);
966       Rsrc2Val |= S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks);
967     }
968     if (Rsrc2Val) {
969       OutStreamer->EmitIntValue(RsrcReg + 4 /*rsrc2*/, 4);
970       OutStreamer->EmitIntValue(Rsrc2Val, 4);
971     }
972   }
973 
974   OutStreamer->EmitIntValue(R_SPILLED_SGPRS, 4);
975   OutStreamer->EmitIntValue(MFI->getNumSpilledSGPRs(), 4);
976   OutStreamer->EmitIntValue(R_SPILLED_VGPRS, 4);
977   OutStreamer->EmitIntValue(MFI->getNumSpilledVGPRs(), 4);
978 }
979 
980 // This is the equivalent of EmitProgramInfoSI above, but for when the OS type
981 // is AMDPAL.  It stores each compute/SPI register setting and other PAL
982 // metadata items into the PALMetadataMap, combining with any provided by the
983 // frontend as LLVM metadata. Once all functions are written, PALMetadataMap is
984 // then written as a single block in the .note section.
985 void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
986        const SIProgramInfo &CurrentProgramInfo) {
987   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
988   // Given the calling convention, calculate the register number for rsrc1. In
989   // principle the register number could change in future hardware, but we know
990   // it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so
991   // we can use the same fixed value that .AMDGPU.config has for Mesa. Note
992   // that we use a register number rather than a byte offset, so we need to
993   // divide by 4.
994   unsigned Rsrc1Reg = getRsrcReg(MF.getFunction()->getCallingConv()) / 4;
995   unsigned Rsrc2Reg = Rsrc1Reg + 1;
996   // Also calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used
997   // with a constant offset to access any non-register shader-specific PAL
998   // metadata key.
999   unsigned ScratchSizeKey = PALMD::Key::CS_SCRATCH_SIZE;
1000   switch (MF.getFunction()->getCallingConv()) {
1001     case CallingConv::AMDGPU_PS:
1002       ScratchSizeKey = PALMD::Key::PS_SCRATCH_SIZE;
1003       break;
1004     case CallingConv::AMDGPU_VS:
1005       ScratchSizeKey = PALMD::Key::VS_SCRATCH_SIZE;
1006       break;
1007     case CallingConv::AMDGPU_GS:
1008       ScratchSizeKey = PALMD::Key::GS_SCRATCH_SIZE;
1009       break;
1010     case CallingConv::AMDGPU_ES:
1011       ScratchSizeKey = PALMD::Key::ES_SCRATCH_SIZE;
1012       break;
1013     case CallingConv::AMDGPU_HS:
1014       ScratchSizeKey = PALMD::Key::HS_SCRATCH_SIZE;
1015       break;
1016     case CallingConv::AMDGPU_LS:
1017       ScratchSizeKey = PALMD::Key::LS_SCRATCH_SIZE;
1018       break;
1019   }
1020   unsigned NumUsedVgprsKey = ScratchSizeKey +
1021       PALMD::Key::VS_NUM_USED_VGPRS - PALMD::Key::VS_SCRATCH_SIZE;
1022   unsigned NumUsedSgprsKey = ScratchSizeKey +
1023       PALMD::Key::VS_NUM_USED_SGPRS - PALMD::Key::VS_SCRATCH_SIZE;
1024   PALMetadataMap[NumUsedVgprsKey] = CurrentProgramInfo.NumVGPRsForWavesPerEU;
1025   PALMetadataMap[NumUsedSgprsKey] = CurrentProgramInfo.NumSGPRsForWavesPerEU;
1026   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
1027     PALMetadataMap[Rsrc1Reg] |= CurrentProgramInfo.ComputePGMRSrc1;
1028     PALMetadataMap[Rsrc2Reg] |= CurrentProgramInfo.ComputePGMRSrc2;
1029     // ScratchSize is in bytes, 16 aligned.
1030     PALMetadataMap[ScratchSizeKey] |=
1031         alignTo(CurrentProgramInfo.ScratchSize, 16);
1032   } else {
1033     PALMetadataMap[Rsrc1Reg] |= S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
1034         S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks);
1035     if (CurrentProgramInfo.ScratchBlocks > 0)
1036       PALMetadataMap[Rsrc2Reg] |= S_00B84C_SCRATCH_EN(1);
1037     // ScratchSize is in bytes, 16 aligned.
1038     PALMetadataMap[ScratchSizeKey] |=
1039         alignTo(CurrentProgramInfo.ScratchSize, 16);
1040   }
1041   if (MF.getFunction()->getCallingConv() == CallingConv::AMDGPU_PS) {
1042     PALMetadataMap[Rsrc2Reg] |=
1043         S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks);
1044     PALMetadataMap[R_0286CC_SPI_PS_INPUT_ENA / 4] |= MFI->getPSInputEnable();
1045     PALMetadataMap[R_0286D0_SPI_PS_INPUT_ADDR / 4] |= MFI->getPSInputAddr();
1046   }
1047 }
1048 
1049 // This is supposed to be log2(Size)
1050 static amd_element_byte_size_t getElementByteSizeValue(unsigned Size) {
1051   switch (Size) {
1052   case 4:
1053     return AMD_ELEMENT_4_BYTES;
1054   case 8:
1055     return AMD_ELEMENT_8_BYTES;
1056   case 16:
1057     return AMD_ELEMENT_16_BYTES;
1058   default:
1059     llvm_unreachable("invalid private_element_size");
1060   }
1061 }
1062 
1063 void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out,
1064                                         const SIProgramInfo &CurrentProgramInfo,
1065                                         const MachineFunction &MF) const {
1066   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1067   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
1068 
1069   AMDGPU::initDefaultAMDKernelCodeT(Out, STM.getFeatureBits());
1070 
1071   Out.compute_pgm_resource_registers =
1072       CurrentProgramInfo.ComputePGMRSrc1 |
1073       (CurrentProgramInfo.ComputePGMRSrc2 << 32);
1074   Out.code_properties = AMD_CODE_PROPERTY_IS_PTR64;
1075 
1076   if (CurrentProgramInfo.DynamicCallStack)
1077     Out.code_properties |= AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK;
1078 
1079   AMD_HSA_BITS_SET(Out.code_properties,
1080                    AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE,
1081                    getElementByteSizeValue(STM.getMaxPrivateElementSize()));
1082 
1083   if (MFI->hasPrivateSegmentBuffer()) {
1084     Out.code_properties |=
1085       AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
1086   }
1087 
1088   if (MFI->hasDispatchPtr())
1089     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
1090 
1091   if (MFI->hasQueuePtr())
1092     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
1093 
1094   if (MFI->hasKernargSegmentPtr())
1095     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
1096 
1097   if (MFI->hasDispatchID())
1098     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
1099 
1100   if (MFI->hasFlatScratchInit())
1101     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
1102 
1103   if (MFI->hasGridWorkgroupCountX()) {
1104     Out.code_properties |=
1105       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X;
1106   }
1107 
1108   if (MFI->hasGridWorkgroupCountY()) {
1109     Out.code_properties |=
1110       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y;
1111   }
1112 
1113   if (MFI->hasGridWorkgroupCountZ()) {
1114     Out.code_properties |=
1115       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z;
1116   }
1117 
1118   if (MFI->hasDispatchPtr())
1119     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
1120 
1121   if (STM.debuggerSupported())
1122     Out.code_properties |= AMD_CODE_PROPERTY_IS_DEBUG_SUPPORTED;
1123 
1124   if (STM.isXNACKEnabled())
1125     Out.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED;
1126 
1127   // FIXME: Should use getKernArgSize
1128   Out.kernarg_segment_byte_size =
1129     STM.getKernArgSegmentSize(MF, MFI->getABIArgOffset());
1130   Out.wavefront_sgpr_count = CurrentProgramInfo.NumSGPR;
1131   Out.workitem_vgpr_count = CurrentProgramInfo.NumVGPR;
1132   Out.workitem_private_segment_byte_size = CurrentProgramInfo.ScratchSize;
1133   Out.workgroup_group_segment_byte_size = CurrentProgramInfo.LDSSize;
1134   Out.reserved_vgpr_first = CurrentProgramInfo.ReservedVGPRFirst;
1135   Out.reserved_vgpr_count = CurrentProgramInfo.ReservedVGPRCount;
1136 
1137   // These alignment values are specified in powers of two, so alignment =
1138   // 2^n.  The minimum alignment is 2^4 = 16.
1139   Out.kernarg_segment_alignment = std::max((size_t)4,
1140       countTrailingZeros(MFI->getMaxKernArgAlign()));
1141 
1142   if (STM.debuggerEmitPrologue()) {
1143     Out.debug_wavefront_private_segment_offset_sgpr =
1144       CurrentProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR;
1145     Out.debug_private_segment_buffer_sgpr =
1146       CurrentProgramInfo.DebuggerPrivateSegmentBufferSGPR;
1147   }
1148 }
1149 
1150 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
1151                                        unsigned AsmVariant,
1152                                        const char *ExtraCode, raw_ostream &O) {
1153   // First try the generic code, which knows about modifiers like 'c' and 'n'.
1154   if (!AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O))
1155     return false;
1156 
1157   if (ExtraCode && ExtraCode[0]) {
1158     if (ExtraCode[1] != 0)
1159       return true; // Unknown modifier.
1160 
1161     switch (ExtraCode[0]) {
1162     case 'r':
1163       break;
1164     default:
1165       return true;
1166     }
1167   }
1168 
1169   // TODO: Should be able to support other operand types like globals.
1170   const MachineOperand &MO = MI->getOperand(OpNo);
1171   if (MO.isReg()) {
1172     AMDGPUInstPrinter::printRegOperand(MO.getReg(), O,
1173                                        *MF->getSubtarget().getRegisterInfo());
1174     return false;
1175   }
1176 
1177   return true;
1178 }
1179