1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
15 //
16 //===----------------------------------------------------------------------===//
17 //
18 
19 #include "AMDGPUAsmPrinter.h"
20 #include "AMDGPU.h"
21 #include "AMDGPUSubtarget.h"
22 #include "AMDGPUTargetMachine.h"
23 #include "InstPrinter/AMDGPUInstPrinter.h"
24 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
25 #include "R600Defines.h"
26 #include "R600MachineFunctionInfo.h"
27 #include "R600RegisterInfo.h"
28 #include "SIDefines.h"
29 #include "SIInstrInfo.h"
30 #include "SIMachineFunctionInfo.h"
31 #include "SIRegisterInfo.h"
32 #include "Utils/AMDGPUBaseInfo.h"
33 #include "llvm/BinaryFormat/ELF.h"
34 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/IR/DiagnosticInfo.h"
36 #include "llvm/MC/MCContext.h"
37 #include "llvm/MC/MCSectionELF.h"
38 #include "llvm/MC/MCStreamer.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Target/TargetLoweringObjectFile.h"
42 
43 using namespace llvm;
44 
45 // TODO: This should get the default rounding mode from the kernel. We just set
46 // the default here, but this could change if the OpenCL rounding mode pragmas
47 // are used.
48 //
49 // The denormal mode here should match what is reported by the OpenCL runtime
50 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
51 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
52 //
53 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
54 // precision, and leaves single precision to flush all and does not report
55 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
56 // CL_FP_DENORM for both.
57 //
58 // FIXME: It seems some instructions do not support single precision denormals
59 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
60 // and sin_f32, cos_f32 on most parts).
61 
62 // We want to use these instructions, and using fp32 denormals also causes
63 // instructions to run at the double precision rate for the device so it's
64 // probably best to just report no single precision denormals.
65 static uint32_t getFPMode(const MachineFunction &F) {
66   const SISubtarget& ST = F.getSubtarget<SISubtarget>();
67   // TODO: Is there any real use for the flush in only / flush out only modes?
68 
69   uint32_t FP32Denormals =
70     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
71 
72   uint32_t FP64Denormals =
73     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
74 
75   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
76          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
77          FP_DENORM_MODE_SP(FP32Denormals) |
78          FP_DENORM_MODE_DP(FP64Denormals);
79 }
80 
81 static AsmPrinter *
82 createAMDGPUAsmPrinterPass(TargetMachine &tm,
83                            std::unique_ptr<MCStreamer> &&Streamer) {
84   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
85 }
86 
87 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
88   TargetRegistry::RegisterAsmPrinter(getTheAMDGPUTarget(),
89                                      createAMDGPUAsmPrinterPass);
90   TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(),
91                                      createAMDGPUAsmPrinterPass);
92 }
93 
94 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
95                                    std::unique_ptr<MCStreamer> Streamer)
96   : AsmPrinter(TM, std::move(Streamer)) {
97     AMDGPUASI = static_cast<AMDGPUTargetMachine*>(&TM)->getAMDGPUAS();
98   }
99 
100 StringRef AMDGPUAsmPrinter::getPassName() const {
101   return "AMDGPU Assembly Printer";
102 }
103 
104 const MCSubtargetInfo* AMDGPUAsmPrinter::getSTI() const {
105   return TM.getMCSubtargetInfo();
106 }
107 
108 AMDGPUTargetStreamer& AMDGPUAsmPrinter::getTargetStreamer() const {
109   return static_cast<AMDGPUTargetStreamer&>(*OutStreamer->getTargetStreamer());
110 }
111 
112 void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) {
113   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
114     return;
115 
116   AMDGPU::IsaInfo::IsaVersion ISA =
117       AMDGPU::IsaInfo::getIsaVersion(getSTI()->getFeatureBits());
118 
119   getTargetStreamer().EmitDirectiveHSACodeObjectVersion(2, 1);
120   getTargetStreamer().EmitDirectiveHSACodeObjectISA(
121       ISA.Major, ISA.Minor, ISA.Stepping, "AMD", "AMDGPU");
122   getTargetStreamer().EmitStartOfCodeObjectMetadata(M);
123 }
124 
125 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
126   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
127     return;
128 
129   getTargetStreamer().EmitEndOfCodeObjectMetadata();
130 }
131 
132 bool AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough(
133   const MachineBasicBlock *MBB) const {
134   if (!AsmPrinter::isBlockOnlyReachableByFallthrough(MBB))
135     return false;
136 
137   if (MBB->empty())
138     return true;
139 
140   // If this is a block implementing a long branch, an expression relative to
141   // the start of the block is needed.  to the start of the block.
142   // XXX - Is there a smarter way to check this?
143   return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
144 }
145 
146 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
147   const AMDGPUMachineFunction *MFI = MF->getInfo<AMDGPUMachineFunction>();
148   if (!MFI->isEntryFunction())
149     return;
150 
151   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
152   amd_kernel_code_t KernelCode;
153   if (STM.isAmdCodeObjectV2(*MF)) {
154     getAmdKernelCode(KernelCode, CurrentProgramInfo, *MF);
155 
156     OutStreamer->SwitchSection(getObjFileLowering().getTextSection());
157     getTargetStreamer().EmitAMDKernelCodeT(KernelCode);
158   }
159 
160   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
161     return;
162   getTargetStreamer().EmitKernelCodeObjectMetadata(*MF->getFunction(),
163                                                    KernelCode);
164 }
165 
166 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
167   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
168   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
169   if (MFI->isEntryFunction() && STM.isAmdCodeObjectV2(*MF)) {
170     SmallString<128> SymbolName;
171     getNameWithPrefix(SymbolName, MF->getFunction()),
172     getTargetStreamer().EmitAMDGPUSymbolType(
173         SymbolName, ELF::STT_AMDGPU_HSA_KERNEL);
174   }
175 
176   AsmPrinter::EmitFunctionEntryLabel();
177 }
178 
179 void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
180 
181   // Group segment variables aren't emitted in HSA.
182   if (AMDGPU::isGroupSegment(GV, AMDGPUASI))
183     return;
184 
185   AsmPrinter::EmitGlobalVariable(GV);
186 }
187 
188 bool AMDGPUAsmPrinter::doFinalization(Module &M) {
189   CallGraphResourceInfo.clear();
190   return AsmPrinter::doFinalization(M);
191 }
192 
193 // Print comments that apply to both callable functions and entry points.
194 void AMDGPUAsmPrinter::emitCommonFunctionComments(
195   uint32_t NumVGPR,
196   uint32_t NumSGPR,
197   uint32_t ScratchSize,
198   uint64_t CodeSize) {
199   OutStreamer->emitRawComment(" codeLenInByte = " + Twine(CodeSize), false);
200   OutStreamer->emitRawComment(" NumSgprs: " + Twine(NumSGPR), false);
201   OutStreamer->emitRawComment(" NumVgprs: " + Twine(NumVGPR), false);
202   OutStreamer->emitRawComment(" ScratchSize: " + Twine(ScratchSize), false);
203 }
204 
205 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
206   CurrentProgramInfo = SIProgramInfo();
207 
208   const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
209 
210   // The starting address of all shader programs must be 256 bytes aligned.
211   // Regular functions just need the basic required instruction alignment.
212   MF.setAlignment(MFI->isEntryFunction() ? 8 : 2);
213 
214   SetupMachineFunction(MF);
215 
216   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
217   MCContext &Context = getObjFileLowering().getContext();
218   if (!STM.isAmdHsaOS()) {
219     MCSectionELF *ConfigSection =
220         Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
221     OutStreamer->SwitchSection(ConfigSection);
222   }
223 
224   if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
225     if (MFI->isEntryFunction()) {
226       getSIProgramInfo(CurrentProgramInfo, MF);
227     } else {
228       auto I = CallGraphResourceInfo.insert(
229         std::make_pair(MF.getFunction(), SIFunctionResourceInfo()));
230       SIFunctionResourceInfo &Info = I.first->second;
231       assert(I.second && "should only be called once per function");
232       Info = analyzeResourceUsage(MF);
233     }
234 
235     if (!STM.isAmdHsaOS()) {
236       EmitProgramInfoSI(MF, CurrentProgramInfo);
237     }
238   } else {
239     EmitProgramInfoR600(MF);
240   }
241 
242   DisasmLines.clear();
243   HexLines.clear();
244   DisasmLineMaxLen = 0;
245 
246   EmitFunctionBody();
247 
248   if (isVerbose()) {
249     MCSectionELF *CommentSection =
250         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
251     OutStreamer->SwitchSection(CommentSection);
252 
253     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
254       if (!MFI->isEntryFunction()) {
255         OutStreamer->emitRawComment(" Function info:", false);
256         SIFunctionResourceInfo &Info = CallGraphResourceInfo[MF.getFunction()];
257         emitCommonFunctionComments(
258           Info.NumVGPR,
259           Info.getTotalNumSGPRs(MF.getSubtarget<SISubtarget>()),
260           Info.PrivateSegmentSize,
261           getFunctionCodeSize(MF));
262         return false;
263       }
264 
265       OutStreamer->emitRawComment(" Kernel info:", false);
266       emitCommonFunctionComments(CurrentProgramInfo.NumVGPR,
267                                  CurrentProgramInfo.NumSGPR,
268                                  CurrentProgramInfo.ScratchSize,
269                                  getFunctionCodeSize(MF));
270 
271       OutStreamer->emitRawComment(" codeLenInByte = " +
272                                   Twine(getFunctionCodeSize(MF)), false);
273       OutStreamer->emitRawComment(
274         " NumSgprs: " + Twine(CurrentProgramInfo.NumSGPR), false);
275       OutStreamer->emitRawComment(
276         " NumVgprs: " + Twine(CurrentProgramInfo.NumVGPR), false);
277 
278       OutStreamer->emitRawComment(
279         " FloatMode: " + Twine(CurrentProgramInfo.FloatMode), false);
280       OutStreamer->emitRawComment(
281         " IeeeMode: " + Twine(CurrentProgramInfo.IEEEMode), false);
282       OutStreamer->emitRawComment(
283         " ScratchSize: " + Twine(CurrentProgramInfo.ScratchSize), false);
284       OutStreamer->emitRawComment(
285         " LDSByteSize: " + Twine(CurrentProgramInfo.LDSSize) +
286         " bytes/workgroup (compile time only)", false);
287 
288       OutStreamer->emitRawComment(
289         " SGPRBlocks: " + Twine(CurrentProgramInfo.SGPRBlocks), false);
290       OutStreamer->emitRawComment(
291         " VGPRBlocks: " + Twine(CurrentProgramInfo.VGPRBlocks), false);
292 
293       OutStreamer->emitRawComment(
294         " NumSGPRsForWavesPerEU: " +
295         Twine(CurrentProgramInfo.NumSGPRsForWavesPerEU), false);
296       OutStreamer->emitRawComment(
297         " NumVGPRsForWavesPerEU: " +
298         Twine(CurrentProgramInfo.NumVGPRsForWavesPerEU), false);
299 
300       OutStreamer->emitRawComment(
301         " ReservedVGPRFirst: " + Twine(CurrentProgramInfo.ReservedVGPRFirst),
302         false);
303       OutStreamer->emitRawComment(
304         " ReservedVGPRCount: " + Twine(CurrentProgramInfo.ReservedVGPRCount),
305         false);
306 
307       if (MF.getSubtarget<SISubtarget>().debuggerEmitPrologue()) {
308         OutStreamer->emitRawComment(
309           " DebuggerWavefrontPrivateSegmentOffsetSGPR: s" +
310           Twine(CurrentProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR), false);
311         OutStreamer->emitRawComment(
312           " DebuggerPrivateSegmentBufferSGPR: s" +
313           Twine(CurrentProgramInfo.DebuggerPrivateSegmentBufferSGPR), false);
314       }
315 
316       OutStreamer->emitRawComment(
317         " COMPUTE_PGM_RSRC2:USER_SGPR: " +
318         Twine(G_00B84C_USER_SGPR(CurrentProgramInfo.ComputePGMRSrc2)), false);
319       OutStreamer->emitRawComment(
320         " COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
321         Twine(G_00B84C_TRAP_HANDLER(CurrentProgramInfo.ComputePGMRSrc2)), false);
322       OutStreamer->emitRawComment(
323         " COMPUTE_PGM_RSRC2:TGID_X_EN: " +
324         Twine(G_00B84C_TGID_X_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
325       OutStreamer->emitRawComment(
326         " COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
327         Twine(G_00B84C_TGID_Y_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
328       OutStreamer->emitRawComment(
329         " COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
330         Twine(G_00B84C_TGID_Z_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
331       OutStreamer->emitRawComment(
332         " COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
333         Twine(G_00B84C_TIDIG_COMP_CNT(CurrentProgramInfo.ComputePGMRSrc2)),
334         false);
335     } else {
336       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
337       OutStreamer->emitRawComment(
338         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->CFStackSize)));
339     }
340   }
341 
342   if (STM.dumpCode()) {
343 
344     OutStreamer->SwitchSection(
345         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
346 
347     for (size_t i = 0; i < DisasmLines.size(); ++i) {
348       std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
349       Comment += " ; " + HexLines[i] + "\n";
350 
351       OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
352       OutStreamer->EmitBytes(StringRef(Comment));
353     }
354   }
355 
356   return false;
357 }
358 
359 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
360   unsigned MaxGPR = 0;
361   bool killPixel = false;
362   const R600Subtarget &STM = MF.getSubtarget<R600Subtarget>();
363   const R600RegisterInfo *RI = STM.getRegisterInfo();
364   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
365 
366   for (const MachineBasicBlock &MBB : MF) {
367     for (const MachineInstr &MI : MBB) {
368       if (MI.getOpcode() == AMDGPU::KILLGT)
369         killPixel = true;
370       unsigned numOperands = MI.getNumOperands();
371       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
372         const MachineOperand &MO = MI.getOperand(op_idx);
373         if (!MO.isReg())
374           continue;
375         unsigned HWReg = RI->getHWRegIndex(MO.getReg());
376 
377         // Register with value > 127 aren't GPR
378         if (HWReg > 127)
379           continue;
380         MaxGPR = std::max(MaxGPR, HWReg);
381       }
382     }
383   }
384 
385   unsigned RsrcReg;
386   if (STM.getGeneration() >= R600Subtarget::EVERGREEN) {
387     // Evergreen / Northern Islands
388     switch (MF.getFunction()->getCallingConv()) {
389     default: LLVM_FALLTHROUGH;
390     case CallingConv::AMDGPU_CS: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
391     case CallingConv::AMDGPU_GS: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
392     case CallingConv::AMDGPU_PS: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
393     case CallingConv::AMDGPU_VS: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
394     }
395   } else {
396     // R600 / R700
397     switch (MF.getFunction()->getCallingConv()) {
398     default: LLVM_FALLTHROUGH;
399     case CallingConv::AMDGPU_GS: LLVM_FALLTHROUGH;
400     case CallingConv::AMDGPU_CS: LLVM_FALLTHROUGH;
401     case CallingConv::AMDGPU_VS: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
402     case CallingConv::AMDGPU_PS: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
403     }
404   }
405 
406   OutStreamer->EmitIntValue(RsrcReg, 4);
407   OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
408                            S_STACK_SIZE(MFI->CFStackSize), 4);
409   OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
410   OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
411 
412   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
413     OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
414     OutStreamer->EmitIntValue(alignTo(MFI->getLDSSize(), 4) >> 2, 4);
415   }
416 }
417 
418 uint64_t AMDGPUAsmPrinter::getFunctionCodeSize(const MachineFunction &MF) const {
419   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
420   const SIInstrInfo *TII = STM.getInstrInfo();
421 
422   uint64_t CodeSize = 0;
423 
424   for (const MachineBasicBlock &MBB : MF) {
425     for (const MachineInstr &MI : MBB) {
426       // TODO: CodeSize should account for multiple functions.
427 
428       // TODO: Should we count size of debug info?
429       if (MI.isDebugValue())
430         continue;
431 
432       CodeSize += TII->getInstSizeInBytes(MI);
433     }
434   }
435 
436   return CodeSize;
437 }
438 
439 static bool hasAnyNonFlatUseOfReg(const MachineRegisterInfo &MRI,
440                                   const SIInstrInfo &TII,
441                                   unsigned Reg) {
442   for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) {
443     if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent()))
444       return true;
445   }
446 
447   return false;
448 }
449 
450 static unsigned getNumExtraSGPRs(const SISubtarget &ST,
451                                  bool VCCUsed,
452                                  bool FlatScrUsed) {
453   unsigned ExtraSGPRs = 0;
454   if (VCCUsed)
455     ExtraSGPRs = 2;
456 
457   if (ST.getGeneration() < SISubtarget::VOLCANIC_ISLANDS) {
458     if (FlatScrUsed)
459       ExtraSGPRs = 4;
460   } else {
461     if (ST.isXNACKEnabled())
462       ExtraSGPRs = 4;
463 
464     if (FlatScrUsed)
465       ExtraSGPRs = 6;
466   }
467 
468   return ExtraSGPRs;
469 }
470 
471 int32_t AMDGPUAsmPrinter::SIFunctionResourceInfo::getTotalNumSGPRs(
472   const SISubtarget &ST) const {
473   return NumExplicitSGPR + getNumExtraSGPRs(ST, UsesVCC, UsesFlatScratch);
474 }
475 
476 AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
477   const MachineFunction &MF) const {
478   SIFunctionResourceInfo Info;
479 
480   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
481   const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
482   const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
483   const MachineRegisterInfo &MRI = MF.getRegInfo();
484   const SIInstrInfo *TII = ST.getInstrInfo();
485   const SIRegisterInfo &TRI = TII->getRegisterInfo();
486 
487   Info.UsesFlatScratch = MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_LO) ||
488                          MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_HI);
489 
490   // Even if FLAT_SCRATCH is implicitly used, it has no effect if flat
491   // instructions aren't used to access the scratch buffer. Inline assembly may
492   // need it though.
493   //
494   // If we only have implicit uses of flat_scr on flat instructions, it is not
495   // really needed.
496   if (Info.UsesFlatScratch && !MFI->hasFlatScratchInit() &&
497       (!hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR) &&
498        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_LO) &&
499        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_HI))) {
500     Info.UsesFlatScratch = false;
501   }
502 
503   Info.HasDynamicallySizedStack = FrameInfo.hasVarSizedObjects();
504   Info.PrivateSegmentSize = FrameInfo.getStackSize();
505 
506 
507   Info.UsesVCC = MRI.isPhysRegUsed(AMDGPU::VCC_LO) ||
508                  MRI.isPhysRegUsed(AMDGPU::VCC_HI);
509 
510   // If there are no calls, MachineRegisterInfo can tell us the used register
511   // count easily.
512 
513   MCPhysReg HighestVGPRReg = AMDGPU::NoRegister;
514   for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) {
515     if (MRI.isPhysRegUsed(Reg)) {
516       HighestVGPRReg = Reg;
517       break;
518     }
519   }
520 
521   MCPhysReg HighestSGPRReg = AMDGPU::NoRegister;
522   for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) {
523     if (MRI.isPhysRegUsed(Reg)) {
524       HighestSGPRReg = Reg;
525       break;
526     }
527   }
528 
529   // We found the maximum register index. They start at 0, so add one to get the
530   // number of registers.
531   Info.NumVGPR = HighestVGPRReg == AMDGPU::NoRegister ? 0 :
532     TRI.getHWRegIndex(HighestVGPRReg) + 1;
533   Info.NumExplicitSGPR = HighestSGPRReg == AMDGPU::NoRegister ? 0 :
534     TRI.getHWRegIndex(HighestSGPRReg) + 1;
535 
536   return Info;
537 }
538 
539 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
540                                         const MachineFunction &MF) {
541   SIFunctionResourceInfo Info = analyzeResourceUsage(MF);
542 
543   ProgInfo.NumVGPR = Info.NumVGPR;
544   ProgInfo.NumSGPR = Info.NumExplicitSGPR;
545   ProgInfo.ScratchSize = Info.PrivateSegmentSize;
546   ProgInfo.VCCUsed = Info.UsesVCC;
547   ProgInfo.FlatUsed = Info.UsesFlatScratch;
548   ProgInfo.DynamicCallStack = Info.HasDynamicallySizedStack || Info.HasRecursion;
549 
550   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
551   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
552   const SIInstrInfo *TII = STM.getInstrInfo();
553   const SIRegisterInfo *RI = &TII->getRegisterInfo();
554 
555   unsigned ExtraSGPRs = getNumExtraSGPRs(STM,
556                                          ProgInfo.VCCUsed,
557                                          ProgInfo.FlatUsed);
558   unsigned ExtraVGPRs = STM.getReservedNumVGPRs(MF);
559 
560   // Check the addressable register limit before we add ExtraSGPRs.
561   if (STM.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
562       !STM.hasSGPRInitBug()) {
563     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
564     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
565       // This can happen due to a compiler bug or when using inline asm.
566       LLVMContext &Ctx = MF.getFunction()->getContext();
567       DiagnosticInfoResourceLimit Diag(*MF.getFunction(),
568                                        "addressable scalar registers",
569                                        ProgInfo.NumSGPR, DS_Error,
570                                        DK_ResourceLimit,
571                                        MaxAddressableNumSGPRs);
572       Ctx.diagnose(Diag);
573       ProgInfo.NumSGPR = MaxAddressableNumSGPRs - 1;
574     }
575   }
576 
577   // Account for extra SGPRs and VGPRs reserved for debugger use.
578   ProgInfo.NumSGPR += ExtraSGPRs;
579   ProgInfo.NumVGPR += ExtraVGPRs;
580 
581   // Adjust number of registers used to meet default/requested minimum/maximum
582   // number of waves per execution unit request.
583   ProgInfo.NumSGPRsForWavesPerEU = std::max(
584     std::max(ProgInfo.NumSGPR, 1u), STM.getMinNumSGPRs(MFI->getMaxWavesPerEU()));
585   ProgInfo.NumVGPRsForWavesPerEU = std::max(
586     std::max(ProgInfo.NumVGPR, 1u), STM.getMinNumVGPRs(MFI->getMaxWavesPerEU()));
587 
588   if (STM.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ||
589       STM.hasSGPRInitBug()) {
590     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
591     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
592       // This can happen due to a compiler bug or when using inline asm to use
593       // the registers which are usually reserved for vcc etc.
594       LLVMContext &Ctx = MF.getFunction()->getContext();
595       DiagnosticInfoResourceLimit Diag(*MF.getFunction(),
596                                        "scalar registers",
597                                        ProgInfo.NumSGPR, DS_Error,
598                                        DK_ResourceLimit,
599                                        MaxAddressableNumSGPRs);
600       Ctx.diagnose(Diag);
601       ProgInfo.NumSGPR = MaxAddressableNumSGPRs;
602       ProgInfo.NumSGPRsForWavesPerEU = MaxAddressableNumSGPRs;
603     }
604   }
605 
606   if (STM.hasSGPRInitBug()) {
607     ProgInfo.NumSGPR =
608         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
609     ProgInfo.NumSGPRsForWavesPerEU =
610         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
611   }
612 
613   if (MFI->getNumUserSGPRs() > STM.getMaxNumUserSGPRs()) {
614     LLVMContext &Ctx = MF.getFunction()->getContext();
615     DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "user SGPRs",
616                                      MFI->getNumUserSGPRs(), DS_Error);
617     Ctx.diagnose(Diag);
618   }
619 
620   if (MFI->getLDSSize() > static_cast<unsigned>(STM.getLocalMemorySize())) {
621     LLVMContext &Ctx = MF.getFunction()->getContext();
622     DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "local memory",
623                                      MFI->getLDSSize(), DS_Error);
624     Ctx.diagnose(Diag);
625   }
626 
627   // SGPRBlocks is actual number of SGPR blocks minus 1.
628   ProgInfo.SGPRBlocks = alignTo(ProgInfo.NumSGPRsForWavesPerEU,
629                                 STM.getSGPREncodingGranule());
630   ProgInfo.SGPRBlocks = ProgInfo.SGPRBlocks / STM.getSGPREncodingGranule() - 1;
631 
632   // VGPRBlocks is actual number of VGPR blocks minus 1.
633   ProgInfo.VGPRBlocks = alignTo(ProgInfo.NumVGPRsForWavesPerEU,
634                                 STM.getVGPREncodingGranule());
635   ProgInfo.VGPRBlocks = ProgInfo.VGPRBlocks / STM.getVGPREncodingGranule() - 1;
636 
637   // Record first reserved VGPR and number of reserved VGPRs.
638   ProgInfo.ReservedVGPRFirst = STM.debuggerReserveRegs() ? ProgInfo.NumVGPR : 0;
639   ProgInfo.ReservedVGPRCount = STM.getReservedNumVGPRs(MF);
640 
641   // Update DebuggerWavefrontPrivateSegmentOffsetSGPR and
642   // DebuggerPrivateSegmentBufferSGPR fields if "amdgpu-debugger-emit-prologue"
643   // attribute was requested.
644   if (STM.debuggerEmitPrologue()) {
645     ProgInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR =
646       RI->getHWRegIndex(MFI->getScratchWaveOffsetReg());
647     ProgInfo.DebuggerPrivateSegmentBufferSGPR =
648       RI->getHWRegIndex(MFI->getScratchRSrcReg());
649   }
650 
651   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
652   // register.
653   ProgInfo.FloatMode = getFPMode(MF);
654 
655   ProgInfo.IEEEMode = STM.enableIEEEBit(MF);
656 
657   // Make clamp modifier on NaN input returns 0.
658   ProgInfo.DX10Clamp = STM.enableDX10Clamp();
659 
660   unsigned LDSAlignShift;
661   if (STM.getGeneration() < SISubtarget::SEA_ISLANDS) {
662     // LDS is allocated in 64 dword blocks.
663     LDSAlignShift = 8;
664   } else {
665     // LDS is allocated in 128 dword blocks.
666     LDSAlignShift = 9;
667   }
668 
669   unsigned LDSSpillSize =
670     MFI->getLDSWaveSpillSize() * MFI->getMaxFlatWorkGroupSize();
671 
672   ProgInfo.LDSSize = MFI->getLDSSize() + LDSSpillSize;
673   ProgInfo.LDSBlocks =
674       alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
675 
676   // Scratch is allocated in 256 dword blocks.
677   unsigned ScratchAlignShift = 10;
678   // We need to program the hardware with the amount of scratch memory that
679   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
680   // scratch memory used per thread.
681   ProgInfo.ScratchBlocks =
682       alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
683               1ULL << ScratchAlignShift) >>
684       ScratchAlignShift;
685 
686   ProgInfo.ComputePGMRSrc1 =
687       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
688       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
689       S_00B848_PRIORITY(ProgInfo.Priority) |
690       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
691       S_00B848_PRIV(ProgInfo.Priv) |
692       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
693       S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
694       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
695 
696   // 0 = X, 1 = XY, 2 = XYZ
697   unsigned TIDIGCompCnt = 0;
698   if (MFI->hasWorkItemIDZ())
699     TIDIGCompCnt = 2;
700   else if (MFI->hasWorkItemIDY())
701     TIDIGCompCnt = 1;
702 
703   ProgInfo.ComputePGMRSrc2 =
704       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
705       S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
706       S_00B84C_TRAP_HANDLER(STM.isTrapHandlerEnabled()) |
707       S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
708       S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
709       S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
710       S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
711       S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
712       S_00B84C_EXCP_EN_MSB(0) |
713       // For AMDHSA, LDS_SIZE must be zero, as it is populated by the CP.
714       S_00B84C_LDS_SIZE(STM.isAmdHsaOS() ? 0 : ProgInfo.LDSBlocks) |
715       S_00B84C_EXCP_EN(0);
716 }
717 
718 static unsigned getRsrcReg(CallingConv::ID CallConv) {
719   switch (CallConv) {
720   default: LLVM_FALLTHROUGH;
721   case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
722   case CallingConv::AMDGPU_HS: return R_00B428_SPI_SHADER_PGM_RSRC1_HS;
723   case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
724   case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
725   case CallingConv::AMDGPU_VS: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
726   }
727 }
728 
729 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
730                                          const SIProgramInfo &CurrentProgramInfo) {
731   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
732   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
733   unsigned RsrcReg = getRsrcReg(MF.getFunction()->getCallingConv());
734 
735   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
736     OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
737 
738     OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc1, 4);
739 
740     OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
741     OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc2, 4);
742 
743     OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
744     OutStreamer->EmitIntValue(S_00B860_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
745 
746     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
747     // 0" comment but I don't see a corresponding field in the register spec.
748   } else {
749     OutStreamer->EmitIntValue(RsrcReg, 4);
750     OutStreamer->EmitIntValue(S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
751                               S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks), 4);
752     if (STM.isVGPRSpillingEnabled(*MF.getFunction())) {
753       OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
754       OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
755     }
756   }
757 
758   if (MF.getFunction()->getCallingConv() == CallingConv::AMDGPU_PS) {
759     OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
760     OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks), 4);
761     OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
762     OutStreamer->EmitIntValue(MFI->getPSInputEnable(), 4);
763     OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
764     OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4);
765   }
766 
767   OutStreamer->EmitIntValue(R_SPILLED_SGPRS, 4);
768   OutStreamer->EmitIntValue(MFI->getNumSpilledSGPRs(), 4);
769   OutStreamer->EmitIntValue(R_SPILLED_VGPRS, 4);
770   OutStreamer->EmitIntValue(MFI->getNumSpilledVGPRs(), 4);
771 }
772 
773 // This is supposed to be log2(Size)
774 static amd_element_byte_size_t getElementByteSizeValue(unsigned Size) {
775   switch (Size) {
776   case 4:
777     return AMD_ELEMENT_4_BYTES;
778   case 8:
779     return AMD_ELEMENT_8_BYTES;
780   case 16:
781     return AMD_ELEMENT_16_BYTES;
782   default:
783     llvm_unreachable("invalid private_element_size");
784   }
785 }
786 
787 void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out,
788                                         const SIProgramInfo &CurrentProgramInfo,
789                                         const MachineFunction &MF) const {
790   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
791   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
792 
793   AMDGPU::initDefaultAMDKernelCodeT(Out, STM.getFeatureBits());
794 
795   Out.compute_pgm_resource_registers =
796       CurrentProgramInfo.ComputePGMRSrc1 |
797       (CurrentProgramInfo.ComputePGMRSrc2 << 32);
798   Out.code_properties = AMD_CODE_PROPERTY_IS_PTR64;
799 
800   if (CurrentProgramInfo.DynamicCallStack)
801     Out.code_properties |= AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK;
802 
803   AMD_HSA_BITS_SET(Out.code_properties,
804                    AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE,
805                    getElementByteSizeValue(STM.getMaxPrivateElementSize()));
806 
807   if (MFI->hasPrivateSegmentBuffer()) {
808     Out.code_properties |=
809       AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
810   }
811 
812   if (MFI->hasDispatchPtr())
813     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
814 
815   if (MFI->hasQueuePtr())
816     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
817 
818   if (MFI->hasKernargSegmentPtr())
819     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
820 
821   if (MFI->hasDispatchID())
822     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
823 
824   if (MFI->hasFlatScratchInit())
825     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
826 
827   if (MFI->hasGridWorkgroupCountX()) {
828     Out.code_properties |=
829       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X;
830   }
831 
832   if (MFI->hasGridWorkgroupCountY()) {
833     Out.code_properties |=
834       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y;
835   }
836 
837   if (MFI->hasGridWorkgroupCountZ()) {
838     Out.code_properties |=
839       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z;
840   }
841 
842   if (MFI->hasDispatchPtr())
843     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
844 
845   if (STM.debuggerSupported())
846     Out.code_properties |= AMD_CODE_PROPERTY_IS_DEBUG_SUPPORTED;
847 
848   if (STM.isXNACKEnabled())
849     Out.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED;
850 
851   // FIXME: Should use getKernArgSize
852   Out.kernarg_segment_byte_size =
853     STM.getKernArgSegmentSize(MF, MFI->getABIArgOffset());
854   Out.wavefront_sgpr_count = CurrentProgramInfo.NumSGPR;
855   Out.workitem_vgpr_count = CurrentProgramInfo.NumVGPR;
856   Out.workitem_private_segment_byte_size = CurrentProgramInfo.ScratchSize;
857   Out.workgroup_group_segment_byte_size = CurrentProgramInfo.LDSSize;
858   Out.reserved_vgpr_first = CurrentProgramInfo.ReservedVGPRFirst;
859   Out.reserved_vgpr_count = CurrentProgramInfo.ReservedVGPRCount;
860 
861   // These alignment values are specified in powers of two, so alignment =
862   // 2^n.  The minimum alignment is 2^4 = 16.
863   Out.kernarg_segment_alignment = std::max((size_t)4,
864       countTrailingZeros(MFI->getMaxKernArgAlign()));
865 
866   if (STM.debuggerEmitPrologue()) {
867     Out.debug_wavefront_private_segment_offset_sgpr =
868       CurrentProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR;
869     Out.debug_private_segment_buffer_sgpr =
870       CurrentProgramInfo.DebuggerPrivateSegmentBufferSGPR;
871   }
872 }
873 
874 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
875                                        unsigned AsmVariant,
876                                        const char *ExtraCode, raw_ostream &O) {
877   if (ExtraCode && ExtraCode[0]) {
878     if (ExtraCode[1] != 0)
879       return true; // Unknown modifier.
880 
881     switch (ExtraCode[0]) {
882     default:
883       // See if this is a generic print operand
884       return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
885     case 'r':
886       break;
887     }
888   }
889 
890   AMDGPUInstPrinter::printRegOperand(MI->getOperand(OpNo).getReg(), O,
891                    *TM.getSubtargetImpl(*MF->getFunction())->getRegisterInfo());
892   return false;
893 }
894