1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU assembly printer  -------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
15 //
16 //===----------------------------------------------------------------------===//
17 //
18 
19 #include "AMDGPUAsmPrinter.h"
20 #include "AMDGPU.h"
21 #include "AMDGPUSubtarget.h"
22 #include "AMDGPUTargetMachine.h"
23 #include "InstPrinter/AMDGPUInstPrinter.h"
24 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
25 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
26 #include "R600AsmPrinter.h"
27 #include "R600Defines.h"
28 #include "R600MachineFunctionInfo.h"
29 #include "R600RegisterInfo.h"
30 #include "SIDefines.h"
31 #include "SIInstrInfo.h"
32 #include "SIMachineFunctionInfo.h"
33 #include "SIRegisterInfo.h"
34 #include "Utils/AMDGPUBaseInfo.h"
35 #include "llvm/BinaryFormat/ELF.h"
36 #include "llvm/CodeGen/MachineFrameInfo.h"
37 #include "llvm/IR/DiagnosticInfo.h"
38 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCSectionELF.h"
40 #include "llvm/MC/MCStreamer.h"
41 #include "llvm/Support/AMDGPUMetadata.h"
42 #include "llvm/Support/MathExtras.h"
43 #include "llvm/Support/TargetParser.h"
44 #include "llvm/Support/TargetRegistry.h"
45 #include "llvm/Target/TargetLoweringObjectFile.h"
46 
47 using namespace llvm;
48 using namespace llvm::AMDGPU;
49 
50 // TODO: This should get the default rounding mode from the kernel. We just set
51 // the default here, but this could change if the OpenCL rounding mode pragmas
52 // are used.
53 //
54 // The denormal mode here should match what is reported by the OpenCL runtime
55 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
56 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
57 //
58 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
59 // precision, and leaves single precision to flush all and does not report
60 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
61 // CL_FP_DENORM for both.
62 //
63 // FIXME: It seems some instructions do not support single precision denormals
64 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
65 // and sin_f32, cos_f32 on most parts).
66 
67 // We want to use these instructions, and using fp32 denormals also causes
68 // instructions to run at the double precision rate for the device so it's
69 // probably best to just report no single precision denormals.
70 static uint32_t getFPMode(const MachineFunction &F) {
71   const GCNSubtarget& ST = F.getSubtarget<GCNSubtarget>();
72   // TODO: Is there any real use for the flush in only / flush out only modes?
73 
74   uint32_t FP32Denormals =
75     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
76 
77   uint32_t FP64Denormals =
78     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
79 
80   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
81          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
82          FP_DENORM_MODE_SP(FP32Denormals) |
83          FP_DENORM_MODE_DP(FP64Denormals);
84 }
85 
86 static AsmPrinter *
87 createAMDGPUAsmPrinterPass(TargetMachine &tm,
88                            std::unique_ptr<MCStreamer> &&Streamer) {
89   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
90 }
91 
92 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
93   TargetRegistry::RegisterAsmPrinter(getTheAMDGPUTarget(),
94                                      llvm::createR600AsmPrinterPass);
95   TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(),
96                                      createAMDGPUAsmPrinterPass);
97 }
98 
99 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
100                                    std::unique_ptr<MCStreamer> Streamer)
101   : AsmPrinter(TM, std::move(Streamer)) {
102 }
103 
104 StringRef AMDGPUAsmPrinter::getPassName() const {
105   return "AMDGPU Assembly Printer";
106 }
107 
108 const MCSubtargetInfo* AMDGPUAsmPrinter::getSTI() const {
109   return TM.getMCSubtargetInfo();
110 }
111 
112 AMDGPUTargetStreamer* AMDGPUAsmPrinter::getTargetStreamer() const {
113   if (!OutStreamer)
114     return nullptr;
115   return static_cast<AMDGPUTargetStreamer*>(OutStreamer->getTargetStreamer());
116 }
117 
118 void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) {
119   if (IsaInfo::hasCodeObjectV3(getSTI())) {
120     std::string ExpectedTarget;
121     raw_string_ostream ExpectedTargetOS(ExpectedTarget);
122     IsaInfo::streamIsaVersion(getSTI(), ExpectedTargetOS);
123 
124     getTargetStreamer()->EmitDirectiveAMDGCNTarget(ExpectedTarget);
125 
126     if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
127       return;
128   }
129 
130   if (TM.getTargetTriple().getOS() != Triple::AMDHSA &&
131       TM.getTargetTriple().getOS() != Triple::AMDPAL)
132     return;
133 
134   if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
135     HSAMetadataStream.begin(M);
136 
137   if (TM.getTargetTriple().getOS() == Triple::AMDPAL)
138     readPALMetadata(M);
139 
140   // HSA emits NT_AMDGPU_HSA_CODE_OBJECT_VERSION for code objects v2.
141   if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
142     getTargetStreamer()->EmitDirectiveHSACodeObjectVersion(2, 1);
143 
144   // HSA and PAL emit NT_AMDGPU_HSA_ISA for code objects v2.
145   IsaVersion Version = getIsaVersion(getSTI()->getCPU());
146   getTargetStreamer()->EmitDirectiveHSACodeObjectISA(
147       Version.Major, Version.Minor, Version.Stepping, "AMD", "AMDGPU");
148 }
149 
150 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
151   // TODO: Add metadata to code object v3.
152   if (IsaInfo::hasCodeObjectV3(getSTI()) &&
153       TM.getTargetTriple().getOS() == Triple::AMDHSA)
154     return;
155 
156   // Following code requires TargetStreamer to be present.
157   if (!getTargetStreamer())
158     return;
159 
160   // Emit ISA Version (NT_AMD_AMDGPU_ISA).
161   std::string ISAVersionString;
162   raw_string_ostream ISAVersionStream(ISAVersionString);
163   IsaInfo::streamIsaVersion(getSTI(), ISAVersionStream);
164   getTargetStreamer()->EmitISAVersion(ISAVersionStream.str());
165 
166   // Emit HSA Metadata (NT_AMD_AMDGPU_HSA_METADATA).
167   if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
168     HSAMetadataStream.end();
169     getTargetStreamer()->EmitHSAMetadata(HSAMetadataStream.getHSAMetadata());
170   }
171 
172   // Emit PAL Metadata (NT_AMD_AMDGPU_PAL_METADATA).
173   if (TM.getTargetTriple().getOS() == Triple::AMDPAL) {
174     // Copy the PAL metadata from the map where we collected it into a vector,
175     // then write it as a .note.
176     PALMD::Metadata PALMetadataVector;
177     for (auto i : PALMetadataMap) {
178       PALMetadataVector.push_back(i.first);
179       PALMetadataVector.push_back(i.second);
180     }
181     getTargetStreamer()->EmitPALMetadata(PALMetadataVector);
182   }
183 }
184 
185 bool AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough(
186   const MachineBasicBlock *MBB) const {
187   if (!AsmPrinter::isBlockOnlyReachableByFallthrough(MBB))
188     return false;
189 
190   if (MBB->empty())
191     return true;
192 
193   // If this is a block implementing a long branch, an expression relative to
194   // the start of the block is needed.  to the start of the block.
195   // XXX - Is there a smarter way to check this?
196   return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
197 }
198 
199 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
200   const SIMachineFunctionInfo &MFI = *MF->getInfo<SIMachineFunctionInfo>();
201   if (!MFI.isEntryFunction())
202     return;
203 
204   const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
205   const Function &F = MF->getFunction();
206   if (!STM.hasCodeObjectV3() && STM.isAmdHsaOrMesa(F) &&
207       (F.getCallingConv() == CallingConv::AMDGPU_KERNEL ||
208        F.getCallingConv() == CallingConv::SPIR_KERNEL)) {
209     amd_kernel_code_t KernelCode;
210     getAmdKernelCode(KernelCode, CurrentProgramInfo, *MF);
211     getTargetStreamer()->EmitAMDKernelCodeT(KernelCode);
212   }
213 
214   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
215     return;
216 
217   if (!STM.hasCodeObjectV3() && STM.isAmdHsaOS())
218     HSAMetadataStream.emitKernel(*MF, CurrentProgramInfo);
219 }
220 
221 void AMDGPUAsmPrinter::EmitFunctionBodyEnd() {
222   const SIMachineFunctionInfo &MFI = *MF->getInfo<SIMachineFunctionInfo>();
223   if (!MFI.isEntryFunction())
224     return;
225   if (!IsaInfo::hasCodeObjectV3(getSTI()) ||
226       TM.getTargetTriple().getOS() != Triple::AMDHSA)
227     return;
228 
229   auto &Streamer = getTargetStreamer()->getStreamer();
230   auto &Context = Streamer.getContext();
231   auto &ObjectFileInfo = *Context.getObjectFileInfo();
232   auto &ReadOnlySection = *ObjectFileInfo.getReadOnlySection();
233 
234   Streamer.PushSection();
235   Streamer.SwitchSection(&ReadOnlySection);
236 
237   // CP microcode requires the kernel descriptor to be allocated on 64 byte
238   // alignment.
239   Streamer.EmitValueToAlignment(64, 0, 1, 0);
240   if (ReadOnlySection.getAlignment() < 64)
241     ReadOnlySection.setAlignment(64);
242 
243   SmallString<128> KernelName;
244   getNameWithPrefix(KernelName, &MF->getFunction());
245   getTargetStreamer()->EmitAmdhsaKernelDescriptor(
246       *getSTI(), KernelName, getAmdhsaKernelDescriptor(*MF, CurrentProgramInfo),
247       CurrentProgramInfo.NumVGPRsForWavesPerEU,
248       CurrentProgramInfo.NumSGPRsForWavesPerEU -
249           IsaInfo::getNumExtraSGPRs(getSTI(),
250                                     CurrentProgramInfo.VCCUsed,
251                                     CurrentProgramInfo.FlatUsed),
252       CurrentProgramInfo.VCCUsed, CurrentProgramInfo.FlatUsed,
253       hasXNACK(*getSTI()));
254 
255   Streamer.PopSection();
256 }
257 
258 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
259   if (IsaInfo::hasCodeObjectV3(getSTI()) &&
260       TM.getTargetTriple().getOS() == Triple::AMDHSA) {
261     AsmPrinter::EmitFunctionEntryLabel();
262     return;
263   }
264 
265   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
266   const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
267   if (MFI->isEntryFunction() && STM.isAmdHsaOrMesa(MF->getFunction())) {
268     SmallString<128> SymbolName;
269     getNameWithPrefix(SymbolName, &MF->getFunction()),
270     getTargetStreamer()->EmitAMDGPUSymbolType(
271         SymbolName, ELF::STT_AMDGPU_HSA_KERNEL);
272   }
273   const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>();
274   if (STI.dumpCode()) {
275     // Disassemble function name label to text.
276     DisasmLines.push_back(MF->getName().str() + ":");
277     DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size());
278     HexLines.push_back("");
279   }
280 
281   AsmPrinter::EmitFunctionEntryLabel();
282 }
283 
284 void AMDGPUAsmPrinter::EmitBasicBlockStart(const MachineBasicBlock &MBB) const {
285   const GCNSubtarget &STI = MBB.getParent()->getSubtarget<GCNSubtarget>();
286   if (STI.dumpCode() && !isBlockOnlyReachableByFallthrough(&MBB)) {
287     // Write a line for the basic block label if it is not only fallthrough.
288     DisasmLines.push_back(
289         (Twine("BB") + Twine(getFunctionNumber())
290          + "_" + Twine(MBB.getNumber()) + ":").str());
291     DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size());
292     HexLines.push_back("");
293   }
294   AsmPrinter::EmitBasicBlockStart(MBB);
295 }
296 
297 void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
298 
299   // Group segment variables aren't emitted in HSA.
300   if (AMDGPU::isGroupSegment(GV))
301     return;
302 
303   AsmPrinter::EmitGlobalVariable(GV);
304 }
305 
306 bool AMDGPUAsmPrinter::doFinalization(Module &M) {
307   CallGraphResourceInfo.clear();
308   return AsmPrinter::doFinalization(M);
309 }
310 
311 // For the amdpal OS type, read the amdgpu.pal.metadata supplied by the
312 // frontend into our PALMetadataMap, ready for per-function modification.  It
313 // is a NamedMD containing an MDTuple containing a number of MDNodes each of
314 // which is an integer value, and each two integer values forms a key=value
315 // pair that we store as PALMetadataMap[key]=value in the map.
316 void AMDGPUAsmPrinter::readPALMetadata(Module &M) {
317   auto NamedMD = M.getNamedMetadata("amdgpu.pal.metadata");
318   if (!NamedMD || !NamedMD->getNumOperands())
319     return;
320   auto Tuple = dyn_cast<MDTuple>(NamedMD->getOperand(0));
321   if (!Tuple)
322     return;
323   for (unsigned I = 0, E = Tuple->getNumOperands() & -2; I != E; I += 2) {
324     auto Key = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I));
325     auto Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I + 1));
326     if (!Key || !Val)
327       continue;
328     PALMetadataMap[Key->getZExtValue()] = Val->getZExtValue();
329   }
330 }
331 
332 // Print comments that apply to both callable functions and entry points.
333 void AMDGPUAsmPrinter::emitCommonFunctionComments(
334   uint32_t NumVGPR,
335   uint32_t NumSGPR,
336   uint64_t ScratchSize,
337   uint64_t CodeSize,
338   const AMDGPUMachineFunction *MFI) {
339   OutStreamer->emitRawComment(" codeLenInByte = " + Twine(CodeSize), false);
340   OutStreamer->emitRawComment(" NumSgprs: " + Twine(NumSGPR), false);
341   OutStreamer->emitRawComment(" NumVgprs: " + Twine(NumVGPR), false);
342   OutStreamer->emitRawComment(" ScratchSize: " + Twine(ScratchSize), false);
343   OutStreamer->emitRawComment(" MemoryBound: " + Twine(MFI->isMemoryBound()),
344                               false);
345 }
346 
347 uint16_t AMDGPUAsmPrinter::getAmdhsaKernelCodeProperties(
348     const MachineFunction &MF) const {
349   const SIMachineFunctionInfo &MFI = *MF.getInfo<SIMachineFunctionInfo>();
350   uint16_t KernelCodeProperties = 0;
351 
352   if (MFI.hasPrivateSegmentBuffer()) {
353     KernelCodeProperties |=
354         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
355   }
356   if (MFI.hasDispatchPtr()) {
357     KernelCodeProperties |=
358         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
359   }
360   if (MFI.hasQueuePtr()) {
361     KernelCodeProperties |=
362         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
363   }
364   if (MFI.hasKernargSegmentPtr()) {
365     KernelCodeProperties |=
366         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
367   }
368   if (MFI.hasDispatchID()) {
369     KernelCodeProperties |=
370         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
371   }
372   if (MFI.hasFlatScratchInit()) {
373     KernelCodeProperties |=
374         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
375   }
376 
377   return KernelCodeProperties;
378 }
379 
380 amdhsa::kernel_descriptor_t AMDGPUAsmPrinter::getAmdhsaKernelDescriptor(
381     const MachineFunction &MF,
382     const SIProgramInfo &PI) const {
383   amdhsa::kernel_descriptor_t KernelDescriptor;
384   memset(&KernelDescriptor, 0x0, sizeof(KernelDescriptor));
385 
386   assert(isUInt<32>(PI.ScratchSize));
387   assert(isUInt<32>(PI.ComputePGMRSrc1));
388   assert(isUInt<32>(PI.ComputePGMRSrc2));
389 
390   KernelDescriptor.group_segment_fixed_size = PI.LDSSize;
391   KernelDescriptor.private_segment_fixed_size = PI.ScratchSize;
392   KernelDescriptor.compute_pgm_rsrc1 = PI.ComputePGMRSrc1;
393   KernelDescriptor.compute_pgm_rsrc2 = PI.ComputePGMRSrc2;
394   KernelDescriptor.kernel_code_properties = getAmdhsaKernelCodeProperties(MF);
395 
396   return KernelDescriptor;
397 }
398 
399 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
400   CurrentProgramInfo = SIProgramInfo();
401 
402   const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
403 
404   // The starting address of all shader programs must be 256 bytes aligned.
405   // Regular functions just need the basic required instruction alignment.
406   MF.setAlignment(MFI->isEntryFunction() ? 8 : 2);
407 
408   SetupMachineFunction(MF);
409 
410   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
411   MCContext &Context = getObjFileLowering().getContext();
412   // FIXME: This should be an explicit check for Mesa.
413   if (!STM.isAmdHsaOS() && !STM.isAmdPalOS()) {
414     MCSectionELF *ConfigSection =
415         Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
416     OutStreamer->SwitchSection(ConfigSection);
417   }
418 
419   if (MFI->isEntryFunction()) {
420     getSIProgramInfo(CurrentProgramInfo, MF);
421   } else {
422     auto I = CallGraphResourceInfo.insert(
423       std::make_pair(&MF.getFunction(), SIFunctionResourceInfo()));
424     SIFunctionResourceInfo &Info = I.first->second;
425     assert(I.second && "should only be called once per function");
426     Info = analyzeResourceUsage(MF);
427   }
428 
429   if (STM.isAmdPalOS())
430     EmitPALMetadata(MF, CurrentProgramInfo);
431   else if (!STM.isAmdHsaOS()) {
432     EmitProgramInfoSI(MF, CurrentProgramInfo);
433   }
434 
435   DisasmLines.clear();
436   HexLines.clear();
437   DisasmLineMaxLen = 0;
438 
439   EmitFunctionBody();
440 
441   if (isVerbose()) {
442     MCSectionELF *CommentSection =
443         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
444     OutStreamer->SwitchSection(CommentSection);
445 
446     if (!MFI->isEntryFunction()) {
447       OutStreamer->emitRawComment(" Function info:", false);
448       SIFunctionResourceInfo &Info = CallGraphResourceInfo[&MF.getFunction()];
449       emitCommonFunctionComments(
450         Info.NumVGPR,
451         Info.getTotalNumSGPRs(MF.getSubtarget<GCNSubtarget>()),
452         Info.PrivateSegmentSize,
453         getFunctionCodeSize(MF), MFI);
454       return false;
455     }
456 
457     OutStreamer->emitRawComment(" Kernel info:", false);
458     emitCommonFunctionComments(CurrentProgramInfo.NumVGPR,
459                                CurrentProgramInfo.NumSGPR,
460                                CurrentProgramInfo.ScratchSize,
461                                getFunctionCodeSize(MF), MFI);
462 
463     OutStreamer->emitRawComment(
464       " FloatMode: " + Twine(CurrentProgramInfo.FloatMode), false);
465     OutStreamer->emitRawComment(
466       " IeeeMode: " + Twine(CurrentProgramInfo.IEEEMode), false);
467     OutStreamer->emitRawComment(
468       " LDSByteSize: " + Twine(CurrentProgramInfo.LDSSize) +
469       " bytes/workgroup (compile time only)", false);
470 
471     OutStreamer->emitRawComment(
472       " SGPRBlocks: " + Twine(CurrentProgramInfo.SGPRBlocks), false);
473     OutStreamer->emitRawComment(
474       " VGPRBlocks: " + Twine(CurrentProgramInfo.VGPRBlocks), false);
475 
476     OutStreamer->emitRawComment(
477       " NumSGPRsForWavesPerEU: " +
478       Twine(CurrentProgramInfo.NumSGPRsForWavesPerEU), false);
479     OutStreamer->emitRawComment(
480       " NumVGPRsForWavesPerEU: " +
481       Twine(CurrentProgramInfo.NumVGPRsForWavesPerEU), false);
482 
483     OutStreamer->emitRawComment(
484       " WaveLimiterHint : " + Twine(MFI->needsWaveLimiter()), false);
485 
486     if (MF.getSubtarget<GCNSubtarget>().debuggerEmitPrologue()) {
487       OutStreamer->emitRawComment(
488         " DebuggerWavefrontPrivateSegmentOffsetSGPR: s" +
489         Twine(CurrentProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR), false);
490       OutStreamer->emitRawComment(
491         " DebuggerPrivateSegmentBufferSGPR: s" +
492         Twine(CurrentProgramInfo.DebuggerPrivateSegmentBufferSGPR), false);
493     }
494 
495     OutStreamer->emitRawComment(
496       " COMPUTE_PGM_RSRC2:USER_SGPR: " +
497       Twine(G_00B84C_USER_SGPR(CurrentProgramInfo.ComputePGMRSrc2)), false);
498     OutStreamer->emitRawComment(
499       " COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
500       Twine(G_00B84C_TRAP_HANDLER(CurrentProgramInfo.ComputePGMRSrc2)), false);
501     OutStreamer->emitRawComment(
502       " COMPUTE_PGM_RSRC2:TGID_X_EN: " +
503       Twine(G_00B84C_TGID_X_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
504     OutStreamer->emitRawComment(
505       " COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
506       Twine(G_00B84C_TGID_Y_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
507     OutStreamer->emitRawComment(
508       " COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
509       Twine(G_00B84C_TGID_Z_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
510     OutStreamer->emitRawComment(
511       " COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
512       Twine(G_00B84C_TIDIG_COMP_CNT(CurrentProgramInfo.ComputePGMRSrc2)),
513       false);
514   }
515 
516   if (STM.dumpCode()) {
517 
518     OutStreamer->SwitchSection(
519         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
520 
521     for (size_t i = 0; i < DisasmLines.size(); ++i) {
522       std::string Comment = "\n";
523       if (!HexLines[i].empty()) {
524         Comment = std::string(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
525         Comment += " ; " + HexLines[i] + "\n";
526       }
527 
528       OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
529       OutStreamer->EmitBytes(StringRef(Comment));
530     }
531   }
532 
533   return false;
534 }
535 
536 uint64_t AMDGPUAsmPrinter::getFunctionCodeSize(const MachineFunction &MF) const {
537   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
538   const SIInstrInfo *TII = STM.getInstrInfo();
539 
540   uint64_t CodeSize = 0;
541 
542   for (const MachineBasicBlock &MBB : MF) {
543     for (const MachineInstr &MI : MBB) {
544       // TODO: CodeSize should account for multiple functions.
545 
546       // TODO: Should we count size of debug info?
547       if (MI.isDebugInstr())
548         continue;
549 
550       CodeSize += TII->getInstSizeInBytes(MI);
551     }
552   }
553 
554   return CodeSize;
555 }
556 
557 static bool hasAnyNonFlatUseOfReg(const MachineRegisterInfo &MRI,
558                                   const SIInstrInfo &TII,
559                                   unsigned Reg) {
560   for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) {
561     if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent()))
562       return true;
563   }
564 
565   return false;
566 }
567 
568 int32_t AMDGPUAsmPrinter::SIFunctionResourceInfo::getTotalNumSGPRs(
569   const GCNSubtarget &ST) const {
570   return NumExplicitSGPR + IsaInfo::getNumExtraSGPRs(&ST,
571                                                      UsesVCC, UsesFlatScratch);
572 }
573 
574 AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
575   const MachineFunction &MF) const {
576   SIFunctionResourceInfo Info;
577 
578   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
579   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
580   const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
581   const MachineRegisterInfo &MRI = MF.getRegInfo();
582   const SIInstrInfo *TII = ST.getInstrInfo();
583   const SIRegisterInfo &TRI = TII->getRegisterInfo();
584 
585   Info.UsesFlatScratch = MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_LO) ||
586                          MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_HI);
587 
588   // Even if FLAT_SCRATCH is implicitly used, it has no effect if flat
589   // instructions aren't used to access the scratch buffer. Inline assembly may
590   // need it though.
591   //
592   // If we only have implicit uses of flat_scr on flat instructions, it is not
593   // really needed.
594   if (Info.UsesFlatScratch && !MFI->hasFlatScratchInit() &&
595       (!hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR) &&
596        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_LO) &&
597        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_HI))) {
598     Info.UsesFlatScratch = false;
599   }
600 
601   Info.HasDynamicallySizedStack = FrameInfo.hasVarSizedObjects();
602   Info.PrivateSegmentSize = FrameInfo.getStackSize();
603   if (MFI->isStackRealigned())
604     Info.PrivateSegmentSize += FrameInfo.getMaxAlignment();
605 
606 
607   Info.UsesVCC = MRI.isPhysRegUsed(AMDGPU::VCC_LO) ||
608                  MRI.isPhysRegUsed(AMDGPU::VCC_HI);
609 
610   // If there are no calls, MachineRegisterInfo can tell us the used register
611   // count easily.
612   // A tail call isn't considered a call for MachineFrameInfo's purposes.
613   if (!FrameInfo.hasCalls() && !FrameInfo.hasTailCall()) {
614     MCPhysReg HighestVGPRReg = AMDGPU::NoRegister;
615     for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) {
616       if (MRI.isPhysRegUsed(Reg)) {
617         HighestVGPRReg = Reg;
618         break;
619       }
620     }
621 
622     MCPhysReg HighestSGPRReg = AMDGPU::NoRegister;
623     for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) {
624       if (MRI.isPhysRegUsed(Reg)) {
625         HighestSGPRReg = Reg;
626         break;
627       }
628     }
629 
630     // We found the maximum register index. They start at 0, so add one to get the
631     // number of registers.
632     Info.NumVGPR = HighestVGPRReg == AMDGPU::NoRegister ? 0 :
633       TRI.getHWRegIndex(HighestVGPRReg) + 1;
634     Info.NumExplicitSGPR = HighestSGPRReg == AMDGPU::NoRegister ? 0 :
635       TRI.getHWRegIndex(HighestSGPRReg) + 1;
636 
637     return Info;
638   }
639 
640   int32_t MaxVGPR = -1;
641   int32_t MaxSGPR = -1;
642   uint64_t CalleeFrameSize = 0;
643 
644   for (const MachineBasicBlock &MBB : MF) {
645     for (const MachineInstr &MI : MBB) {
646       // TODO: Check regmasks? Do they occur anywhere except calls?
647       for (const MachineOperand &MO : MI.operands()) {
648         unsigned Width = 0;
649         bool IsSGPR = false;
650 
651         if (!MO.isReg())
652           continue;
653 
654         unsigned Reg = MO.getReg();
655         switch (Reg) {
656         case AMDGPU::EXEC:
657         case AMDGPU::EXEC_LO:
658         case AMDGPU::EXEC_HI:
659         case AMDGPU::SCC:
660         case AMDGPU::M0:
661         case AMDGPU::SRC_SHARED_BASE:
662         case AMDGPU::SRC_SHARED_LIMIT:
663         case AMDGPU::SRC_PRIVATE_BASE:
664         case AMDGPU::SRC_PRIVATE_LIMIT:
665           continue;
666 
667         case AMDGPU::NoRegister:
668           assert(MI.isDebugInstr());
669           continue;
670 
671         case AMDGPU::VCC:
672         case AMDGPU::VCC_LO:
673         case AMDGPU::VCC_HI:
674           Info.UsesVCC = true;
675           continue;
676 
677         case AMDGPU::FLAT_SCR:
678         case AMDGPU::FLAT_SCR_LO:
679         case AMDGPU::FLAT_SCR_HI:
680           continue;
681 
682         case AMDGPU::XNACK_MASK:
683         case AMDGPU::XNACK_MASK_LO:
684         case AMDGPU::XNACK_MASK_HI:
685           llvm_unreachable("xnack_mask registers should not be used");
686 
687         case AMDGPU::TBA:
688         case AMDGPU::TBA_LO:
689         case AMDGPU::TBA_HI:
690         case AMDGPU::TMA:
691         case AMDGPU::TMA_LO:
692         case AMDGPU::TMA_HI:
693           llvm_unreachable("trap handler registers should not be used");
694 
695         default:
696           break;
697         }
698 
699         if (AMDGPU::SReg_32RegClass.contains(Reg)) {
700           assert(!AMDGPU::TTMP_32RegClass.contains(Reg) &&
701                  "trap handler registers should not be used");
702           IsSGPR = true;
703           Width = 1;
704         } else if (AMDGPU::VGPR_32RegClass.contains(Reg)) {
705           IsSGPR = false;
706           Width = 1;
707         } else if (AMDGPU::SReg_64RegClass.contains(Reg)) {
708           assert(!AMDGPU::TTMP_64RegClass.contains(Reg) &&
709                  "trap handler registers should not be used");
710           IsSGPR = true;
711           Width = 2;
712         } else if (AMDGPU::VReg_64RegClass.contains(Reg)) {
713           IsSGPR = false;
714           Width = 2;
715         } else if (AMDGPU::VReg_96RegClass.contains(Reg)) {
716           IsSGPR = false;
717           Width = 3;
718         } else if (AMDGPU::SReg_128RegClass.contains(Reg)) {
719           assert(!AMDGPU::TTMP_128RegClass.contains(Reg) &&
720             "trap handler registers should not be used");
721           IsSGPR = true;
722           Width = 4;
723         } else if (AMDGPU::VReg_128RegClass.contains(Reg)) {
724           IsSGPR = false;
725           Width = 4;
726         } else if (AMDGPU::SReg_256RegClass.contains(Reg)) {
727           assert(!AMDGPU::TTMP_256RegClass.contains(Reg) &&
728             "trap handler registers should not be used");
729           IsSGPR = true;
730           Width = 8;
731         } else if (AMDGPU::VReg_256RegClass.contains(Reg)) {
732           IsSGPR = false;
733           Width = 8;
734         } else if (AMDGPU::SReg_512RegClass.contains(Reg)) {
735           assert(!AMDGPU::TTMP_512RegClass.contains(Reg) &&
736             "trap handler registers should not be used");
737           IsSGPR = true;
738           Width = 16;
739         } else if (AMDGPU::VReg_512RegClass.contains(Reg)) {
740           IsSGPR = false;
741           Width = 16;
742         } else {
743           llvm_unreachable("Unknown register class");
744         }
745         unsigned HWReg = TRI.getHWRegIndex(Reg);
746         int MaxUsed = HWReg + Width - 1;
747         if (IsSGPR) {
748           MaxSGPR = MaxUsed > MaxSGPR ? MaxUsed : MaxSGPR;
749         } else {
750           MaxVGPR = MaxUsed > MaxVGPR ? MaxUsed : MaxVGPR;
751         }
752       }
753 
754       if (MI.isCall()) {
755         // Pseudo used just to encode the underlying global. Is there a better
756         // way to track this?
757 
758         const MachineOperand *CalleeOp
759           = TII->getNamedOperand(MI, AMDGPU::OpName::callee);
760         const Function *Callee = cast<Function>(CalleeOp->getGlobal());
761         if (Callee->isDeclaration()) {
762           // If this is a call to an external function, we can't do much. Make
763           // conservative guesses.
764 
765           // 48 SGPRs - vcc, - flat_scr, -xnack
766           int MaxSGPRGuess =
767               47 - IsaInfo::getNumExtraSGPRs(getSTI(), true,
768                                              ST.hasFlatAddressSpace());
769           MaxSGPR = std::max(MaxSGPR, MaxSGPRGuess);
770           MaxVGPR = std::max(MaxVGPR, 23);
771 
772           CalleeFrameSize = std::max(CalleeFrameSize, UINT64_C(16384));
773           Info.UsesVCC = true;
774           Info.UsesFlatScratch = ST.hasFlatAddressSpace();
775           Info.HasDynamicallySizedStack = true;
776         } else {
777           // We force CodeGen to run in SCC order, so the callee's register
778           // usage etc. should be the cumulative usage of all callees.
779           auto I = CallGraphResourceInfo.find(Callee);
780           assert(I != CallGraphResourceInfo.end() &&
781                  "callee should have been handled before caller");
782 
783           MaxSGPR = std::max(I->second.NumExplicitSGPR - 1, MaxSGPR);
784           MaxVGPR = std::max(I->second.NumVGPR - 1, MaxVGPR);
785           CalleeFrameSize
786             = std::max(I->second.PrivateSegmentSize, CalleeFrameSize);
787           Info.UsesVCC |= I->second.UsesVCC;
788           Info.UsesFlatScratch |= I->second.UsesFlatScratch;
789           Info.HasDynamicallySizedStack |= I->second.HasDynamicallySizedStack;
790           Info.HasRecursion |= I->second.HasRecursion;
791         }
792 
793         if (!Callee->doesNotRecurse())
794           Info.HasRecursion = true;
795       }
796     }
797   }
798 
799   Info.NumExplicitSGPR = MaxSGPR + 1;
800   Info.NumVGPR = MaxVGPR + 1;
801   Info.PrivateSegmentSize += CalleeFrameSize;
802 
803   return Info;
804 }
805 
806 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
807                                         const MachineFunction &MF) {
808   SIFunctionResourceInfo Info = analyzeResourceUsage(MF);
809 
810   ProgInfo.NumVGPR = Info.NumVGPR;
811   ProgInfo.NumSGPR = Info.NumExplicitSGPR;
812   ProgInfo.ScratchSize = Info.PrivateSegmentSize;
813   ProgInfo.VCCUsed = Info.UsesVCC;
814   ProgInfo.FlatUsed = Info.UsesFlatScratch;
815   ProgInfo.DynamicCallStack = Info.HasDynamicallySizedStack || Info.HasRecursion;
816 
817   if (!isUInt<32>(ProgInfo.ScratchSize)) {
818     DiagnosticInfoStackSize DiagStackSize(MF.getFunction(),
819                                           ProgInfo.ScratchSize, DS_Error);
820     MF.getFunction().getContext().diagnose(DiagStackSize);
821   }
822 
823   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
824   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
825   const SIInstrInfo *TII = STM.getInstrInfo();
826   const SIRegisterInfo *RI = &TII->getRegisterInfo();
827 
828   // TODO(scott.linder): The calculations related to SGPR/VGPR blocks are
829   // duplicated in part in AMDGPUAsmParser::calculateGPRBlocks, and could be
830   // unified.
831   unsigned ExtraSGPRs = IsaInfo::getNumExtraSGPRs(
832       getSTI(), ProgInfo.VCCUsed, ProgInfo.FlatUsed);
833 
834   // Check the addressable register limit before we add ExtraSGPRs.
835   if (STM.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
836       !STM.hasSGPRInitBug()) {
837     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
838     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
839       // This can happen due to a compiler bug or when using inline asm.
840       LLVMContext &Ctx = MF.getFunction().getContext();
841       DiagnosticInfoResourceLimit Diag(MF.getFunction(),
842                                        "addressable scalar registers",
843                                        ProgInfo.NumSGPR, DS_Error,
844                                        DK_ResourceLimit,
845                                        MaxAddressableNumSGPRs);
846       Ctx.diagnose(Diag);
847       ProgInfo.NumSGPR = MaxAddressableNumSGPRs - 1;
848     }
849   }
850 
851   // Account for extra SGPRs and VGPRs reserved for debugger use.
852   ProgInfo.NumSGPR += ExtraSGPRs;
853 
854   // Ensure there are enough SGPRs and VGPRs for wave dispatch, where wave
855   // dispatch registers are function args.
856   unsigned WaveDispatchNumSGPR = 0, WaveDispatchNumVGPR = 0;
857   for (auto &Arg : MF.getFunction().args()) {
858     unsigned NumRegs = (Arg.getType()->getPrimitiveSizeInBits() + 31) / 32;
859     if (Arg.hasAttribute(Attribute::InReg))
860       WaveDispatchNumSGPR += NumRegs;
861     else
862       WaveDispatchNumVGPR += NumRegs;
863   }
864   ProgInfo.NumSGPR = std::max(ProgInfo.NumSGPR, WaveDispatchNumSGPR);
865   ProgInfo.NumVGPR = std::max(ProgInfo.NumVGPR, WaveDispatchNumVGPR);
866 
867   // Adjust number of registers used to meet default/requested minimum/maximum
868   // number of waves per execution unit request.
869   ProgInfo.NumSGPRsForWavesPerEU = std::max(
870     std::max(ProgInfo.NumSGPR, 1u), STM.getMinNumSGPRs(MFI->getMaxWavesPerEU()));
871   ProgInfo.NumVGPRsForWavesPerEU = std::max(
872     std::max(ProgInfo.NumVGPR, 1u), STM.getMinNumVGPRs(MFI->getMaxWavesPerEU()));
873 
874   if (STM.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ||
875       STM.hasSGPRInitBug()) {
876     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
877     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
878       // This can happen due to a compiler bug or when using inline asm to use
879       // the registers which are usually reserved for vcc etc.
880       LLVMContext &Ctx = MF.getFunction().getContext();
881       DiagnosticInfoResourceLimit Diag(MF.getFunction(),
882                                        "scalar registers",
883                                        ProgInfo.NumSGPR, DS_Error,
884                                        DK_ResourceLimit,
885                                        MaxAddressableNumSGPRs);
886       Ctx.diagnose(Diag);
887       ProgInfo.NumSGPR = MaxAddressableNumSGPRs;
888       ProgInfo.NumSGPRsForWavesPerEU = MaxAddressableNumSGPRs;
889     }
890   }
891 
892   if (STM.hasSGPRInitBug()) {
893     ProgInfo.NumSGPR =
894         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
895     ProgInfo.NumSGPRsForWavesPerEU =
896         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
897   }
898 
899   if (MFI->getNumUserSGPRs() > STM.getMaxNumUserSGPRs()) {
900     LLVMContext &Ctx = MF.getFunction().getContext();
901     DiagnosticInfoResourceLimit Diag(MF.getFunction(), "user SGPRs",
902                                      MFI->getNumUserSGPRs(), DS_Error);
903     Ctx.diagnose(Diag);
904   }
905 
906   if (MFI->getLDSSize() > static_cast<unsigned>(STM.getLocalMemorySize())) {
907     LLVMContext &Ctx = MF.getFunction().getContext();
908     DiagnosticInfoResourceLimit Diag(MF.getFunction(), "local memory",
909                                      MFI->getLDSSize(), DS_Error);
910     Ctx.diagnose(Diag);
911   }
912 
913   ProgInfo.SGPRBlocks = IsaInfo::getNumSGPRBlocks(
914       &STM, ProgInfo.NumSGPRsForWavesPerEU);
915   ProgInfo.VGPRBlocks = IsaInfo::getNumVGPRBlocks(
916       &STM, ProgInfo.NumVGPRsForWavesPerEU);
917 
918   // Update DebuggerWavefrontPrivateSegmentOffsetSGPR and
919   // DebuggerPrivateSegmentBufferSGPR fields if "amdgpu-debugger-emit-prologue"
920   // attribute was requested.
921   if (STM.debuggerEmitPrologue()) {
922     ProgInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR =
923       RI->getHWRegIndex(MFI->getScratchWaveOffsetReg());
924     ProgInfo.DebuggerPrivateSegmentBufferSGPR =
925       RI->getHWRegIndex(MFI->getScratchRSrcReg());
926   }
927 
928   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
929   // register.
930   ProgInfo.FloatMode = getFPMode(MF);
931 
932   ProgInfo.IEEEMode = STM.enableIEEEBit(MF);
933 
934   // Make clamp modifier on NaN input returns 0.
935   ProgInfo.DX10Clamp = STM.enableDX10Clamp();
936 
937   unsigned LDSAlignShift;
938   if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
939     // LDS is allocated in 64 dword blocks.
940     LDSAlignShift = 8;
941   } else {
942     // LDS is allocated in 128 dword blocks.
943     LDSAlignShift = 9;
944   }
945 
946   unsigned LDSSpillSize =
947     MFI->getLDSWaveSpillSize() * MFI->getMaxFlatWorkGroupSize();
948 
949   ProgInfo.LDSSize = MFI->getLDSSize() + LDSSpillSize;
950   ProgInfo.LDSBlocks =
951       alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
952 
953   // Scratch is allocated in 256 dword blocks.
954   unsigned ScratchAlignShift = 10;
955   // We need to program the hardware with the amount of scratch memory that
956   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
957   // scratch memory used per thread.
958   ProgInfo.ScratchBlocks =
959       alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
960               1ULL << ScratchAlignShift) >>
961       ScratchAlignShift;
962 
963   ProgInfo.ComputePGMRSrc1 =
964       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
965       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
966       S_00B848_PRIORITY(ProgInfo.Priority) |
967       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
968       S_00B848_PRIV(ProgInfo.Priv) |
969       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
970       S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
971       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
972 
973   // 0 = X, 1 = XY, 2 = XYZ
974   unsigned TIDIGCompCnt = 0;
975   if (MFI->hasWorkItemIDZ())
976     TIDIGCompCnt = 2;
977   else if (MFI->hasWorkItemIDY())
978     TIDIGCompCnt = 1;
979 
980   ProgInfo.ComputePGMRSrc2 =
981       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
982       S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
983       // For AMDHSA, TRAP_HANDLER must be zero, as it is populated by the CP.
984       S_00B84C_TRAP_HANDLER(STM.isAmdHsaOS() ? 0 : STM.isTrapHandlerEnabled()) |
985       S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
986       S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
987       S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
988       S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
989       S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
990       S_00B84C_EXCP_EN_MSB(0) |
991       // For AMDHSA, LDS_SIZE must be zero, as it is populated by the CP.
992       S_00B84C_LDS_SIZE(STM.isAmdHsaOS() ? 0 : ProgInfo.LDSBlocks) |
993       S_00B84C_EXCP_EN(0);
994 }
995 
996 static unsigned getRsrcReg(CallingConv::ID CallConv) {
997   switch (CallConv) {
998   default: LLVM_FALLTHROUGH;
999   case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
1000   case CallingConv::AMDGPU_LS: return R_00B528_SPI_SHADER_PGM_RSRC1_LS;
1001   case CallingConv::AMDGPU_HS: return R_00B428_SPI_SHADER_PGM_RSRC1_HS;
1002   case CallingConv::AMDGPU_ES: return R_00B328_SPI_SHADER_PGM_RSRC1_ES;
1003   case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
1004   case CallingConv::AMDGPU_VS: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
1005   case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
1006   }
1007 }
1008 
1009 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
1010                                          const SIProgramInfo &CurrentProgramInfo) {
1011   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1012   unsigned RsrcReg = getRsrcReg(MF.getFunction().getCallingConv());
1013 
1014   if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
1015     OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
1016 
1017     OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc1, 4);
1018 
1019     OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
1020     OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc2, 4);
1021 
1022     OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
1023     OutStreamer->EmitIntValue(S_00B860_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
1024 
1025     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
1026     // 0" comment but I don't see a corresponding field in the register spec.
1027   } else {
1028     OutStreamer->EmitIntValue(RsrcReg, 4);
1029     OutStreamer->EmitIntValue(S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
1030                               S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks), 4);
1031     OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
1032     OutStreamer->EmitIntValue(
1033         S_0286E8_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
1034   }
1035 
1036   if (MF.getFunction().getCallingConv() == CallingConv::AMDGPU_PS) {
1037     OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
1038     OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks), 4);
1039     OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
1040     OutStreamer->EmitIntValue(MFI->getPSInputEnable(), 4);
1041     OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
1042     OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4);
1043   }
1044 
1045   OutStreamer->EmitIntValue(R_SPILLED_SGPRS, 4);
1046   OutStreamer->EmitIntValue(MFI->getNumSpilledSGPRs(), 4);
1047   OutStreamer->EmitIntValue(R_SPILLED_VGPRS, 4);
1048   OutStreamer->EmitIntValue(MFI->getNumSpilledVGPRs(), 4);
1049 }
1050 
1051 // This is the equivalent of EmitProgramInfoSI above, but for when the OS type
1052 // is AMDPAL.  It stores each compute/SPI register setting and other PAL
1053 // metadata items into the PALMetadataMap, combining with any provided by the
1054 // frontend as LLVM metadata. Once all functions are written, PALMetadataMap is
1055 // then written as a single block in the .note section.
1056 void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
1057        const SIProgramInfo &CurrentProgramInfo) {
1058   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1059   // Given the calling convention, calculate the register number for rsrc1. In
1060   // principle the register number could change in future hardware, but we know
1061   // it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so
1062   // we can use the same fixed value that .AMDGPU.config has for Mesa. Note
1063   // that we use a register number rather than a byte offset, so we need to
1064   // divide by 4.
1065   unsigned Rsrc1Reg = getRsrcReg(MF.getFunction().getCallingConv()) / 4;
1066   unsigned Rsrc2Reg = Rsrc1Reg + 1;
1067   // Also calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used
1068   // with a constant offset to access any non-register shader-specific PAL
1069   // metadata key.
1070   unsigned ScratchSizeKey = PALMD::Key::CS_SCRATCH_SIZE;
1071   switch (MF.getFunction().getCallingConv()) {
1072     case CallingConv::AMDGPU_PS:
1073       ScratchSizeKey = PALMD::Key::PS_SCRATCH_SIZE;
1074       break;
1075     case CallingConv::AMDGPU_VS:
1076       ScratchSizeKey = PALMD::Key::VS_SCRATCH_SIZE;
1077       break;
1078     case CallingConv::AMDGPU_GS:
1079       ScratchSizeKey = PALMD::Key::GS_SCRATCH_SIZE;
1080       break;
1081     case CallingConv::AMDGPU_ES:
1082       ScratchSizeKey = PALMD::Key::ES_SCRATCH_SIZE;
1083       break;
1084     case CallingConv::AMDGPU_HS:
1085       ScratchSizeKey = PALMD::Key::HS_SCRATCH_SIZE;
1086       break;
1087     case CallingConv::AMDGPU_LS:
1088       ScratchSizeKey = PALMD::Key::LS_SCRATCH_SIZE;
1089       break;
1090   }
1091   unsigned NumUsedVgprsKey = ScratchSizeKey +
1092       PALMD::Key::VS_NUM_USED_VGPRS - PALMD::Key::VS_SCRATCH_SIZE;
1093   unsigned NumUsedSgprsKey = ScratchSizeKey +
1094       PALMD::Key::VS_NUM_USED_SGPRS - PALMD::Key::VS_SCRATCH_SIZE;
1095   PALMetadataMap[NumUsedVgprsKey] = CurrentProgramInfo.NumVGPRsForWavesPerEU;
1096   PALMetadataMap[NumUsedSgprsKey] = CurrentProgramInfo.NumSGPRsForWavesPerEU;
1097   if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
1098     PALMetadataMap[Rsrc1Reg] |= CurrentProgramInfo.ComputePGMRSrc1;
1099     PALMetadataMap[Rsrc2Reg] |= CurrentProgramInfo.ComputePGMRSrc2;
1100     // ScratchSize is in bytes, 16 aligned.
1101     PALMetadataMap[ScratchSizeKey] |=
1102         alignTo(CurrentProgramInfo.ScratchSize, 16);
1103   } else {
1104     PALMetadataMap[Rsrc1Reg] |= S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
1105         S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks);
1106     if (CurrentProgramInfo.ScratchBlocks > 0)
1107       PALMetadataMap[Rsrc2Reg] |= S_00B84C_SCRATCH_EN(1);
1108     // ScratchSize is in bytes, 16 aligned.
1109     PALMetadataMap[ScratchSizeKey] |=
1110         alignTo(CurrentProgramInfo.ScratchSize, 16);
1111   }
1112   if (MF.getFunction().getCallingConv() == CallingConv::AMDGPU_PS) {
1113     PALMetadataMap[Rsrc2Reg] |=
1114         S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks);
1115     PALMetadataMap[R_0286CC_SPI_PS_INPUT_ENA / 4] |= MFI->getPSInputEnable();
1116     PALMetadataMap[R_0286D0_SPI_PS_INPUT_ADDR / 4] |= MFI->getPSInputAddr();
1117   }
1118 }
1119 
1120 // This is supposed to be log2(Size)
1121 static amd_element_byte_size_t getElementByteSizeValue(unsigned Size) {
1122   switch (Size) {
1123   case 4:
1124     return AMD_ELEMENT_4_BYTES;
1125   case 8:
1126     return AMD_ELEMENT_8_BYTES;
1127   case 16:
1128     return AMD_ELEMENT_16_BYTES;
1129   default:
1130     llvm_unreachable("invalid private_element_size");
1131   }
1132 }
1133 
1134 void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out,
1135                                         const SIProgramInfo &CurrentProgramInfo,
1136                                         const MachineFunction &MF) const {
1137   const Function &F = MF.getFunction();
1138   assert(F.getCallingConv() == CallingConv::AMDGPU_KERNEL ||
1139          F.getCallingConv() == CallingConv::SPIR_KERNEL);
1140 
1141   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1142   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
1143 
1144   AMDGPU::initDefaultAMDKernelCodeT(Out, getSTI());
1145 
1146   Out.compute_pgm_resource_registers =
1147       CurrentProgramInfo.ComputePGMRSrc1 |
1148       (CurrentProgramInfo.ComputePGMRSrc2 << 32);
1149   Out.code_properties = AMD_CODE_PROPERTY_IS_PTR64;
1150 
1151   if (CurrentProgramInfo.DynamicCallStack)
1152     Out.code_properties |= AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK;
1153 
1154   AMD_HSA_BITS_SET(Out.code_properties,
1155                    AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE,
1156                    getElementByteSizeValue(STM.getMaxPrivateElementSize()));
1157 
1158   if (MFI->hasPrivateSegmentBuffer()) {
1159     Out.code_properties |=
1160       AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
1161   }
1162 
1163   if (MFI->hasDispatchPtr())
1164     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
1165 
1166   if (MFI->hasQueuePtr())
1167     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
1168 
1169   if (MFI->hasKernargSegmentPtr())
1170     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
1171 
1172   if (MFI->hasDispatchID())
1173     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
1174 
1175   if (MFI->hasFlatScratchInit())
1176     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
1177 
1178   if (MFI->hasDispatchPtr())
1179     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
1180 
1181   if (STM.debuggerSupported())
1182     Out.code_properties |= AMD_CODE_PROPERTY_IS_DEBUG_SUPPORTED;
1183 
1184   if (STM.isXNACKEnabled())
1185     Out.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED;
1186 
1187   unsigned MaxKernArgAlign;
1188   Out.kernarg_segment_byte_size = STM.getKernArgSegmentSize(F, MaxKernArgAlign);
1189   Out.wavefront_sgpr_count = CurrentProgramInfo.NumSGPR;
1190   Out.workitem_vgpr_count = CurrentProgramInfo.NumVGPR;
1191   Out.workitem_private_segment_byte_size = CurrentProgramInfo.ScratchSize;
1192   Out.workgroup_group_segment_byte_size = CurrentProgramInfo.LDSSize;
1193 
1194   // These alignment values are specified in powers of two, so alignment =
1195   // 2^n.  The minimum alignment is 2^4 = 16.
1196   Out.kernarg_segment_alignment = std::max((size_t)4,
1197       countTrailingZeros(MaxKernArgAlign));
1198 
1199   if (STM.debuggerEmitPrologue()) {
1200     Out.debug_wavefront_private_segment_offset_sgpr =
1201       CurrentProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR;
1202     Out.debug_private_segment_buffer_sgpr =
1203       CurrentProgramInfo.DebuggerPrivateSegmentBufferSGPR;
1204   }
1205 }
1206 
1207 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
1208                                        unsigned AsmVariant,
1209                                        const char *ExtraCode, raw_ostream &O) {
1210   // First try the generic code, which knows about modifiers like 'c' and 'n'.
1211   if (!AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O))
1212     return false;
1213 
1214   if (ExtraCode && ExtraCode[0]) {
1215     if (ExtraCode[1] != 0)
1216       return true; // Unknown modifier.
1217 
1218     switch (ExtraCode[0]) {
1219     case 'r':
1220       break;
1221     default:
1222       return true;
1223     }
1224   }
1225 
1226   // TODO: Should be able to support other operand types like globals.
1227   const MachineOperand &MO = MI->getOperand(OpNo);
1228   if (MO.isReg()) {
1229     AMDGPUInstPrinter::printRegOperand(MO.getReg(), O,
1230                                        *MF->getSubtarget().getRegisterInfo());
1231     return false;
1232   }
1233 
1234   return true;
1235 }
1236