1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
15 //
16 //===----------------------------------------------------------------------===//
17 //
18 
19 #include "AMDGPUAsmPrinter.h"
20 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
21 #include "InstPrinter/AMDGPUInstPrinter.h"
22 #include "Utils/AMDGPUBaseInfo.h"
23 #include "AMDGPU.h"
24 #include "AMDKernelCodeT.h"
25 #include "AMDGPUSubtarget.h"
26 #include "R600Defines.h"
27 #include "R600MachineFunctionInfo.h"
28 #include "R600RegisterInfo.h"
29 #include "SIDefines.h"
30 #include "SIMachineFunctionInfo.h"
31 #include "SIInstrInfo.h"
32 #include "SIRegisterInfo.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/IR/DiagnosticInfo.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCSectionELF.h"
37 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/Support/ELF.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/TargetRegistry.h"
41 #include "llvm/Target/TargetLoweringObjectFile.h"
42 
43 using namespace llvm;
44 
45 // TODO: This should get the default rounding mode from the kernel. We just set
46 // the default here, but this could change if the OpenCL rounding mode pragmas
47 // are used.
48 //
49 // The denormal mode here should match what is reported by the OpenCL runtime
50 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
51 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
52 //
53 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
54 // precision, and leaves single precision to flush all and does not report
55 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
56 // CL_FP_DENORM for both.
57 //
58 // FIXME: It seems some instructions do not support single precision denormals
59 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
60 // and sin_f32, cos_f32 on most parts).
61 
62 // We want to use these instructions, and using fp32 denormals also causes
63 // instructions to run at the double precision rate for the device so it's
64 // probably best to just report no single precision denormals.
65 static uint32_t getFPMode(const MachineFunction &F) {
66   const AMDGPUSubtarget& ST = F.getSubtarget<AMDGPUSubtarget>();
67   // TODO: Is there any real use for the flush in only / flush out only modes?
68 
69   uint32_t FP32Denormals =
70     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
71 
72   uint32_t FP64Denormals =
73     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
74 
75   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
76          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
77          FP_DENORM_MODE_SP(FP32Denormals) |
78          FP_DENORM_MODE_DP(FP64Denormals);
79 }
80 
81 static AsmPrinter *
82 createAMDGPUAsmPrinterPass(TargetMachine &tm,
83                            std::unique_ptr<MCStreamer> &&Streamer) {
84   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
85 }
86 
87 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
88   TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
89   TargetRegistry::RegisterAsmPrinter(TheGCNTarget, createAMDGPUAsmPrinterPass);
90 }
91 
92 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
93                                    std::unique_ptr<MCStreamer> Streamer)
94     : AsmPrinter(TM, std::move(Streamer)) {}
95 
96 void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) {
97   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
98     return;
99 
100   // Need to construct an MCSubtargetInfo here in case we have no functions
101   // in the module.
102   std::unique_ptr<MCSubtargetInfo> STI(TM.getTarget().createMCSubtargetInfo(
103         TM.getTargetTriple().str(), TM.getTargetCPU(),
104         TM.getTargetFeatureString()));
105 
106   AMDGPUTargetStreamer *TS =
107       static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
108 
109   TS->EmitDirectiveHSACodeObjectVersion(2, 0);
110 
111   AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI->getFeatureBits());
112   TS->EmitDirectiveHSACodeObjectISA(ISA.Major, ISA.Minor, ISA.Stepping,
113                                     "AMD", "AMDGPU");
114 }
115 
116 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
117   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
118   SIProgramInfo KernelInfo;
119   if (STM.isAmdHsaOS()) {
120     getSIProgramInfo(KernelInfo, *MF);
121     EmitAmdKernelCodeT(*MF, KernelInfo);
122   }
123 }
124 
125 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
126   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
127   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
128   if (MFI->isKernel() && STM.isAmdHsaOS()) {
129     AMDGPUTargetStreamer *TS =
130         static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
131     TS->EmitAMDGPUSymbolType(CurrentFnSym->getName(),
132                              ELF::STT_AMDGPU_HSA_KERNEL);
133   }
134 
135   AsmPrinter::EmitFunctionEntryLabel();
136 }
137 
138 void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
139 
140   // Group segment variables aren't emitted in HSA.
141   if (AMDGPU::isGroupSegment(GV))
142     return;
143 
144   AsmPrinter::EmitGlobalVariable(GV);
145 }
146 
147 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
148 
149   // The starting address of all shader programs must be 256 bytes aligned.
150   MF.setAlignment(8);
151 
152   SetupMachineFunction(MF);
153 
154   MCContext &Context = getObjFileLowering().getContext();
155   MCSectionELF *ConfigSection =
156       Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
157   OutStreamer->SwitchSection(ConfigSection);
158 
159   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
160   SIProgramInfo KernelInfo;
161   if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
162     getSIProgramInfo(KernelInfo, MF);
163     if (!STM.isAmdHsaOS()) {
164       EmitProgramInfoSI(MF, KernelInfo);
165     }
166   } else {
167     EmitProgramInfoR600(MF);
168   }
169 
170   DisasmLines.clear();
171   HexLines.clear();
172   DisasmLineMaxLen = 0;
173 
174   EmitFunctionBody();
175 
176   if (isVerbose()) {
177     MCSectionELF *CommentSection =
178         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
179     OutStreamer->SwitchSection(CommentSection);
180 
181     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
182       OutStreamer->emitRawComment(" Kernel info:", false);
183       OutStreamer->emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
184                                   false);
185       OutStreamer->emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
186                                   false);
187       OutStreamer->emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
188                                   false);
189       OutStreamer->emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
190                                   false);
191       OutStreamer->emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
192                                   false);
193       OutStreamer->emitRawComment(" ScratchSize: " + Twine(KernelInfo.ScratchSize),
194                                   false);
195       OutStreamer->emitRawComment(" LDSByteSize: " + Twine(KernelInfo.LDSSize) +
196                                   " bytes/workgroup (compile time only)", false);
197 
198       OutStreamer->emitRawComment(" ReservedVGPRFirst: " + Twine(KernelInfo.ReservedVGPRFirst),
199                                   false);
200       OutStreamer->emitRawComment(" ReservedVGPRCount: " + Twine(KernelInfo.ReservedVGPRCount),
201                                   false);
202 
203       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:USER_SGPR: " +
204                                   Twine(G_00B84C_USER_SGPR(KernelInfo.ComputePGMRSrc2)),
205                                   false);
206       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_X_EN: " +
207                                   Twine(G_00B84C_TGID_X_EN(KernelInfo.ComputePGMRSrc2)),
208                                   false);
209       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
210                                   Twine(G_00B84C_TGID_Y_EN(KernelInfo.ComputePGMRSrc2)),
211                                   false);
212       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
213                                   Twine(G_00B84C_TGID_Z_EN(KernelInfo.ComputePGMRSrc2)),
214                                   false);
215       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
216                                   Twine(G_00B84C_TIDIG_COMP_CNT(KernelInfo.ComputePGMRSrc2)),
217                                   false);
218 
219     } else {
220       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
221       OutStreamer->emitRawComment(
222         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
223     }
224   }
225 
226   if (STM.dumpCode()) {
227 
228     OutStreamer->SwitchSection(
229         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
230 
231     for (size_t i = 0; i < DisasmLines.size(); ++i) {
232       std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
233       Comment += " ; " + HexLines[i] + "\n";
234 
235       OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
236       OutStreamer->EmitBytes(StringRef(Comment));
237     }
238   }
239 
240   return false;
241 }
242 
243 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
244   unsigned MaxGPR = 0;
245   bool killPixel = false;
246   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
247   const R600RegisterInfo *RI =
248       static_cast<const R600RegisterInfo *>(STM.getRegisterInfo());
249   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
250 
251   for (const MachineBasicBlock &MBB : MF) {
252     for (const MachineInstr &MI : MBB) {
253       if (MI.getOpcode() == AMDGPU::KILLGT)
254         killPixel = true;
255       unsigned numOperands = MI.getNumOperands();
256       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
257         const MachineOperand &MO = MI.getOperand(op_idx);
258         if (!MO.isReg())
259           continue;
260         unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
261 
262         // Register with value > 127 aren't GPR
263         if (HWReg > 127)
264           continue;
265         MaxGPR = std::max(MaxGPR, HWReg);
266       }
267     }
268   }
269 
270   unsigned RsrcReg;
271   if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
272     // Evergreen / Northern Islands
273     switch (MF.getFunction()->getCallingConv()) {
274     default: // Fall through
275     case CallingConv::AMDGPU_CS: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
276     case CallingConv::AMDGPU_GS: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
277     case CallingConv::AMDGPU_PS: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
278     case CallingConv::AMDGPU_VS: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
279     }
280   } else {
281     // R600 / R700
282     switch (MF.getFunction()->getCallingConv()) {
283     default: // Fall through
284     case CallingConv::AMDGPU_GS: // Fall through
285     case CallingConv::AMDGPU_CS: // Fall through
286     case CallingConv::AMDGPU_VS: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
287     case CallingConv::AMDGPU_PS: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
288     }
289   }
290 
291   OutStreamer->EmitIntValue(RsrcReg, 4);
292   OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
293                            S_STACK_SIZE(MFI->StackSize), 4);
294   OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
295   OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
296 
297   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
298     OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
299     OutStreamer->EmitIntValue(alignTo(MFI->LDSSize, 4) >> 2, 4);
300   }
301 }
302 
303 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
304                                         const MachineFunction &MF) const {
305   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
306   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
307   uint64_t CodeSize = 0;
308   unsigned MaxSGPR = 0;
309   unsigned MaxVGPR = 0;
310   bool VCCUsed = false;
311   bool FlatUsed = false;
312   const SIRegisterInfo *RI =
313       static_cast<const SIRegisterInfo *>(STM.getRegisterInfo());
314   const SIInstrInfo *TII =
315       static_cast<const SIInstrInfo *>(STM.getInstrInfo());
316 
317   for (const MachineBasicBlock &MBB : MF) {
318     for (const MachineInstr &MI : MBB) {
319       // TODO: CodeSize should account for multiple functions.
320 
321       // TODO: Should we count size of debug info?
322       if (MI.isDebugValue())
323         continue;
324 
325       CodeSize += TII->getInstSizeInBytes(MI);
326 
327       unsigned numOperands = MI.getNumOperands();
328       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
329         const MachineOperand &MO = MI.getOperand(op_idx);
330         unsigned width = 0;
331         bool isSGPR = false;
332 
333         if (!MO.isReg())
334           continue;
335 
336         unsigned reg = MO.getReg();
337         switch (reg) {
338         case AMDGPU::EXEC:
339         case AMDGPU::EXEC_LO:
340         case AMDGPU::EXEC_HI:
341         case AMDGPU::SCC:
342         case AMDGPU::M0:
343           continue;
344 
345         case AMDGPU::VCC:
346         case AMDGPU::VCC_LO:
347         case AMDGPU::VCC_HI:
348           VCCUsed = true;
349           continue;
350 
351         case AMDGPU::FLAT_SCR:
352         case AMDGPU::FLAT_SCR_LO:
353         case AMDGPU::FLAT_SCR_HI:
354           FlatUsed = true;
355           continue;
356 
357         case AMDGPU::TBA:
358         case AMDGPU::TBA_LO:
359         case AMDGPU::TBA_HI:
360         case AMDGPU::TMA:
361         case AMDGPU::TMA_LO:
362         case AMDGPU::TMA_HI:
363           llvm_unreachable("Trap Handler registers should not be used");
364           continue;
365 
366         default:
367           break;
368         }
369 
370         if (AMDGPU::SReg_32RegClass.contains(reg)) {
371           if (AMDGPU::TTMP_32RegClass.contains(reg)) {
372             llvm_unreachable("Trap Handler registers should not be used");
373           }
374           isSGPR = true;
375           width = 1;
376         } else if (AMDGPU::VGPR_32RegClass.contains(reg)) {
377           isSGPR = false;
378           width = 1;
379         } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
380           if (AMDGPU::TTMP_64RegClass.contains(reg)) {
381             llvm_unreachable("Trap Handler registers should not be used");
382           }
383           isSGPR = true;
384           width = 2;
385         } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
386           isSGPR = false;
387           width = 2;
388         } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
389           isSGPR = false;
390           width = 3;
391         } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
392           isSGPR = true;
393           width = 4;
394         } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
395           isSGPR = false;
396           width = 4;
397         } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
398           isSGPR = true;
399           width = 8;
400         } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
401           isSGPR = false;
402           width = 8;
403         } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
404           isSGPR = true;
405           width = 16;
406         } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
407           isSGPR = false;
408           width = 16;
409         } else {
410           llvm_unreachable("Unknown register class");
411         }
412         unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
413         unsigned maxUsed = hwReg + width - 1;
414         if (isSGPR) {
415           MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
416         } else {
417           MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
418         }
419       }
420     }
421   }
422 
423   unsigned ExtraSGPRs = 0;
424 
425   if (VCCUsed)
426     ExtraSGPRs = 2;
427 
428   if (STM.getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS) {
429     if (FlatUsed)
430       ExtraSGPRs = 4;
431   } else {
432     if (STM.isXNACKEnabled())
433       ExtraSGPRs = 4;
434 
435     if (FlatUsed)
436       ExtraSGPRs = 6;
437   }
438 
439   MaxSGPR += ExtraSGPRs;
440 
441   // Record first reserved register and reserved register count fields, and
442   // update max register counts if "amdgpu-debugger-reserve-regs" attribute was
443   // specified.
444   if (STM.debuggerReserveRegs()) {
445     ProgInfo.ReservedVGPRFirst = MaxVGPR + 1;
446     ProgInfo.ReservedVGPRCount = MFI->getDebuggerReservedVGPRCount();
447     MaxVGPR += MFI->getDebuggerReservedVGPRCount();
448   }
449 
450   // We found the maximum register index. They start at 0, so add one to get the
451   // number of registers.
452   ProgInfo.NumVGPR = MaxVGPR + 1;
453   ProgInfo.NumSGPR = MaxSGPR + 1;
454 
455   if (STM.hasSGPRInitBug()) {
456     if (ProgInfo.NumSGPR > AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG) {
457       LLVMContext &Ctx = MF.getFunction()->getContext();
458       DiagnosticInfoResourceLimit Diag(*MF.getFunction(),
459                                        "SGPRs with SGPR init bug",
460                                        ProgInfo.NumSGPR, DS_Error);
461       Ctx.diagnose(Diag);
462     }
463 
464     ProgInfo.NumSGPR = AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG;
465   }
466 
467   if (MFI->NumUserSGPRs > STM.getMaxNumUserSGPRs()) {
468     LLVMContext &Ctx = MF.getFunction()->getContext();
469     DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "user SGPRs",
470                                      MFI->NumUserSGPRs, DS_Error);
471     Ctx.diagnose(Diag);
472   }
473 
474   if (MFI->LDSSize > static_cast<unsigned>(STM.getLocalMemorySize())) {
475     LLVMContext &Ctx = MF.getFunction()->getContext();
476     DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "local memory",
477                                      MFI->LDSSize, DS_Error);
478     Ctx.diagnose(Diag);
479   }
480 
481   ProgInfo.VGPRBlocks = (ProgInfo.NumVGPR - 1) / 4;
482   ProgInfo.SGPRBlocks = (ProgInfo.NumSGPR - 1) / 8;
483   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
484   // register.
485   ProgInfo.FloatMode = getFPMode(MF);
486 
487   ProgInfo.IEEEMode = 0;
488 
489   // Make clamp modifier on NaN input returns 0.
490   ProgInfo.DX10Clamp = 1;
491 
492   const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
493   ProgInfo.ScratchSize = FrameInfo->getStackSize();
494 
495   ProgInfo.FlatUsed = FlatUsed;
496   ProgInfo.VCCUsed = VCCUsed;
497   ProgInfo.CodeLen = CodeSize;
498 
499   unsigned LDSAlignShift;
500   if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
501     // LDS is allocated in 64 dword blocks.
502     LDSAlignShift = 8;
503   } else {
504     // LDS is allocated in 128 dword blocks.
505     LDSAlignShift = 9;
506   }
507 
508   unsigned LDSSpillSize = MFI->LDSWaveSpillSize *
509                           MFI->getMaximumWorkGroupSize(MF);
510 
511   ProgInfo.LDSSize = MFI->LDSSize + LDSSpillSize;
512   ProgInfo.LDSBlocks =
513       alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
514 
515   // Scratch is allocated in 256 dword blocks.
516   unsigned ScratchAlignShift = 10;
517   // We need to program the hardware with the amount of scratch memory that
518   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
519   // scratch memory used per thread.
520   ProgInfo.ScratchBlocks =
521       alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
522               1ULL << ScratchAlignShift) >>
523       ScratchAlignShift;
524 
525   ProgInfo.ComputePGMRSrc1 =
526       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
527       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
528       S_00B848_PRIORITY(ProgInfo.Priority) |
529       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
530       S_00B848_PRIV(ProgInfo.Priv) |
531       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
532       S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
533       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
534 
535   // 0 = X, 1 = XY, 2 = XYZ
536   unsigned TIDIGCompCnt = 0;
537   if (MFI->hasWorkItemIDZ())
538     TIDIGCompCnt = 2;
539   else if (MFI->hasWorkItemIDY())
540     TIDIGCompCnt = 1;
541 
542   ProgInfo.ComputePGMRSrc2 =
543       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
544       S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
545       S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
546       S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
547       S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
548       S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
549       S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
550       S_00B84C_EXCP_EN_MSB(0) |
551       S_00B84C_LDS_SIZE(ProgInfo.LDSBlocks) |
552       S_00B84C_EXCP_EN(0);
553 }
554 
555 static unsigned getRsrcReg(CallingConv::ID CallConv) {
556   switch (CallConv) {
557   default: // Fall through
558   case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
559   case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
560   case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
561   case CallingConv::AMDGPU_VS: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
562   }
563 }
564 
565 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
566                                          const SIProgramInfo &KernelInfo) {
567   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
568   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
569   unsigned RsrcReg = getRsrcReg(MF.getFunction()->getCallingConv());
570 
571   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
572     OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
573 
574     OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc1, 4);
575 
576     OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
577     OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc2, 4);
578 
579     OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
580     OutStreamer->EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4);
581 
582     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
583     // 0" comment but I don't see a corresponding field in the register spec.
584   } else {
585     OutStreamer->EmitIntValue(RsrcReg, 4);
586     OutStreamer->EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
587                               S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4);
588     if (STM.isVGPRSpillingEnabled(*MF.getFunction())) {
589       OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
590       OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(KernelInfo.ScratchBlocks), 4);
591     }
592   }
593 
594   if (MF.getFunction()->getCallingConv() == CallingConv::AMDGPU_PS) {
595     OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
596     OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4);
597     OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
598     OutStreamer->EmitIntValue(MFI->PSInputEna, 4);
599     OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
600     OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4);
601   }
602 }
603 
604 // This is supposed to be log2(Size)
605 static amd_element_byte_size_t getElementByteSizeValue(unsigned Size) {
606   switch (Size) {
607   case 4:
608     return AMD_ELEMENT_4_BYTES;
609   case 8:
610     return AMD_ELEMENT_8_BYTES;
611   case 16:
612     return AMD_ELEMENT_16_BYTES;
613   default:
614     llvm_unreachable("invalid private_element_size");
615   }
616 }
617 
618 void AMDGPUAsmPrinter::EmitAmdKernelCodeT(const MachineFunction &MF,
619                                          const SIProgramInfo &KernelInfo) const {
620   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
621   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
622   amd_kernel_code_t header;
623 
624   AMDGPU::initDefaultAMDKernelCodeT(header, STM.getFeatureBits());
625 
626   header.compute_pgm_resource_registers =
627       KernelInfo.ComputePGMRSrc1 |
628       (KernelInfo.ComputePGMRSrc2 << 32);
629   header.code_properties = AMD_CODE_PROPERTY_IS_PTR64;
630 
631 
632   AMD_HSA_BITS_SET(header.code_properties,
633                    AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE,
634                    getElementByteSizeValue(STM.getMaxPrivateElementSize()));
635 
636   if (MFI->hasPrivateSegmentBuffer()) {
637     header.code_properties |=
638       AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
639   }
640 
641   if (MFI->hasDispatchPtr())
642     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
643 
644   if (MFI->hasQueuePtr())
645     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
646 
647   if (MFI->hasKernargSegmentPtr())
648     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
649 
650   if (MFI->hasDispatchID())
651     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
652 
653   if (MFI->hasFlatScratchInit())
654     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
655 
656   // TODO: Private segment size
657 
658   if (MFI->hasGridWorkgroupCountX()) {
659     header.code_properties |=
660       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X;
661   }
662 
663   if (MFI->hasGridWorkgroupCountY()) {
664     header.code_properties |=
665       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y;
666   }
667 
668   if (MFI->hasGridWorkgroupCountZ()) {
669     header.code_properties |=
670       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z;
671   }
672 
673   if (MFI->hasDispatchPtr())
674     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
675 
676   if (STM.isXNACKEnabled())
677     header.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED;
678 
679   header.kernarg_segment_byte_size = MFI->ABIArgOffset;
680   header.wavefront_sgpr_count = KernelInfo.NumSGPR;
681   header.workitem_vgpr_count = KernelInfo.NumVGPR;
682   header.workitem_private_segment_byte_size = KernelInfo.ScratchSize;
683   header.workgroup_group_segment_byte_size = KernelInfo.LDSSize;
684   header.reserved_vgpr_first = KernelInfo.ReservedVGPRFirst;
685   header.reserved_vgpr_count = KernelInfo.ReservedVGPRCount;
686 
687   AMDGPUTargetStreamer *TS =
688       static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
689 
690   OutStreamer->SwitchSection(getObjFileLowering().getTextSection());
691   TS->EmitAMDKernelCodeT(header);
692 }
693 
694 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
695                                        unsigned AsmVariant,
696                                        const char *ExtraCode, raw_ostream &O) {
697   if (ExtraCode && ExtraCode[0]) {
698     if (ExtraCode[1] != 0)
699       return true; // Unknown modifier.
700 
701     switch (ExtraCode[0]) {
702     default:
703       // See if this is a generic print operand
704       return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
705     case 'r':
706       break;
707     }
708   }
709 
710   AMDGPUInstPrinter::printRegOperand(MI->getOperand(OpNo).getReg(), O,
711                    *TM.getSubtargetImpl(*MF->getFunction())->getRegisterInfo());
712   return false;
713 }
714