1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
15 //
16 //===----------------------------------------------------------------------===//
17 //
18 
19 #include "AMDGPUAsmPrinter.h"
20 #include "AMDGPU.h"
21 #include "AMDGPUSubtarget.h"
22 #include "AMDGPUTargetMachine.h"
23 #include "InstPrinter/AMDGPUInstPrinter.h"
24 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
25 #include "R600Defines.h"
26 #include "R600MachineFunctionInfo.h"
27 #include "R600RegisterInfo.h"
28 #include "SIDefines.h"
29 #include "SIInstrInfo.h"
30 #include "SIMachineFunctionInfo.h"
31 #include "SIRegisterInfo.h"
32 #include "Utils/AMDGPUBaseInfo.h"
33 #include "llvm/BinaryFormat/ELF.h"
34 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/IR/DiagnosticInfo.h"
36 #include "llvm/MC/MCContext.h"
37 #include "llvm/MC/MCSectionELF.h"
38 #include "llvm/MC/MCStreamer.h"
39 #include "llvm/Support/AMDGPUMetadata.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Target/TargetLoweringObjectFile.h"
43 
44 using namespace llvm;
45 using namespace llvm::AMDGPU;
46 
47 // TODO: This should get the default rounding mode from the kernel. We just set
48 // the default here, but this could change if the OpenCL rounding mode pragmas
49 // are used.
50 //
51 // The denormal mode here should match what is reported by the OpenCL runtime
52 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
53 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
54 //
55 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
56 // precision, and leaves single precision to flush all and does not report
57 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
58 // CL_FP_DENORM for both.
59 //
60 // FIXME: It seems some instructions do not support single precision denormals
61 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
62 // and sin_f32, cos_f32 on most parts).
63 
64 // We want to use these instructions, and using fp32 denormals also causes
65 // instructions to run at the double precision rate for the device so it's
66 // probably best to just report no single precision denormals.
67 static uint32_t getFPMode(const MachineFunction &F) {
68   const SISubtarget& ST = F.getSubtarget<SISubtarget>();
69   // TODO: Is there any real use for the flush in only / flush out only modes?
70 
71   uint32_t FP32Denormals =
72     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
73 
74   uint32_t FP64Denormals =
75     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
76 
77   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
78          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
79          FP_DENORM_MODE_SP(FP32Denormals) |
80          FP_DENORM_MODE_DP(FP64Denormals);
81 }
82 
83 static AsmPrinter *
84 createAMDGPUAsmPrinterPass(TargetMachine &tm,
85                            std::unique_ptr<MCStreamer> &&Streamer) {
86   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
87 }
88 
89 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
90   TargetRegistry::RegisterAsmPrinter(getTheAMDGPUTarget(),
91                                      createAMDGPUAsmPrinterPass);
92   TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(),
93                                      createAMDGPUAsmPrinterPass);
94 }
95 
96 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
97                                    std::unique_ptr<MCStreamer> Streamer)
98   : AsmPrinter(TM, std::move(Streamer)) {
99     AMDGPUASI = static_cast<AMDGPUTargetMachine*>(&TM)->getAMDGPUAS();
100   }
101 
102 StringRef AMDGPUAsmPrinter::getPassName() const {
103   return "AMDGPU Assembly Printer";
104 }
105 
106 const MCSubtargetInfo* AMDGPUAsmPrinter::getSTI() const {
107   return TM.getMCSubtargetInfo();
108 }
109 
110 AMDGPUTargetStreamer* AMDGPUAsmPrinter::getTargetStreamer() const {
111   if (!OutStreamer)
112     return nullptr;
113   return static_cast<AMDGPUTargetStreamer*>(OutStreamer->getTargetStreamer());
114 }
115 
116 void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) {
117   if (TM.getTargetTriple().getArch() != Triple::amdgcn)
118     return;
119 
120   if (TM.getTargetTriple().getOS() != Triple::AMDHSA &&
121       TM.getTargetTriple().getOS() != Triple::AMDPAL)
122     return;
123 
124   if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
125     HSAMetadataStream.begin(M);
126 
127   if (TM.getTargetTriple().getOS() == Triple::AMDPAL)
128     readPALMetadata(M);
129 
130   // Deprecated notes are not emitted for code object v3.
131   if (IsaInfo::hasCodeObjectV3(getSTI()->getFeatureBits()))
132     return;
133 
134   // HSA emits NT_AMDGPU_HSA_CODE_OBJECT_VERSION for code objects v2.
135   if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
136     getTargetStreamer()->EmitDirectiveHSACodeObjectVersion(2, 1);
137 
138   // HSA and PAL emit NT_AMDGPU_HSA_ISA for code objects v2.
139   IsaInfo::IsaVersion ISA = IsaInfo::getIsaVersion(getSTI()->getFeatureBits());
140   getTargetStreamer()->EmitDirectiveHSACodeObjectISA(
141       ISA.Major, ISA.Minor, ISA.Stepping, "AMD", "AMDGPU");
142 }
143 
144 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
145   if (TM.getTargetTriple().getArch() != Triple::amdgcn)
146     return;
147 
148   // Following code requires TargetStreamer to be present.
149   if (!getTargetStreamer())
150     return;
151 
152   // Emit ISA Version (NT_AMD_AMDGPU_ISA).
153   std::string ISAVersionString;
154   raw_string_ostream ISAVersionStream(ISAVersionString);
155   IsaInfo::streamIsaVersion(getSTI(), ISAVersionStream);
156   getTargetStreamer()->EmitISAVersion(ISAVersionStream.str());
157 
158   // Emit HSA Metadata (NT_AMD_AMDGPU_HSA_METADATA).
159   if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
160     HSAMetadataStream.end();
161     getTargetStreamer()->EmitHSAMetadata(HSAMetadataStream.getHSAMetadata());
162   }
163 
164   // Emit PAL Metadata (NT_AMD_AMDGPU_PAL_METADATA).
165   if (TM.getTargetTriple().getOS() == Triple::AMDPAL) {
166     // Copy the PAL metadata from the map where we collected it into a vector,
167     // then write it as a .note.
168     PALMD::Metadata PALMetadataVector;
169     for (auto i : PALMetadataMap) {
170       PALMetadataVector.push_back(i.first);
171       PALMetadataVector.push_back(i.second);
172     }
173     getTargetStreamer()->EmitPALMetadata(PALMetadataVector);
174   }
175 }
176 
177 bool AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough(
178   const MachineBasicBlock *MBB) const {
179   if (!AsmPrinter::isBlockOnlyReachableByFallthrough(MBB))
180     return false;
181 
182   if (MBB->empty())
183     return true;
184 
185   // If this is a block implementing a long branch, an expression relative to
186   // the start of the block is needed.  to the start of the block.
187   // XXX - Is there a smarter way to check this?
188   return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
189 }
190 
191 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
192   const AMDGPUMachineFunction *MFI = MF->getInfo<AMDGPUMachineFunction>();
193   if (!MFI->isEntryFunction())
194     return;
195 
196   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
197   amd_kernel_code_t KernelCode;
198   if (STM.isAmdCodeObjectV2(*MF)) {
199     getAmdKernelCode(KernelCode, CurrentProgramInfo, *MF);
200 
201     OutStreamer->SwitchSection(getObjFileLowering().getTextSection());
202     getTargetStreamer()->EmitAMDKernelCodeT(KernelCode);
203   }
204 
205   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
206     return;
207 
208   HSAMetadataStream.emitKernel(MF->getFunction(),
209                                getHSACodeProps(*MF, CurrentProgramInfo),
210                                getHSADebugProps(*MF, CurrentProgramInfo));
211 }
212 
213 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
214   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
215   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
216   if (MFI->isEntryFunction() && STM.isAmdCodeObjectV2(*MF)) {
217     SmallString<128> SymbolName;
218     getNameWithPrefix(SymbolName, &MF->getFunction()),
219     getTargetStreamer()->EmitAMDGPUSymbolType(
220         SymbolName, ELF::STT_AMDGPU_HSA_KERNEL);
221   }
222   const AMDGPUSubtarget &STI = MF->getSubtarget<AMDGPUSubtarget>();
223   if (STI.dumpCode()) {
224     // Disassemble function name label to text.
225     DisasmLines.push_back(MF->getName().str() + ":");
226     DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size());
227     HexLines.push_back("");
228   }
229 
230   AsmPrinter::EmitFunctionEntryLabel();
231 }
232 
233 void AMDGPUAsmPrinter::EmitBasicBlockStart(const MachineBasicBlock &MBB) const {
234   const AMDGPUSubtarget &STI = MBB.getParent()->getSubtarget<AMDGPUSubtarget>();
235   if (STI.dumpCode() && !isBlockOnlyReachableByFallthrough(&MBB)) {
236     // Write a line for the basic block label if it is not only fallthrough.
237     DisasmLines.push_back(
238         (Twine("BB") + Twine(getFunctionNumber())
239          + "_" + Twine(MBB.getNumber()) + ":").str());
240     DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size());
241     HexLines.push_back("");
242   }
243   AsmPrinter::EmitBasicBlockStart(MBB);
244 }
245 
246 void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
247 
248   // Group segment variables aren't emitted in HSA.
249   if (AMDGPU::isGroupSegment(GV))
250     return;
251 
252   AsmPrinter::EmitGlobalVariable(GV);
253 }
254 
255 bool AMDGPUAsmPrinter::doFinalization(Module &M) {
256   CallGraphResourceInfo.clear();
257   return AsmPrinter::doFinalization(M);
258 }
259 
260 // For the amdpal OS type, read the amdgpu.pal.metadata supplied by the
261 // frontend into our PALMetadataMap, ready for per-function modification.  It
262 // is a NamedMD containing an MDTuple containing a number of MDNodes each of
263 // which is an integer value, and each two integer values forms a key=value
264 // pair that we store as PALMetadataMap[key]=value in the map.
265 void AMDGPUAsmPrinter::readPALMetadata(Module &M) {
266   auto NamedMD = M.getNamedMetadata("amdgpu.pal.metadata");
267   if (!NamedMD || !NamedMD->getNumOperands())
268     return;
269   auto Tuple = dyn_cast<MDTuple>(NamedMD->getOperand(0));
270   if (!Tuple)
271     return;
272   for (unsigned I = 0, E = Tuple->getNumOperands() & -2; I != E; I += 2) {
273     auto Key = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I));
274     auto Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I + 1));
275     if (!Key || !Val)
276       continue;
277     PALMetadataMap[Key->getZExtValue()] = Val->getZExtValue();
278   }
279 }
280 
281 // Print comments that apply to both callable functions and entry points.
282 void AMDGPUAsmPrinter::emitCommonFunctionComments(
283   uint32_t NumVGPR,
284   uint32_t NumSGPR,
285   uint64_t ScratchSize,
286   uint64_t CodeSize) {
287   OutStreamer->emitRawComment(" codeLenInByte = " + Twine(CodeSize), false);
288   OutStreamer->emitRawComment(" NumSgprs: " + Twine(NumSGPR), false);
289   OutStreamer->emitRawComment(" NumVgprs: " + Twine(NumVGPR), false);
290   OutStreamer->emitRawComment(" ScratchSize: " + Twine(ScratchSize), false);
291 }
292 
293 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
294   CurrentProgramInfo = SIProgramInfo();
295 
296   const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
297 
298   // The starting address of all shader programs must be 256 bytes aligned.
299   // Regular functions just need the basic required instruction alignment.
300   MF.setAlignment(MFI->isEntryFunction() ? 8 : 2);
301 
302   SetupMachineFunction(MF);
303 
304   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
305   MCContext &Context = getObjFileLowering().getContext();
306   // FIXME: This should be an explicit check for Mesa.
307   if (!STM.isAmdHsaOS() && !STM.isAmdPalOS()) {
308     MCSectionELF *ConfigSection =
309         Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
310     OutStreamer->SwitchSection(ConfigSection);
311   }
312 
313   if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
314     if (MFI->isEntryFunction()) {
315       getSIProgramInfo(CurrentProgramInfo, MF);
316     } else {
317       auto I = CallGraphResourceInfo.insert(
318         std::make_pair(&MF.getFunction(), SIFunctionResourceInfo()));
319       SIFunctionResourceInfo &Info = I.first->second;
320       assert(I.second && "should only be called once per function");
321       Info = analyzeResourceUsage(MF);
322     }
323 
324     if (STM.isAmdPalOS())
325       EmitPALMetadata(MF, CurrentProgramInfo);
326     else if (!STM.isAmdHsaOS()) {
327       EmitProgramInfoSI(MF, CurrentProgramInfo);
328     }
329   } else {
330     EmitProgramInfoR600(MF);
331   }
332 
333   DisasmLines.clear();
334   HexLines.clear();
335   DisasmLineMaxLen = 0;
336 
337   EmitFunctionBody();
338 
339   if (isVerbose()) {
340     MCSectionELF *CommentSection =
341         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
342     OutStreamer->SwitchSection(CommentSection);
343 
344     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
345       if (!MFI->isEntryFunction()) {
346         OutStreamer->emitRawComment(" Function info:", false);
347         SIFunctionResourceInfo &Info = CallGraphResourceInfo[&MF.getFunction()];
348         emitCommonFunctionComments(
349           Info.NumVGPR,
350           Info.getTotalNumSGPRs(MF.getSubtarget<SISubtarget>()),
351           Info.PrivateSegmentSize,
352           getFunctionCodeSize(MF));
353         return false;
354       }
355 
356       OutStreamer->emitRawComment(" Kernel info:", false);
357       emitCommonFunctionComments(CurrentProgramInfo.NumVGPR,
358                                  CurrentProgramInfo.NumSGPR,
359                                  CurrentProgramInfo.ScratchSize,
360                                  getFunctionCodeSize(MF));
361 
362       OutStreamer->emitRawComment(
363         " FloatMode: " + Twine(CurrentProgramInfo.FloatMode), false);
364       OutStreamer->emitRawComment(
365         " IeeeMode: " + Twine(CurrentProgramInfo.IEEEMode), false);
366       OutStreamer->emitRawComment(
367         " LDSByteSize: " + Twine(CurrentProgramInfo.LDSSize) +
368         " bytes/workgroup (compile time only)", false);
369 
370       OutStreamer->emitRawComment(
371         " SGPRBlocks: " + Twine(CurrentProgramInfo.SGPRBlocks), false);
372       OutStreamer->emitRawComment(
373         " VGPRBlocks: " + Twine(CurrentProgramInfo.VGPRBlocks), false);
374 
375       OutStreamer->emitRawComment(
376         " NumSGPRsForWavesPerEU: " +
377         Twine(CurrentProgramInfo.NumSGPRsForWavesPerEU), false);
378       OutStreamer->emitRawComment(
379         " NumVGPRsForWavesPerEU: " +
380         Twine(CurrentProgramInfo.NumVGPRsForWavesPerEU), false);
381 
382       OutStreamer->emitRawComment(
383         " ReservedVGPRFirst: " + Twine(CurrentProgramInfo.ReservedVGPRFirst),
384         false);
385       OutStreamer->emitRawComment(
386         " ReservedVGPRCount: " + Twine(CurrentProgramInfo.ReservedVGPRCount),
387         false);
388 
389       if (MF.getSubtarget<SISubtarget>().debuggerEmitPrologue()) {
390         OutStreamer->emitRawComment(
391           " DebuggerWavefrontPrivateSegmentOffsetSGPR: s" +
392           Twine(CurrentProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR), false);
393         OutStreamer->emitRawComment(
394           " DebuggerPrivateSegmentBufferSGPR: s" +
395           Twine(CurrentProgramInfo.DebuggerPrivateSegmentBufferSGPR), false);
396       }
397 
398       OutStreamer->emitRawComment(
399         " COMPUTE_PGM_RSRC2:USER_SGPR: " +
400         Twine(G_00B84C_USER_SGPR(CurrentProgramInfo.ComputePGMRSrc2)), false);
401       OutStreamer->emitRawComment(
402         " COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
403         Twine(G_00B84C_TRAP_HANDLER(CurrentProgramInfo.ComputePGMRSrc2)), false);
404       OutStreamer->emitRawComment(
405         " COMPUTE_PGM_RSRC2:TGID_X_EN: " +
406         Twine(G_00B84C_TGID_X_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
407       OutStreamer->emitRawComment(
408         " COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
409         Twine(G_00B84C_TGID_Y_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
410       OutStreamer->emitRawComment(
411         " COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
412         Twine(G_00B84C_TGID_Z_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
413       OutStreamer->emitRawComment(
414         " COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
415         Twine(G_00B84C_TIDIG_COMP_CNT(CurrentProgramInfo.ComputePGMRSrc2)),
416         false);
417     } else {
418       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
419       OutStreamer->emitRawComment(
420         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->CFStackSize)));
421     }
422   }
423 
424   if (STM.dumpCode()) {
425 
426     OutStreamer->SwitchSection(
427         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
428 
429     for (size_t i = 0; i < DisasmLines.size(); ++i) {
430       std::string Comment = "\n";
431       if (!HexLines[i].empty()) {
432         Comment = std::string(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
433         Comment += " ; " + HexLines[i] + "\n";
434       }
435 
436       OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
437       OutStreamer->EmitBytes(StringRef(Comment));
438     }
439   }
440 
441   return false;
442 }
443 
444 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
445   unsigned MaxGPR = 0;
446   bool killPixel = false;
447   const R600Subtarget &STM = MF.getSubtarget<R600Subtarget>();
448   const R600RegisterInfo *RI = STM.getRegisterInfo();
449   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
450 
451   for (const MachineBasicBlock &MBB : MF) {
452     for (const MachineInstr &MI : MBB) {
453       if (MI.getOpcode() == AMDGPU::KILLGT)
454         killPixel = true;
455       unsigned numOperands = MI.getNumOperands();
456       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
457         const MachineOperand &MO = MI.getOperand(op_idx);
458         if (!MO.isReg())
459           continue;
460         unsigned HWReg = RI->getHWRegIndex(MO.getReg());
461 
462         // Register with value > 127 aren't GPR
463         if (HWReg > 127)
464           continue;
465         MaxGPR = std::max(MaxGPR, HWReg);
466       }
467     }
468   }
469 
470   unsigned RsrcReg;
471   if (STM.getGeneration() >= R600Subtarget::EVERGREEN) {
472     // Evergreen / Northern Islands
473     switch (MF.getFunction().getCallingConv()) {
474     default: LLVM_FALLTHROUGH;
475     case CallingConv::AMDGPU_CS: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
476     case CallingConv::AMDGPU_GS: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
477     case CallingConv::AMDGPU_PS: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
478     case CallingConv::AMDGPU_VS: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
479     }
480   } else {
481     // R600 / R700
482     switch (MF.getFunction().getCallingConv()) {
483     default: LLVM_FALLTHROUGH;
484     case CallingConv::AMDGPU_GS: LLVM_FALLTHROUGH;
485     case CallingConv::AMDGPU_CS: LLVM_FALLTHROUGH;
486     case CallingConv::AMDGPU_VS: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
487     case CallingConv::AMDGPU_PS: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
488     }
489   }
490 
491   OutStreamer->EmitIntValue(RsrcReg, 4);
492   OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
493                            S_STACK_SIZE(MFI->CFStackSize), 4);
494   OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
495   OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
496 
497   if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
498     OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
499     OutStreamer->EmitIntValue(alignTo(MFI->getLDSSize(), 4) >> 2, 4);
500   }
501 }
502 
503 uint64_t AMDGPUAsmPrinter::getFunctionCodeSize(const MachineFunction &MF) const {
504   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
505   const SIInstrInfo *TII = STM.getInstrInfo();
506 
507   uint64_t CodeSize = 0;
508 
509   for (const MachineBasicBlock &MBB : MF) {
510     for (const MachineInstr &MI : MBB) {
511       // TODO: CodeSize should account for multiple functions.
512 
513       // TODO: Should we count size of debug info?
514       if (MI.isDebugValue())
515         continue;
516 
517       CodeSize += TII->getInstSizeInBytes(MI);
518     }
519   }
520 
521   return CodeSize;
522 }
523 
524 static bool hasAnyNonFlatUseOfReg(const MachineRegisterInfo &MRI,
525                                   const SIInstrInfo &TII,
526                                   unsigned Reg) {
527   for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) {
528     if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent()))
529       return true;
530   }
531 
532   return false;
533 }
534 
535 static unsigned getNumExtraSGPRs(const SISubtarget &ST,
536                                  bool VCCUsed,
537                                  bool FlatScrUsed) {
538   unsigned ExtraSGPRs = 0;
539   if (VCCUsed)
540     ExtraSGPRs = 2;
541 
542   if (ST.getGeneration() < SISubtarget::VOLCANIC_ISLANDS) {
543     if (FlatScrUsed)
544       ExtraSGPRs = 4;
545   } else {
546     if (ST.isXNACKEnabled())
547       ExtraSGPRs = 4;
548 
549     if (FlatScrUsed)
550       ExtraSGPRs = 6;
551   }
552 
553   return ExtraSGPRs;
554 }
555 
556 int32_t AMDGPUAsmPrinter::SIFunctionResourceInfo::getTotalNumSGPRs(
557   const SISubtarget &ST) const {
558   return NumExplicitSGPR + getNumExtraSGPRs(ST, UsesVCC, UsesFlatScratch);
559 }
560 
561 AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
562   const MachineFunction &MF) const {
563   SIFunctionResourceInfo Info;
564 
565   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
566   const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
567   const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
568   const MachineRegisterInfo &MRI = MF.getRegInfo();
569   const SIInstrInfo *TII = ST.getInstrInfo();
570   const SIRegisterInfo &TRI = TII->getRegisterInfo();
571 
572   Info.UsesFlatScratch = MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_LO) ||
573                          MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_HI);
574 
575   // Even if FLAT_SCRATCH is implicitly used, it has no effect if flat
576   // instructions aren't used to access the scratch buffer. Inline assembly may
577   // need it though.
578   //
579   // If we only have implicit uses of flat_scr on flat instructions, it is not
580   // really needed.
581   if (Info.UsesFlatScratch && !MFI->hasFlatScratchInit() &&
582       (!hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR) &&
583        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_LO) &&
584        !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_HI))) {
585     Info.UsesFlatScratch = false;
586   }
587 
588   Info.HasDynamicallySizedStack = FrameInfo.hasVarSizedObjects();
589   Info.PrivateSegmentSize = FrameInfo.getStackSize();
590   if (MFI->isStackRealigned())
591     Info.PrivateSegmentSize += FrameInfo.getMaxAlignment();
592 
593 
594   Info.UsesVCC = MRI.isPhysRegUsed(AMDGPU::VCC_LO) ||
595                  MRI.isPhysRegUsed(AMDGPU::VCC_HI);
596 
597   // If there are no calls, MachineRegisterInfo can tell us the used register
598   // count easily.
599   // A tail call isn't considered a call for MachineFrameInfo's purposes.
600   if (!FrameInfo.hasCalls() && !FrameInfo.hasTailCall()) {
601     MCPhysReg HighestVGPRReg = AMDGPU::NoRegister;
602     for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) {
603       if (MRI.isPhysRegUsed(Reg)) {
604         HighestVGPRReg = Reg;
605         break;
606       }
607     }
608 
609     MCPhysReg HighestSGPRReg = AMDGPU::NoRegister;
610     for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) {
611       if (MRI.isPhysRegUsed(Reg)) {
612         HighestSGPRReg = Reg;
613         break;
614       }
615     }
616 
617     // We found the maximum register index. They start at 0, so add one to get the
618     // number of registers.
619     Info.NumVGPR = HighestVGPRReg == AMDGPU::NoRegister ? 0 :
620       TRI.getHWRegIndex(HighestVGPRReg) + 1;
621     Info.NumExplicitSGPR = HighestSGPRReg == AMDGPU::NoRegister ? 0 :
622       TRI.getHWRegIndex(HighestSGPRReg) + 1;
623 
624     return Info;
625   }
626 
627   int32_t MaxVGPR = -1;
628   int32_t MaxSGPR = -1;
629   uint64_t CalleeFrameSize = 0;
630 
631   for (const MachineBasicBlock &MBB : MF) {
632     for (const MachineInstr &MI : MBB) {
633       // TODO: Check regmasks? Do they occur anywhere except calls?
634       for (const MachineOperand &MO : MI.operands()) {
635         unsigned Width = 0;
636         bool IsSGPR = false;
637 
638         if (!MO.isReg())
639           continue;
640 
641         unsigned Reg = MO.getReg();
642         switch (Reg) {
643         case AMDGPU::EXEC:
644         case AMDGPU::EXEC_LO:
645         case AMDGPU::EXEC_HI:
646         case AMDGPU::SCC:
647         case AMDGPU::M0:
648         case AMDGPU::SRC_SHARED_BASE:
649         case AMDGPU::SRC_SHARED_LIMIT:
650         case AMDGPU::SRC_PRIVATE_BASE:
651         case AMDGPU::SRC_PRIVATE_LIMIT:
652           continue;
653 
654         case AMDGPU::NoRegister:
655           assert(MI.isDebugValue());
656           continue;
657 
658         case AMDGPU::VCC:
659         case AMDGPU::VCC_LO:
660         case AMDGPU::VCC_HI:
661           Info.UsesVCC = true;
662           continue;
663 
664         case AMDGPU::FLAT_SCR:
665         case AMDGPU::FLAT_SCR_LO:
666         case AMDGPU::FLAT_SCR_HI:
667           continue;
668 
669         case AMDGPU::XNACK_MASK:
670         case AMDGPU::XNACK_MASK_LO:
671         case AMDGPU::XNACK_MASK_HI:
672           llvm_unreachable("xnack_mask registers should not be used");
673 
674         case AMDGPU::TBA:
675         case AMDGPU::TBA_LO:
676         case AMDGPU::TBA_HI:
677         case AMDGPU::TMA:
678         case AMDGPU::TMA_LO:
679         case AMDGPU::TMA_HI:
680           llvm_unreachable("trap handler registers should not be used");
681 
682         default:
683           break;
684         }
685 
686         if (AMDGPU::SReg_32RegClass.contains(Reg)) {
687           assert(!AMDGPU::TTMP_32RegClass.contains(Reg) &&
688                  "trap handler registers should not be used");
689           IsSGPR = true;
690           Width = 1;
691         } else if (AMDGPU::VGPR_32RegClass.contains(Reg)) {
692           IsSGPR = false;
693           Width = 1;
694         } else if (AMDGPU::SReg_64RegClass.contains(Reg)) {
695           assert(!AMDGPU::TTMP_64RegClass.contains(Reg) &&
696                  "trap handler registers should not be used");
697           IsSGPR = true;
698           Width = 2;
699         } else if (AMDGPU::VReg_64RegClass.contains(Reg)) {
700           IsSGPR = false;
701           Width = 2;
702         } else if (AMDGPU::VReg_96RegClass.contains(Reg)) {
703           IsSGPR = false;
704           Width = 3;
705         } else if (AMDGPU::SReg_128RegClass.contains(Reg)) {
706           assert(!AMDGPU::TTMP_128RegClass.contains(Reg) &&
707             "trap handler registers should not be used");
708           IsSGPR = true;
709           Width = 4;
710         } else if (AMDGPU::VReg_128RegClass.contains(Reg)) {
711           IsSGPR = false;
712           Width = 4;
713         } else if (AMDGPU::SReg_256RegClass.contains(Reg)) {
714           assert(!AMDGPU::TTMP_256RegClass.contains(Reg) &&
715             "trap handler registers should not be used");
716           IsSGPR = true;
717           Width = 8;
718         } else if (AMDGPU::VReg_256RegClass.contains(Reg)) {
719           IsSGPR = false;
720           Width = 8;
721         } else if (AMDGPU::SReg_512RegClass.contains(Reg)) {
722           assert(!AMDGPU::TTMP_512RegClass.contains(Reg) &&
723             "trap handler registers should not be used");
724           IsSGPR = true;
725           Width = 16;
726         } else if (AMDGPU::VReg_512RegClass.contains(Reg)) {
727           IsSGPR = false;
728           Width = 16;
729         } else {
730           llvm_unreachable("Unknown register class");
731         }
732         unsigned HWReg = TRI.getHWRegIndex(Reg);
733         int MaxUsed = HWReg + Width - 1;
734         if (IsSGPR) {
735           MaxSGPR = MaxUsed > MaxSGPR ? MaxUsed : MaxSGPR;
736         } else {
737           MaxVGPR = MaxUsed > MaxVGPR ? MaxUsed : MaxVGPR;
738         }
739       }
740 
741       if (MI.isCall()) {
742         // Pseudo used just to encode the underlying global. Is there a better
743         // way to track this?
744 
745         const MachineOperand *CalleeOp
746           = TII->getNamedOperand(MI, AMDGPU::OpName::callee);
747         const Function *Callee = cast<Function>(CalleeOp->getGlobal());
748         if (Callee->isDeclaration()) {
749           // If this is a call to an external function, we can't do much. Make
750           // conservative guesses.
751 
752           // 48 SGPRs - vcc, - flat_scr, -xnack
753           int MaxSGPRGuess = 47 - getNumExtraSGPRs(ST, true,
754                                                    ST.hasFlatAddressSpace());
755           MaxSGPR = std::max(MaxSGPR, MaxSGPRGuess);
756           MaxVGPR = std::max(MaxVGPR, 23);
757 
758           CalleeFrameSize = std::max(CalleeFrameSize, UINT64_C(16384));
759           Info.UsesVCC = true;
760           Info.UsesFlatScratch = ST.hasFlatAddressSpace();
761           Info.HasDynamicallySizedStack = true;
762         } else {
763           // We force CodeGen to run in SCC order, so the callee's register
764           // usage etc. should be the cumulative usage of all callees.
765           auto I = CallGraphResourceInfo.find(Callee);
766           assert(I != CallGraphResourceInfo.end() &&
767                  "callee should have been handled before caller");
768 
769           MaxSGPR = std::max(I->second.NumExplicitSGPR - 1, MaxSGPR);
770           MaxVGPR = std::max(I->second.NumVGPR - 1, MaxVGPR);
771           CalleeFrameSize
772             = std::max(I->second.PrivateSegmentSize, CalleeFrameSize);
773           Info.UsesVCC |= I->second.UsesVCC;
774           Info.UsesFlatScratch |= I->second.UsesFlatScratch;
775           Info.HasDynamicallySizedStack |= I->second.HasDynamicallySizedStack;
776           Info.HasRecursion |= I->second.HasRecursion;
777         }
778 
779         if (!Callee->doesNotRecurse())
780           Info.HasRecursion = true;
781       }
782     }
783   }
784 
785   Info.NumExplicitSGPR = MaxSGPR + 1;
786   Info.NumVGPR = MaxVGPR + 1;
787   Info.PrivateSegmentSize += CalleeFrameSize;
788 
789   return Info;
790 }
791 
792 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
793                                         const MachineFunction &MF) {
794   SIFunctionResourceInfo Info = analyzeResourceUsage(MF);
795 
796   ProgInfo.NumVGPR = Info.NumVGPR;
797   ProgInfo.NumSGPR = Info.NumExplicitSGPR;
798   ProgInfo.ScratchSize = Info.PrivateSegmentSize;
799   ProgInfo.VCCUsed = Info.UsesVCC;
800   ProgInfo.FlatUsed = Info.UsesFlatScratch;
801   ProgInfo.DynamicCallStack = Info.HasDynamicallySizedStack || Info.HasRecursion;
802 
803   if (!isUInt<32>(ProgInfo.ScratchSize)) {
804     DiagnosticInfoStackSize DiagStackSize(MF.getFunction(),
805                                           ProgInfo.ScratchSize, DS_Error);
806     MF.getFunction().getContext().diagnose(DiagStackSize);
807   }
808 
809   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
810   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
811   const SIInstrInfo *TII = STM.getInstrInfo();
812   const SIRegisterInfo *RI = &TII->getRegisterInfo();
813 
814   unsigned ExtraSGPRs = getNumExtraSGPRs(STM,
815                                          ProgInfo.VCCUsed,
816                                          ProgInfo.FlatUsed);
817   unsigned ExtraVGPRs = STM.getReservedNumVGPRs(MF);
818 
819   // Check the addressable register limit before we add ExtraSGPRs.
820   if (STM.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
821       !STM.hasSGPRInitBug()) {
822     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
823     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
824       // This can happen due to a compiler bug or when using inline asm.
825       LLVMContext &Ctx = MF.getFunction().getContext();
826       DiagnosticInfoResourceLimit Diag(MF.getFunction(),
827                                        "addressable scalar registers",
828                                        ProgInfo.NumSGPR, DS_Error,
829                                        DK_ResourceLimit,
830                                        MaxAddressableNumSGPRs);
831       Ctx.diagnose(Diag);
832       ProgInfo.NumSGPR = MaxAddressableNumSGPRs - 1;
833     }
834   }
835 
836   // Account for extra SGPRs and VGPRs reserved for debugger use.
837   ProgInfo.NumSGPR += ExtraSGPRs;
838   ProgInfo.NumVGPR += ExtraVGPRs;
839 
840   // Ensure there are enough SGPRs and VGPRs for wave dispatch, where wave
841   // dispatch registers are function args.
842   unsigned WaveDispatchNumSGPR = 0, WaveDispatchNumVGPR = 0;
843   for (auto &Arg : MF.getFunction().args()) {
844     unsigned NumRegs = (Arg.getType()->getPrimitiveSizeInBits() + 31) / 32;
845     if (Arg.hasAttribute(Attribute::InReg))
846       WaveDispatchNumSGPR += NumRegs;
847     else
848       WaveDispatchNumVGPR += NumRegs;
849   }
850   ProgInfo.NumSGPR = std::max(ProgInfo.NumSGPR, WaveDispatchNumSGPR);
851   ProgInfo.NumVGPR = std::max(ProgInfo.NumVGPR, WaveDispatchNumVGPR);
852 
853   // Adjust number of registers used to meet default/requested minimum/maximum
854   // number of waves per execution unit request.
855   ProgInfo.NumSGPRsForWavesPerEU = std::max(
856     std::max(ProgInfo.NumSGPR, 1u), STM.getMinNumSGPRs(MFI->getMaxWavesPerEU()));
857   ProgInfo.NumVGPRsForWavesPerEU = std::max(
858     std::max(ProgInfo.NumVGPR, 1u), STM.getMinNumVGPRs(MFI->getMaxWavesPerEU()));
859 
860   if (STM.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ||
861       STM.hasSGPRInitBug()) {
862     unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
863     if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
864       // This can happen due to a compiler bug or when using inline asm to use
865       // the registers which are usually reserved for vcc etc.
866       LLVMContext &Ctx = MF.getFunction().getContext();
867       DiagnosticInfoResourceLimit Diag(MF.getFunction(),
868                                        "scalar registers",
869                                        ProgInfo.NumSGPR, DS_Error,
870                                        DK_ResourceLimit,
871                                        MaxAddressableNumSGPRs);
872       Ctx.diagnose(Diag);
873       ProgInfo.NumSGPR = MaxAddressableNumSGPRs;
874       ProgInfo.NumSGPRsForWavesPerEU = MaxAddressableNumSGPRs;
875     }
876   }
877 
878   if (STM.hasSGPRInitBug()) {
879     ProgInfo.NumSGPR =
880         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
881     ProgInfo.NumSGPRsForWavesPerEU =
882         AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
883   }
884 
885   if (MFI->getNumUserSGPRs() > STM.getMaxNumUserSGPRs()) {
886     LLVMContext &Ctx = MF.getFunction().getContext();
887     DiagnosticInfoResourceLimit Diag(MF.getFunction(), "user SGPRs",
888                                      MFI->getNumUserSGPRs(), DS_Error);
889     Ctx.diagnose(Diag);
890   }
891 
892   if (MFI->getLDSSize() > static_cast<unsigned>(STM.getLocalMemorySize())) {
893     LLVMContext &Ctx = MF.getFunction().getContext();
894     DiagnosticInfoResourceLimit Diag(MF.getFunction(), "local memory",
895                                      MFI->getLDSSize(), DS_Error);
896     Ctx.diagnose(Diag);
897   }
898 
899   // SGPRBlocks is actual number of SGPR blocks minus 1.
900   ProgInfo.SGPRBlocks = alignTo(ProgInfo.NumSGPRsForWavesPerEU,
901                                 STM.getSGPREncodingGranule());
902   ProgInfo.SGPRBlocks = ProgInfo.SGPRBlocks / STM.getSGPREncodingGranule() - 1;
903 
904   // VGPRBlocks is actual number of VGPR blocks minus 1.
905   ProgInfo.VGPRBlocks = alignTo(ProgInfo.NumVGPRsForWavesPerEU,
906                                 STM.getVGPREncodingGranule());
907   ProgInfo.VGPRBlocks = ProgInfo.VGPRBlocks / STM.getVGPREncodingGranule() - 1;
908 
909   // Record first reserved VGPR and number of reserved VGPRs.
910   ProgInfo.ReservedVGPRFirst = STM.debuggerReserveRegs() ? ProgInfo.NumVGPR : 0;
911   ProgInfo.ReservedVGPRCount = STM.getReservedNumVGPRs(MF);
912 
913   // Update DebuggerWavefrontPrivateSegmentOffsetSGPR and
914   // DebuggerPrivateSegmentBufferSGPR fields if "amdgpu-debugger-emit-prologue"
915   // attribute was requested.
916   if (STM.debuggerEmitPrologue()) {
917     ProgInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR =
918       RI->getHWRegIndex(MFI->getScratchWaveOffsetReg());
919     ProgInfo.DebuggerPrivateSegmentBufferSGPR =
920       RI->getHWRegIndex(MFI->getScratchRSrcReg());
921   }
922 
923   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
924   // register.
925   ProgInfo.FloatMode = getFPMode(MF);
926 
927   ProgInfo.IEEEMode = STM.enableIEEEBit(MF);
928 
929   // Make clamp modifier on NaN input returns 0.
930   ProgInfo.DX10Clamp = STM.enableDX10Clamp();
931 
932   unsigned LDSAlignShift;
933   if (STM.getGeneration() < SISubtarget::SEA_ISLANDS) {
934     // LDS is allocated in 64 dword blocks.
935     LDSAlignShift = 8;
936   } else {
937     // LDS is allocated in 128 dword blocks.
938     LDSAlignShift = 9;
939   }
940 
941   unsigned LDSSpillSize =
942     MFI->getLDSWaveSpillSize() * MFI->getMaxFlatWorkGroupSize();
943 
944   ProgInfo.LDSSize = MFI->getLDSSize() + LDSSpillSize;
945   ProgInfo.LDSBlocks =
946       alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
947 
948   // Scratch is allocated in 256 dword blocks.
949   unsigned ScratchAlignShift = 10;
950   // We need to program the hardware with the amount of scratch memory that
951   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
952   // scratch memory used per thread.
953   ProgInfo.ScratchBlocks =
954       alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
955               1ULL << ScratchAlignShift) >>
956       ScratchAlignShift;
957 
958   ProgInfo.ComputePGMRSrc1 =
959       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
960       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
961       S_00B848_PRIORITY(ProgInfo.Priority) |
962       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
963       S_00B848_PRIV(ProgInfo.Priv) |
964       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
965       S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
966       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
967 
968   // 0 = X, 1 = XY, 2 = XYZ
969   unsigned TIDIGCompCnt = 0;
970   if (MFI->hasWorkItemIDZ())
971     TIDIGCompCnt = 2;
972   else if (MFI->hasWorkItemIDY())
973     TIDIGCompCnt = 1;
974 
975   ProgInfo.ComputePGMRSrc2 =
976       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
977       S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
978       S_00B84C_TRAP_HANDLER(STM.isTrapHandlerEnabled()) |
979       S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
980       S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
981       S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
982       S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
983       S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
984       S_00B84C_EXCP_EN_MSB(0) |
985       // For AMDHSA, LDS_SIZE must be zero, as it is populated by the CP.
986       S_00B84C_LDS_SIZE(STM.isAmdHsaOS() ? 0 : ProgInfo.LDSBlocks) |
987       S_00B84C_EXCP_EN(0);
988 }
989 
990 static unsigned getRsrcReg(CallingConv::ID CallConv) {
991   switch (CallConv) {
992   default: LLVM_FALLTHROUGH;
993   case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
994   case CallingConv::AMDGPU_LS: return R_00B528_SPI_SHADER_PGM_RSRC1_LS;
995   case CallingConv::AMDGPU_HS: return R_00B428_SPI_SHADER_PGM_RSRC1_HS;
996   case CallingConv::AMDGPU_ES: return R_00B328_SPI_SHADER_PGM_RSRC1_ES;
997   case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
998   case CallingConv::AMDGPU_VS: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
999   case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
1000   }
1001 }
1002 
1003 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
1004                                          const SIProgramInfo &CurrentProgramInfo) {
1005   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
1006   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1007   unsigned RsrcReg = getRsrcReg(MF.getFunction().getCallingConv());
1008 
1009   if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
1010     OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
1011 
1012     OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc1, 4);
1013 
1014     OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
1015     OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc2, 4);
1016 
1017     OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
1018     OutStreamer->EmitIntValue(S_00B860_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
1019 
1020     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
1021     // 0" comment but I don't see a corresponding field in the register spec.
1022   } else {
1023     OutStreamer->EmitIntValue(RsrcReg, 4);
1024     OutStreamer->EmitIntValue(S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
1025                               S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks), 4);
1026     if (STM.isVGPRSpillingEnabled(MF.getFunction())) {
1027       OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
1028       OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
1029     }
1030   }
1031 
1032   if (MF.getFunction().getCallingConv() == CallingConv::AMDGPU_PS) {
1033     OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
1034     OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks), 4);
1035     OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
1036     OutStreamer->EmitIntValue(MFI->getPSInputEnable(), 4);
1037     OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
1038     OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4);
1039   }
1040 
1041   OutStreamer->EmitIntValue(R_SPILLED_SGPRS, 4);
1042   OutStreamer->EmitIntValue(MFI->getNumSpilledSGPRs(), 4);
1043   OutStreamer->EmitIntValue(R_SPILLED_VGPRS, 4);
1044   OutStreamer->EmitIntValue(MFI->getNumSpilledVGPRs(), 4);
1045 }
1046 
1047 // This is the equivalent of EmitProgramInfoSI above, but for when the OS type
1048 // is AMDPAL.  It stores each compute/SPI register setting and other PAL
1049 // metadata items into the PALMetadataMap, combining with any provided by the
1050 // frontend as LLVM metadata. Once all functions are written, PALMetadataMap is
1051 // then written as a single block in the .note section.
1052 void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
1053        const SIProgramInfo &CurrentProgramInfo) {
1054   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1055   // Given the calling convention, calculate the register number for rsrc1. In
1056   // principle the register number could change in future hardware, but we know
1057   // it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so
1058   // we can use the same fixed value that .AMDGPU.config has for Mesa. Note
1059   // that we use a register number rather than a byte offset, so we need to
1060   // divide by 4.
1061   unsigned Rsrc1Reg = getRsrcReg(MF.getFunction().getCallingConv()) / 4;
1062   unsigned Rsrc2Reg = Rsrc1Reg + 1;
1063   // Also calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used
1064   // with a constant offset to access any non-register shader-specific PAL
1065   // metadata key.
1066   unsigned ScratchSizeKey = PALMD::Key::CS_SCRATCH_SIZE;
1067   switch (MF.getFunction().getCallingConv()) {
1068     case CallingConv::AMDGPU_PS:
1069       ScratchSizeKey = PALMD::Key::PS_SCRATCH_SIZE;
1070       break;
1071     case CallingConv::AMDGPU_VS:
1072       ScratchSizeKey = PALMD::Key::VS_SCRATCH_SIZE;
1073       break;
1074     case CallingConv::AMDGPU_GS:
1075       ScratchSizeKey = PALMD::Key::GS_SCRATCH_SIZE;
1076       break;
1077     case CallingConv::AMDGPU_ES:
1078       ScratchSizeKey = PALMD::Key::ES_SCRATCH_SIZE;
1079       break;
1080     case CallingConv::AMDGPU_HS:
1081       ScratchSizeKey = PALMD::Key::HS_SCRATCH_SIZE;
1082       break;
1083     case CallingConv::AMDGPU_LS:
1084       ScratchSizeKey = PALMD::Key::LS_SCRATCH_SIZE;
1085       break;
1086   }
1087   unsigned NumUsedVgprsKey = ScratchSizeKey +
1088       PALMD::Key::VS_NUM_USED_VGPRS - PALMD::Key::VS_SCRATCH_SIZE;
1089   unsigned NumUsedSgprsKey = ScratchSizeKey +
1090       PALMD::Key::VS_NUM_USED_SGPRS - PALMD::Key::VS_SCRATCH_SIZE;
1091   PALMetadataMap[NumUsedVgprsKey] = CurrentProgramInfo.NumVGPRsForWavesPerEU;
1092   PALMetadataMap[NumUsedSgprsKey] = CurrentProgramInfo.NumSGPRsForWavesPerEU;
1093   if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
1094     PALMetadataMap[Rsrc1Reg] |= CurrentProgramInfo.ComputePGMRSrc1;
1095     PALMetadataMap[Rsrc2Reg] |= CurrentProgramInfo.ComputePGMRSrc2;
1096     // ScratchSize is in bytes, 16 aligned.
1097     PALMetadataMap[ScratchSizeKey] |=
1098         alignTo(CurrentProgramInfo.ScratchSize, 16);
1099   } else {
1100     PALMetadataMap[Rsrc1Reg] |= S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
1101         S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks);
1102     if (CurrentProgramInfo.ScratchBlocks > 0)
1103       PALMetadataMap[Rsrc2Reg] |= S_00B84C_SCRATCH_EN(1);
1104     // ScratchSize is in bytes, 16 aligned.
1105     PALMetadataMap[ScratchSizeKey] |=
1106         alignTo(CurrentProgramInfo.ScratchSize, 16);
1107   }
1108   if (MF.getFunction().getCallingConv() == CallingConv::AMDGPU_PS) {
1109     PALMetadataMap[Rsrc2Reg] |=
1110         S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks);
1111     PALMetadataMap[R_0286CC_SPI_PS_INPUT_ENA / 4] |= MFI->getPSInputEnable();
1112     PALMetadataMap[R_0286D0_SPI_PS_INPUT_ADDR / 4] |= MFI->getPSInputAddr();
1113   }
1114 }
1115 
1116 // This is supposed to be log2(Size)
1117 static amd_element_byte_size_t getElementByteSizeValue(unsigned Size) {
1118   switch (Size) {
1119   case 4:
1120     return AMD_ELEMENT_4_BYTES;
1121   case 8:
1122     return AMD_ELEMENT_8_BYTES;
1123   case 16:
1124     return AMD_ELEMENT_16_BYTES;
1125   default:
1126     llvm_unreachable("invalid private_element_size");
1127   }
1128 }
1129 
1130 void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out,
1131                                         const SIProgramInfo &CurrentProgramInfo,
1132                                         const MachineFunction &MF) const {
1133   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1134   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
1135 
1136   AMDGPU::initDefaultAMDKernelCodeT(Out, STM.getFeatureBits());
1137 
1138   Out.compute_pgm_resource_registers =
1139       CurrentProgramInfo.ComputePGMRSrc1 |
1140       (CurrentProgramInfo.ComputePGMRSrc2 << 32);
1141   Out.code_properties = AMD_CODE_PROPERTY_IS_PTR64;
1142 
1143   if (CurrentProgramInfo.DynamicCallStack)
1144     Out.code_properties |= AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK;
1145 
1146   AMD_HSA_BITS_SET(Out.code_properties,
1147                    AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE,
1148                    getElementByteSizeValue(STM.getMaxPrivateElementSize()));
1149 
1150   if (MFI->hasPrivateSegmentBuffer()) {
1151     Out.code_properties |=
1152       AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
1153   }
1154 
1155   if (MFI->hasDispatchPtr())
1156     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
1157 
1158   if (MFI->hasQueuePtr())
1159     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
1160 
1161   if (MFI->hasKernargSegmentPtr())
1162     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
1163 
1164   if (MFI->hasDispatchID())
1165     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
1166 
1167   if (MFI->hasFlatScratchInit())
1168     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
1169 
1170   if (MFI->hasGridWorkgroupCountX()) {
1171     Out.code_properties |=
1172       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X;
1173   }
1174 
1175   if (MFI->hasGridWorkgroupCountY()) {
1176     Out.code_properties |=
1177       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y;
1178   }
1179 
1180   if (MFI->hasGridWorkgroupCountZ()) {
1181     Out.code_properties |=
1182       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z;
1183   }
1184 
1185   if (MFI->hasDispatchPtr())
1186     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
1187 
1188   if (STM.debuggerSupported())
1189     Out.code_properties |= AMD_CODE_PROPERTY_IS_DEBUG_SUPPORTED;
1190 
1191   if (STM.isXNACKEnabled())
1192     Out.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED;
1193 
1194   // FIXME: Should use getKernArgSize
1195   Out.kernarg_segment_byte_size =
1196     STM.getKernArgSegmentSize(MF, MFI->getABIArgOffset());
1197   Out.wavefront_sgpr_count = CurrentProgramInfo.NumSGPR;
1198   Out.workitem_vgpr_count = CurrentProgramInfo.NumVGPR;
1199   Out.workitem_private_segment_byte_size = CurrentProgramInfo.ScratchSize;
1200   Out.workgroup_group_segment_byte_size = CurrentProgramInfo.LDSSize;
1201   Out.reserved_vgpr_first = CurrentProgramInfo.ReservedVGPRFirst;
1202   Out.reserved_vgpr_count = CurrentProgramInfo.ReservedVGPRCount;
1203 
1204   // These alignment values are specified in powers of two, so alignment =
1205   // 2^n.  The minimum alignment is 2^4 = 16.
1206   Out.kernarg_segment_alignment = std::max((size_t)4,
1207       countTrailingZeros(MFI->getMaxKernArgAlign()));
1208 
1209   if (STM.debuggerEmitPrologue()) {
1210     Out.debug_wavefront_private_segment_offset_sgpr =
1211       CurrentProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR;
1212     Out.debug_private_segment_buffer_sgpr =
1213       CurrentProgramInfo.DebuggerPrivateSegmentBufferSGPR;
1214   }
1215 }
1216 
1217 AMDGPU::HSAMD::Kernel::CodeProps::Metadata AMDGPUAsmPrinter::getHSACodeProps(
1218     const MachineFunction &MF,
1219     const SIProgramInfo &ProgramInfo) const {
1220   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
1221   const SIMachineFunctionInfo &MFI = *MF.getInfo<SIMachineFunctionInfo>();
1222   HSAMD::Kernel::CodeProps::Metadata HSACodeProps;
1223 
1224   HSACodeProps.mKernargSegmentSize =
1225       STM.getKernArgSegmentSize(MF, MFI.getABIArgOffset());
1226   HSACodeProps.mGroupSegmentFixedSize = ProgramInfo.LDSSize;
1227   HSACodeProps.mPrivateSegmentFixedSize = ProgramInfo.ScratchSize;
1228   HSACodeProps.mKernargSegmentAlign =
1229       std::max(uint32_t(4), MFI.getMaxKernArgAlign());
1230   HSACodeProps.mWavefrontSize = STM.getWavefrontSize();
1231   HSACodeProps.mNumSGPRs = CurrentProgramInfo.NumSGPR;
1232   HSACodeProps.mNumVGPRs = CurrentProgramInfo.NumVGPR;
1233   HSACodeProps.mMaxFlatWorkGroupSize = MFI.getMaxFlatWorkGroupSize();
1234   HSACodeProps.mIsDynamicCallStack = ProgramInfo.DynamicCallStack;
1235   HSACodeProps.mIsXNACKEnabled = STM.isXNACKEnabled();
1236   HSACodeProps.mNumSpilledSGPRs = MFI.getNumSpilledSGPRs();
1237   HSACodeProps.mNumSpilledVGPRs = MFI.getNumSpilledVGPRs();
1238 
1239   return HSACodeProps;
1240 }
1241 
1242 AMDGPU::HSAMD::Kernel::DebugProps::Metadata AMDGPUAsmPrinter::getHSADebugProps(
1243     const MachineFunction &MF,
1244     const SIProgramInfo &ProgramInfo) const {
1245   const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
1246   HSAMD::Kernel::DebugProps::Metadata HSADebugProps;
1247 
1248   if (!STM.debuggerSupported())
1249     return HSADebugProps;
1250 
1251   HSADebugProps.mDebuggerABIVersion.push_back(1);
1252   HSADebugProps.mDebuggerABIVersion.push_back(0);
1253   HSADebugProps.mReservedNumVGPRs = ProgramInfo.ReservedVGPRCount;
1254   HSADebugProps.mReservedFirstVGPR = ProgramInfo.ReservedVGPRFirst;
1255 
1256   if (STM.debuggerEmitPrologue()) {
1257     HSADebugProps.mPrivateSegmentBufferSGPR =
1258         ProgramInfo.DebuggerPrivateSegmentBufferSGPR;
1259     HSADebugProps.mWavefrontPrivateSegmentOffsetSGPR =
1260         ProgramInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR;
1261   }
1262 
1263   return HSADebugProps;
1264 }
1265 
1266 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
1267                                        unsigned AsmVariant,
1268                                        const char *ExtraCode, raw_ostream &O) {
1269   // First try the generic code, which knows about modifiers like 'c' and 'n'.
1270   if (!AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O))
1271     return false;
1272 
1273   if (ExtraCode && ExtraCode[0]) {
1274     if (ExtraCode[1] != 0)
1275       return true; // Unknown modifier.
1276 
1277     switch (ExtraCode[0]) {
1278     case 'r':
1279       break;
1280     default:
1281       return true;
1282     }
1283   }
1284 
1285   // TODO: Should be able to support other operand types like globals.
1286   const MachineOperand &MO = MI->getOperand(OpNo);
1287   if (MO.isReg()) {
1288     AMDGPUInstPrinter::printRegOperand(MO.getReg(), O,
1289                                        *MF->getSubtarget().getRegisterInfo());
1290     return false;
1291   }
1292 
1293   return true;
1294 }
1295