1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
15 //
16 //===----------------------------------------------------------------------===//
17 //
18 
19 #include "AMDGPUAsmPrinter.h"
20 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
21 #include "InstPrinter/AMDGPUInstPrinter.h"
22 #include "Utils/AMDGPUBaseInfo.h"
23 #include "AMDGPU.h"
24 #include "AMDKernelCodeT.h"
25 #include "AMDGPUSubtarget.h"
26 #include "R600Defines.h"
27 #include "R600MachineFunctionInfo.h"
28 #include "R600RegisterInfo.h"
29 #include "SIDefines.h"
30 #include "SIMachineFunctionInfo.h"
31 #include "SIRegisterInfo.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/MC/MCContext.h"
34 #include "llvm/MC/MCSectionELF.h"
35 #include "llvm/MC/MCStreamer.h"
36 #include "llvm/Support/ELF.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/TargetRegistry.h"
39 #include "llvm/Target/TargetLoweringObjectFile.h"
40 
41 using namespace llvm;
42 
43 // TODO: This should get the default rounding mode from the kernel. We just set
44 // the default here, but this could change if the OpenCL rounding mode pragmas
45 // are used.
46 //
47 // The denormal mode here should match what is reported by the OpenCL runtime
48 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
49 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
50 //
51 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
52 // precision, and leaves single precision to flush all and does not report
53 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
54 // CL_FP_DENORM for both.
55 //
56 // FIXME: It seems some instructions do not support single precision denormals
57 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
58 // and sin_f32, cos_f32 on most parts).
59 
60 // We want to use these instructions, and using fp32 denormals also causes
61 // instructions to run at the double precision rate for the device so it's
62 // probably best to just report no single precision denormals.
63 static uint32_t getFPMode(const MachineFunction &F) {
64   const AMDGPUSubtarget& ST = F.getSubtarget<AMDGPUSubtarget>();
65   // TODO: Is there any real use for the flush in only / flush out only modes?
66 
67   uint32_t FP32Denormals =
68     ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
69 
70   uint32_t FP64Denormals =
71     ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
72 
73   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
74          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
75          FP_DENORM_MODE_SP(FP32Denormals) |
76          FP_DENORM_MODE_DP(FP64Denormals);
77 }
78 
79 static AsmPrinter *
80 createAMDGPUAsmPrinterPass(TargetMachine &tm,
81                            std::unique_ptr<MCStreamer> &&Streamer) {
82   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
83 }
84 
85 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
86   TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
87   TargetRegistry::RegisterAsmPrinter(TheGCNTarget, createAMDGPUAsmPrinterPass);
88 }
89 
90 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
91                                    std::unique_ptr<MCStreamer> Streamer)
92     : AsmPrinter(TM, std::move(Streamer)) {}
93 
94 void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) {
95   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
96     return;
97 
98   // Need to construct an MCSubtargetInfo here in case we have no functions
99   // in the module.
100   std::unique_ptr<MCSubtargetInfo> STI(TM.getTarget().createMCSubtargetInfo(
101         TM.getTargetTriple().str(), TM.getTargetCPU(),
102         TM.getTargetFeatureString()));
103 
104   AMDGPUTargetStreamer *TS =
105       static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
106 
107   TS->EmitDirectiveHSACodeObjectVersion(2, 0);
108 
109   AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI->getFeatureBits());
110   TS->EmitDirectiveHSACodeObjectISA(ISA.Major, ISA.Minor, ISA.Stepping,
111                                     "AMD", "AMDGPU");
112 }
113 
114 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
115   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
116   SIProgramInfo KernelInfo;
117   if (STM.isAmdHsaOS()) {
118     getSIProgramInfo(KernelInfo, *MF);
119     EmitAmdKernelCodeT(*MF, KernelInfo);
120   }
121 }
122 
123 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
124   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
125   const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
126   if (MFI->isKernel() && STM.isAmdHsaOS()) {
127     AMDGPUTargetStreamer *TS =
128         static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
129     TS->EmitAMDGPUSymbolType(CurrentFnSym->getName(),
130                              ELF::STT_AMDGPU_HSA_KERNEL);
131   }
132 
133   AsmPrinter::EmitFunctionEntryLabel();
134 }
135 
136 void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
137 
138   // Group segment variables aren't emitted in HSA.
139   if (AMDGPU::isGroupSegment(GV))
140     return;
141 
142   AsmPrinter::EmitGlobalVariable(GV);
143 }
144 
145 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
146 
147   // The starting address of all shader programs must be 256 bytes aligned.
148   MF.setAlignment(8);
149 
150   SetupMachineFunction(MF);
151 
152   MCContext &Context = getObjFileLowering().getContext();
153   MCSectionELF *ConfigSection =
154       Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
155   OutStreamer->SwitchSection(ConfigSection);
156 
157   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
158   SIProgramInfo KernelInfo;
159   if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
160     getSIProgramInfo(KernelInfo, MF);
161     if (!STM.isAmdHsaOS()) {
162       EmitProgramInfoSI(MF, KernelInfo);
163     }
164   } else {
165     EmitProgramInfoR600(MF);
166   }
167 
168   DisasmLines.clear();
169   HexLines.clear();
170   DisasmLineMaxLen = 0;
171 
172   EmitFunctionBody();
173 
174   if (isVerbose()) {
175     MCSectionELF *CommentSection =
176         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
177     OutStreamer->SwitchSection(CommentSection);
178 
179     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
180       OutStreamer->emitRawComment(" Kernel info:", false);
181       OutStreamer->emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
182                                   false);
183       OutStreamer->emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
184                                   false);
185       OutStreamer->emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
186                                   false);
187       OutStreamer->emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
188                                   false);
189       OutStreamer->emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
190                                   false);
191       OutStreamer->emitRawComment(" ScratchSize: " + Twine(KernelInfo.ScratchSize),
192                                   false);
193       OutStreamer->emitRawComment(" LDSByteSize: " + Twine(KernelInfo.LDSSize) +
194                                   " bytes/workgroup (compile time only)", false);
195 
196       OutStreamer->emitRawComment(" ReservedVGPRFirst: " + Twine(KernelInfo.ReservedVGPRFirst),
197                                   false);
198       OutStreamer->emitRawComment(" ReservedVGPRCount: " + Twine(KernelInfo.ReservedVGPRCount),
199                                   false);
200 
201       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:USER_SGPR: " +
202                                   Twine(G_00B84C_USER_SGPR(KernelInfo.ComputePGMRSrc2)),
203                                   false);
204       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_X_EN: " +
205                                   Twine(G_00B84C_TGID_X_EN(KernelInfo.ComputePGMRSrc2)),
206                                   false);
207       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
208                                   Twine(G_00B84C_TGID_Y_EN(KernelInfo.ComputePGMRSrc2)),
209                                   false);
210       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
211                                   Twine(G_00B84C_TGID_Z_EN(KernelInfo.ComputePGMRSrc2)),
212                                   false);
213       OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
214                                   Twine(G_00B84C_TIDIG_COMP_CNT(KernelInfo.ComputePGMRSrc2)),
215                                   false);
216 
217     } else {
218       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
219       OutStreamer->emitRawComment(
220         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
221     }
222   }
223 
224   if (STM.dumpCode()) {
225 
226     OutStreamer->SwitchSection(
227         Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
228 
229     for (size_t i = 0; i < DisasmLines.size(); ++i) {
230       std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
231       Comment += " ; " + HexLines[i] + "\n";
232 
233       OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
234       OutStreamer->EmitBytes(StringRef(Comment));
235     }
236   }
237 
238   return false;
239 }
240 
241 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
242   unsigned MaxGPR = 0;
243   bool killPixel = false;
244   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
245   const R600RegisterInfo *RI =
246       static_cast<const R600RegisterInfo *>(STM.getRegisterInfo());
247   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
248 
249   for (const MachineBasicBlock &MBB : MF) {
250     for (const MachineInstr &MI : MBB) {
251       if (MI.getOpcode() == AMDGPU::KILLGT)
252         killPixel = true;
253       unsigned numOperands = MI.getNumOperands();
254       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
255         const MachineOperand &MO = MI.getOperand(op_idx);
256         if (!MO.isReg())
257           continue;
258         unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
259 
260         // Register with value > 127 aren't GPR
261         if (HWReg > 127)
262           continue;
263         MaxGPR = std::max(MaxGPR, HWReg);
264       }
265     }
266   }
267 
268   unsigned RsrcReg;
269   if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
270     // Evergreen / Northern Islands
271     switch (MF.getFunction()->getCallingConv()) {
272     default: // Fall through
273     case CallingConv::AMDGPU_CS: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
274     case CallingConv::AMDGPU_GS: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
275     case CallingConv::AMDGPU_PS: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
276     case CallingConv::AMDGPU_VS: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
277     }
278   } else {
279     // R600 / R700
280     switch (MF.getFunction()->getCallingConv()) {
281     default: // Fall through
282     case CallingConv::AMDGPU_GS: // Fall through
283     case CallingConv::AMDGPU_CS: // Fall through
284     case CallingConv::AMDGPU_VS: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
285     case CallingConv::AMDGPU_PS: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
286     }
287   }
288 
289   OutStreamer->EmitIntValue(RsrcReg, 4);
290   OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
291                            S_STACK_SIZE(MFI->StackSize), 4);
292   OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
293   OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
294 
295   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
296     OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
297     OutStreamer->EmitIntValue(alignTo(MFI->LDSSize, 4) >> 2, 4);
298   }
299 }
300 
301 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
302                                         const MachineFunction &MF) const {
303   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
304   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
305   uint64_t CodeSize = 0;
306   unsigned MaxSGPR = 0;
307   unsigned MaxVGPR = 0;
308   bool VCCUsed = false;
309   bool FlatUsed = false;
310   const SIRegisterInfo *RI =
311       static_cast<const SIRegisterInfo *>(STM.getRegisterInfo());
312 
313   for (const MachineBasicBlock &MBB : MF) {
314     for (const MachineInstr &MI : MBB) {
315       // TODO: CodeSize should account for multiple functions.
316 
317       // TODO: Should we count size of debug info?
318       if (MI.isDebugValue())
319         continue;
320 
321       // FIXME: This is reporting 0 for many instructions.
322       CodeSize += MI.getDesc().Size;
323 
324       unsigned numOperands = MI.getNumOperands();
325       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
326         const MachineOperand &MO = MI.getOperand(op_idx);
327         unsigned width = 0;
328         bool isSGPR = false;
329 
330         if (!MO.isReg())
331           continue;
332 
333         unsigned reg = MO.getReg();
334         switch (reg) {
335         case AMDGPU::EXEC:
336         case AMDGPU::EXEC_LO:
337         case AMDGPU::EXEC_HI:
338         case AMDGPU::SCC:
339         case AMDGPU::M0:
340           continue;
341 
342         case AMDGPU::VCC:
343         case AMDGPU::VCC_LO:
344         case AMDGPU::VCC_HI:
345           VCCUsed = true;
346           continue;
347 
348         case AMDGPU::FLAT_SCR:
349         case AMDGPU::FLAT_SCR_LO:
350         case AMDGPU::FLAT_SCR_HI:
351           FlatUsed = true;
352           continue;
353 
354         case AMDGPU::TBA:
355         case AMDGPU::TBA_LO:
356         case AMDGPU::TBA_HI:
357         case AMDGPU::TMA:
358         case AMDGPU::TMA_LO:
359         case AMDGPU::TMA_HI:
360           llvm_unreachable("Trap Handler registers should not be used");
361           continue;
362 
363         default:
364           break;
365         }
366 
367         if (AMDGPU::SReg_32RegClass.contains(reg)) {
368           if (AMDGPU::TTMP_32RegClass.contains(reg)) {
369             llvm_unreachable("Trap Handler registers should not be used");
370           }
371           isSGPR = true;
372           width = 1;
373         } else if (AMDGPU::VGPR_32RegClass.contains(reg)) {
374           isSGPR = false;
375           width = 1;
376         } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
377           if (AMDGPU::TTMP_64RegClass.contains(reg)) {
378             llvm_unreachable("Trap Handler registers should not be used");
379           }
380           isSGPR = true;
381           width = 2;
382         } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
383           isSGPR = false;
384           width = 2;
385         } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
386           isSGPR = false;
387           width = 3;
388         } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
389           isSGPR = true;
390           width = 4;
391         } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
392           isSGPR = false;
393           width = 4;
394         } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
395           isSGPR = true;
396           width = 8;
397         } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
398           isSGPR = false;
399           width = 8;
400         } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
401           isSGPR = true;
402           width = 16;
403         } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
404           isSGPR = false;
405           width = 16;
406         } else {
407           llvm_unreachable("Unknown register class");
408         }
409         unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
410         unsigned maxUsed = hwReg + width - 1;
411         if (isSGPR) {
412           MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
413         } else {
414           MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
415         }
416       }
417     }
418   }
419 
420   unsigned ExtraSGPRs = 0;
421 
422   if (VCCUsed)
423     ExtraSGPRs = 2;
424 
425   if (STM.getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS) {
426     if (FlatUsed)
427       ExtraSGPRs = 4;
428   } else {
429     if (STM.isXNACKEnabled())
430       ExtraSGPRs = 4;
431 
432     if (FlatUsed)
433       ExtraSGPRs = 6;
434   }
435 
436   MaxSGPR += ExtraSGPRs;
437 
438   // Update necessary Reserved* fields and max VGPRs used if
439   // "amdgpu-debugger-reserve-trap-regs" attribute was specified.
440   if (STM.debuggerReserveTrapVGPRs()) {
441     ProgInfo.ReservedVGPRFirst = MaxVGPR + 1;
442     ProgInfo.ReservedVGPRCount = MFI->getDebuggerReserveTrapVGPRCount();
443     MaxVGPR += MFI->getDebuggerReserveTrapVGPRCount();
444   }
445 
446   // We found the maximum register index. They start at 0, so add one to get the
447   // number of registers.
448   ProgInfo.NumVGPR = MaxVGPR + 1;
449   ProgInfo.NumSGPR = MaxSGPR + 1;
450 
451   if (STM.hasSGPRInitBug()) {
452     if (ProgInfo.NumSGPR > AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG) {
453       LLVMContext &Ctx = MF.getFunction()->getContext();
454       Ctx.emitError("too many SGPRs used with the SGPR init bug");
455     }
456 
457     ProgInfo.NumSGPR = AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG;
458   }
459 
460   if (MFI->NumUserSGPRs > STM.getMaxNumUserSGPRs()) {
461     LLVMContext &Ctx = MF.getFunction()->getContext();
462     Ctx.emitError("too many user SGPRs used");
463   }
464 
465   if (MFI->LDSSize > static_cast<unsigned>(STM.getLocalMemorySize())) {
466     LLVMContext &Ctx = MF.getFunction()->getContext();
467     Ctx.emitError("LDS size exceeds device maximum");
468   }
469 
470   ProgInfo.VGPRBlocks = (ProgInfo.NumVGPR - 1) / 4;
471   ProgInfo.SGPRBlocks = (ProgInfo.NumSGPR - 1) / 8;
472   // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
473   // register.
474   ProgInfo.FloatMode = getFPMode(MF);
475 
476   ProgInfo.IEEEMode = 0;
477 
478   // Make clamp modifier on NaN input returns 0.
479   ProgInfo.DX10Clamp = 1;
480 
481   const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
482   ProgInfo.ScratchSize = FrameInfo->getStackSize();
483 
484   ProgInfo.FlatUsed = FlatUsed;
485   ProgInfo.VCCUsed = VCCUsed;
486   ProgInfo.CodeLen = CodeSize;
487 
488   unsigned LDSAlignShift;
489   if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
490     // LDS is allocated in 64 dword blocks.
491     LDSAlignShift = 8;
492   } else {
493     // LDS is allocated in 128 dword blocks.
494     LDSAlignShift = 9;
495   }
496 
497   unsigned LDSSpillSize = MFI->LDSWaveSpillSize *
498                           MFI->getMaximumWorkGroupSize(MF);
499 
500   ProgInfo.LDSSize = MFI->LDSSize + LDSSpillSize;
501   ProgInfo.LDSBlocks =
502       alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
503 
504   // Scratch is allocated in 256 dword blocks.
505   unsigned ScratchAlignShift = 10;
506   // We need to program the hardware with the amount of scratch memory that
507   // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
508   // scratch memory used per thread.
509   ProgInfo.ScratchBlocks =
510       alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
511               1ULL << ScratchAlignShift) >>
512       ScratchAlignShift;
513 
514   ProgInfo.ComputePGMRSrc1 =
515       S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
516       S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
517       S_00B848_PRIORITY(ProgInfo.Priority) |
518       S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
519       S_00B848_PRIV(ProgInfo.Priv) |
520       S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
521       S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
522       S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
523 
524   // 0 = X, 1 = XY, 2 = XYZ
525   unsigned TIDIGCompCnt = 0;
526   if (MFI->hasWorkItemIDZ())
527     TIDIGCompCnt = 2;
528   else if (MFI->hasWorkItemIDY())
529     TIDIGCompCnt = 1;
530 
531   ProgInfo.ComputePGMRSrc2 =
532       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
533       S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
534       S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
535       S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
536       S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
537       S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
538       S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
539       S_00B84C_EXCP_EN_MSB(0) |
540       S_00B84C_LDS_SIZE(ProgInfo.LDSBlocks) |
541       S_00B84C_EXCP_EN(0);
542 }
543 
544 static unsigned getRsrcReg(CallingConv::ID CallConv) {
545   switch (CallConv) {
546   default: // Fall through
547   case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
548   case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
549   case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
550   case CallingConv::AMDGPU_VS: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
551   }
552 }
553 
554 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
555                                          const SIProgramInfo &KernelInfo) {
556   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
557   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
558   unsigned RsrcReg = getRsrcReg(MF.getFunction()->getCallingConv());
559 
560   if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
561     OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
562 
563     OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc1, 4);
564 
565     OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
566     OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc2, 4);
567 
568     OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
569     OutStreamer->EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4);
570 
571     // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
572     // 0" comment but I don't see a corresponding field in the register spec.
573   } else {
574     OutStreamer->EmitIntValue(RsrcReg, 4);
575     OutStreamer->EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
576                               S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4);
577     if (STM.isVGPRSpillingEnabled(*MF.getFunction())) {
578       OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
579       OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(KernelInfo.ScratchBlocks), 4);
580     }
581   }
582 
583   if (MF.getFunction()->getCallingConv() == CallingConv::AMDGPU_PS) {
584     OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
585     OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4);
586     OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
587     OutStreamer->EmitIntValue(MFI->PSInputEna, 4);
588     OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
589     OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4);
590   }
591 }
592 
593 // This is supposed to be log2(Size)
594 static amd_element_byte_size_t getElementByteSizeValue(unsigned Size) {
595   switch (Size) {
596   case 4:
597     return AMD_ELEMENT_4_BYTES;
598   case 8:
599     return AMD_ELEMENT_8_BYTES;
600   case 16:
601     return AMD_ELEMENT_16_BYTES;
602   default:
603     llvm_unreachable("invalid private_element_size");
604   }
605 }
606 
607 void AMDGPUAsmPrinter::EmitAmdKernelCodeT(const MachineFunction &MF,
608                                          const SIProgramInfo &KernelInfo) const {
609   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
610   const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
611   amd_kernel_code_t header;
612 
613   AMDGPU::initDefaultAMDKernelCodeT(header, STM.getFeatureBits());
614 
615   header.compute_pgm_resource_registers =
616       KernelInfo.ComputePGMRSrc1 |
617       (KernelInfo.ComputePGMRSrc2 << 32);
618   header.code_properties = AMD_CODE_PROPERTY_IS_PTR64;
619 
620 
621   AMD_HSA_BITS_SET(header.code_properties,
622                    AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE,
623                    getElementByteSizeValue(STM.getMaxPrivateElementSize()));
624 
625   if (MFI->hasPrivateSegmentBuffer()) {
626     header.code_properties |=
627       AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
628   }
629 
630   if (MFI->hasDispatchPtr())
631     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
632 
633   if (MFI->hasQueuePtr())
634     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
635 
636   if (MFI->hasKernargSegmentPtr())
637     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
638 
639   if (MFI->hasDispatchID())
640     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
641 
642   if (MFI->hasFlatScratchInit())
643     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
644 
645   // TODO: Private segment size
646 
647   if (MFI->hasGridWorkgroupCountX()) {
648     header.code_properties |=
649       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X;
650   }
651 
652   if (MFI->hasGridWorkgroupCountY()) {
653     header.code_properties |=
654       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y;
655   }
656 
657   if (MFI->hasGridWorkgroupCountZ()) {
658     header.code_properties |=
659       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z;
660   }
661 
662   if (MFI->hasDispatchPtr())
663     header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
664 
665   if (STM.isXNACKEnabled())
666     header.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED;
667 
668   header.kernarg_segment_byte_size = MFI->ABIArgOffset;
669   header.wavefront_sgpr_count = KernelInfo.NumSGPR;
670   header.workitem_vgpr_count = KernelInfo.NumVGPR;
671   header.workitem_private_segment_byte_size = KernelInfo.ScratchSize;
672   header.workgroup_group_segment_byte_size = KernelInfo.LDSSize;
673   header.reserved_vgpr_first = KernelInfo.ReservedVGPRFirst;
674   header.reserved_vgpr_count = KernelInfo.ReservedVGPRCount;
675 
676   AMDGPUTargetStreamer *TS =
677       static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
678 
679   OutStreamer->SwitchSection(getObjFileLowering().getTextSection());
680   TS->EmitAMDKernelCodeT(header);
681 }
682 
683 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
684                                        unsigned AsmVariant,
685                                        const char *ExtraCode, raw_ostream &O) {
686   if (ExtraCode && ExtraCode[0]) {
687     if (ExtraCode[1] != 0)
688       return true; // Unknown modifier.
689 
690     switch (ExtraCode[0]) {
691     default:
692       // See if this is a generic print operand
693       return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
694     case 'r':
695       break;
696     }
697   }
698 
699   AMDGPUInstPrinter::printRegOperand(MI->getOperand(OpNo).getReg(), O,
700                    *TM.getSubtargetImpl(*MF->getFunction())->getRegisterInfo());
701   return false;
702 }
703