1 //===----------------------------------------------------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "AMDGPU.h"
11 #include "AMDGPUArgumentUsageInfo.h"
12 #include "SIRegisterInfo.h"
13 #include "llvm/Support/raw_ostream.h"
14 
15 using namespace llvm;
16 
17 #define DEBUG_TYPE "amdgpu-argument-reg-usage-info"
18 
19 INITIALIZE_PASS(AMDGPUArgumentUsageInfo, DEBUG_TYPE,
20                 "Argument Register Usage Information Storage", false, true)
21 
22 void ArgDescriptor::print(raw_ostream &OS,
23                           const TargetRegisterInfo *TRI) const {
24   if (!isSet()) {
25     OS << "<not set>\n";
26     return;
27   }
28 
29   if (isRegister())
30     OS << "Reg " << printReg(getRegister(), TRI) << '\n';
31   else
32     OS << "Stack offset " << getStackOffset() << '\n';
33 }
34 
35 char AMDGPUArgumentUsageInfo::ID = 0;
36 
37 const AMDGPUFunctionArgInfo AMDGPUArgumentUsageInfo::ExternFunctionInfo{};
38 
39 bool AMDGPUArgumentUsageInfo::doInitialization(Module &M) {
40   return false;
41 }
42 
43 bool AMDGPUArgumentUsageInfo::doFinalization(Module &M) {
44   ArgInfoMap.clear();
45   return false;
46 }
47 
48 void AMDGPUArgumentUsageInfo::print(raw_ostream &OS, const Module *M) const {
49   for (const auto &FI : ArgInfoMap) {
50     OS << "Arguments for " << FI.first->getName() << '\n'
51        << "  PrivateSegmentBuffer: " << FI.second.PrivateSegmentBuffer
52        << "  DispatchPtr: " << FI.second.DispatchPtr
53        << "  QueuePtr: " << FI.second.QueuePtr
54        << "  KernargSegmentPtr: " << FI.second.KernargSegmentPtr
55        << "  DispatchID: " << FI.second.DispatchID
56        << "  FlatScratchInit: " << FI.second.FlatScratchInit
57        << "  PrivateSegmentSize: " << FI.second.PrivateSegmentSize
58        << "  WorkGroupIDX: " << FI.second.WorkGroupIDX
59        << "  WorkGroupIDY: " << FI.second.WorkGroupIDY
60        << "  WorkGroupIDZ: " << FI.second.WorkGroupIDZ
61        << "  WorkGroupInfo: " << FI.second.WorkGroupInfo
62        << "  PrivateSegmentWaveByteOffset: "
63           << FI.second.PrivateSegmentWaveByteOffset
64        << "  ImplicitBufferPtr: " << FI.second.ImplicitBufferPtr
65        << "  ImplicitArgPtr: " << FI.second.ImplicitArgPtr
66        << "  WorkItemIDX " << FI.second.WorkItemIDX
67        << "  WorkItemIDY " << FI.second.WorkItemIDY
68        << "  WorkItemIDZ " << FI.second.WorkItemIDZ
69        << '\n';
70   }
71 }
72 
73 std::pair<const ArgDescriptor *, const TargetRegisterClass *>
74 AMDGPUFunctionArgInfo::getPreloadedValue(
75   AMDGPUFunctionArgInfo::PreloadedValue Value) const {
76   switch (Value) {
77   case AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_BUFFER: {
78     return std::make_pair(
79       PrivateSegmentBuffer ? &PrivateSegmentBuffer : nullptr,
80       &AMDGPU::SGPR_128RegClass);
81   }
82   case AMDGPUFunctionArgInfo::IMPLICIT_BUFFER_PTR:
83     return std::make_pair(ImplicitBufferPtr ? &ImplicitBufferPtr : nullptr,
84                           &AMDGPU::SGPR_64RegClass);
85   case AMDGPUFunctionArgInfo::WORKGROUP_ID_X:
86     return std::make_pair(WorkGroupIDX ? &WorkGroupIDX : nullptr,
87                           &AMDGPU::SGPR_32RegClass);
88 
89   case AMDGPUFunctionArgInfo::WORKGROUP_ID_Y:
90     return std::make_pair(WorkGroupIDY ? &WorkGroupIDY : nullptr,
91                           &AMDGPU::SGPR_32RegClass);
92   case AMDGPUFunctionArgInfo::WORKGROUP_ID_Z:
93     return std::make_pair(WorkGroupIDZ ? &WorkGroupIDZ : nullptr,
94                           &AMDGPU::SGPR_32RegClass);
95   case AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET:
96     return std::make_pair(
97       PrivateSegmentWaveByteOffset ? &PrivateSegmentWaveByteOffset : nullptr,
98       &AMDGPU::SGPR_32RegClass);
99   case AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR:
100     return std::make_pair(KernargSegmentPtr ? &KernargSegmentPtr : nullptr,
101                           &AMDGPU::SGPR_64RegClass);
102   case AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR:
103     return std::make_pair(ImplicitArgPtr ? &ImplicitArgPtr : nullptr,
104                           &AMDGPU::SGPR_64RegClass);
105   case AMDGPUFunctionArgInfo::DISPATCH_ID:
106     return std::make_pair(DispatchID ? &DispatchID : nullptr,
107                           &AMDGPU::SGPR_64RegClass);
108   case AMDGPUFunctionArgInfo::FLAT_SCRATCH_INIT:
109     return std::make_pair(FlatScratchInit ? &FlatScratchInit : nullptr,
110                           &AMDGPU::SGPR_64RegClass);
111   case AMDGPUFunctionArgInfo::DISPATCH_PTR:
112     return std::make_pair(DispatchPtr ? &DispatchPtr : nullptr,
113                           &AMDGPU::SGPR_64RegClass);
114   case AMDGPUFunctionArgInfo::QUEUE_PTR:
115     return std::make_pair(QueuePtr ? &QueuePtr : nullptr,
116                           &AMDGPU::SGPR_64RegClass);
117   case AMDGPUFunctionArgInfo::WORKITEM_ID_X:
118     return std::make_pair(WorkItemIDX ? &WorkItemIDX : nullptr,
119                           &AMDGPU::VGPR_32RegClass);
120   case AMDGPUFunctionArgInfo::WORKITEM_ID_Y:
121     return std::make_pair(WorkItemIDY ? &WorkItemIDY : nullptr,
122                           &AMDGPU::VGPR_32RegClass);
123   case AMDGPUFunctionArgInfo::WORKITEM_ID_Z:
124     return std::make_pair(WorkItemIDZ ? &WorkItemIDZ : nullptr,
125                           &AMDGPU::VGPR_32RegClass);
126   }
127   llvm_unreachable("unexpected preloaded value type");
128 }
129