1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===------------------------------------------------------------===//
8
9include "llvm/TableGen/SearchableTable.td"
10include "llvm/Target/Target.td"
11include "AMDGPUFeatures.td"
12
13def p0 : PtrValueType<i64, 0>;
14def p1 : PtrValueType<i64, 1>;
15def p2 : PtrValueType<i32, 2>;
16def p3 : PtrValueType<i32, 3>;
17def p4 : PtrValueType<i64, 4>;
18def p5 : PtrValueType<i32, 5>;
19def p6 : PtrValueType<i32, 6>;
20
21class BoolToList<bit Value> {
22  list<int> ret = !if(Value, [1]<int>, []<int>);
23}
24
25//===------------------------------------------------------------===//
26// Subtarget Features (device properties)
27//===------------------------------------------------------------===//
28
29def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
30  "FastFMAF32",
31  "true",
32  "Assuming f32 fma is at least as fast as mul + add"
33>;
34
35def FeatureFastDenormalF32 : SubtargetFeature<"fast-denormal-f32",
36  "FastDenormalF32",
37  "true",
38  "Enabling denormals does not cause f32 instructions to run at f64 rates"
39>;
40
41def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
42  "MIMG_R128",
43  "true",
44  "Support 128-bit texture resources"
45>;
46
47def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
48  "HalfRate64Ops",
49  "true",
50  "Most fp64 instructions are half rate instead of quarter"
51>;
52
53def FullRate64Ops : SubtargetFeature<"full-rate-64-ops",
54  "FullRate64Ops",
55  "true",
56  "Most fp64 instructions are full rate"
57>;
58
59def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
60  "FlatAddressSpace",
61  "true",
62  "Support flat address space"
63>;
64
65def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
66  "FlatInstOffsets",
67  "true",
68  "Flat instructions have immediate offset addressing mode"
69>;
70
71def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
72  "FlatGlobalInsts",
73  "true",
74  "Have global_* flat memory instructions"
75>;
76
77def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
78  "FlatScratchInsts",
79  "true",
80  "Have scratch_* flat memory instructions"
81>;
82
83def FeatureScalarFlatScratchInsts : SubtargetFeature<"scalar-flat-scratch-insts",
84  "ScalarFlatScratchInsts",
85  "true",
86  "Have s_scratch_* flat memory instructions"
87>;
88
89def FeatureEnableFlatScratch : SubtargetFeature<"enable-flat-scratch",
90  "EnableFlatScratch",
91  "true",
92  "Use scratch_* flat memory instructions to access scratch"
93>;
94
95def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
96  "AddNoCarryInsts",
97  "true",
98  "Have VALU add/sub instructions without carry out"
99>;
100
101def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
102  "UnalignedBufferAccess",
103  "true",
104  "Hardware supports unaligned global loads and stores"
105>;
106
107def FeatureTrapHandler: SubtargetFeature<"trap-handler",
108  "TrapHandler",
109  "true",
110  "Trap handler support"
111>;
112
113def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
114  "UnalignedScratchAccess",
115  "true",
116  "Support unaligned scratch loads and stores"
117>;
118
119def FeatureUnalignedDSAccess : SubtargetFeature<"unaligned-ds-access",
120  "UnalignedDSAccess",
121  "true",
122  "Hardware supports unaligned local and region loads and stores"
123>;
124
125def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
126  "HasApertureRegs",
127  "true",
128  "Has Memory Aperture Base and Size Registers"
129>;
130
131def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
132  "HasMadMixInsts",
133  "true",
134  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
135>;
136
137def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
138  "HasFmaMixInsts",
139  "true",
140  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
141>;
142
143def FeatureSupportsXNACK : SubtargetFeature<"xnack-support",
144  "SupportsXNACK",
145  "true",
146  "Hardware supports XNACK"
147>;
148
149// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
150// XNACK. The current default kernel driver setting is:
151// - graphics ring: XNACK disabled
152// - compute ring: XNACK enabled
153//
154// If XNACK is enabled, the VMEM latency can be worse.
155// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
156def FeatureXNACK : SubtargetFeature<"xnack",
157  "EnableXNACK",
158  "true",
159  "Enable XNACK support"
160>;
161
162def FeatureTgSplit : SubtargetFeature<"tgsplit",
163  "EnableTgSplit",
164  "true",
165  "Enable threadgroup split execution"
166>;
167
168def FeatureCuMode : SubtargetFeature<"cumode",
169  "EnableCuMode",
170  "true",
171  "Enable CU wavefront execution mode"
172>;
173
174def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
175  "SGPRInitBug",
176  "true",
177  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
178>;
179
180def FeatureLdsMisalignedBug : SubtargetFeature<"lds-misaligned-bug",
181  "LDSMisalignedBug",
182  "true",
183  "Some GFX10 bug with multi-dword LDS and flat access that is not naturally aligned in WGP mode"
184>;
185
186def FeatureMFMAInlineLiteralBug : SubtargetFeature<"mfma-inline-literal-bug",
187  "HasMFMAInlineLiteralBug",
188  "true",
189  "MFMA cannot use inline literal as SrcC"
190>;
191
192def FeatureVcmpxPermlaneHazard : SubtargetFeature<"vcmpx-permlane-hazard",
193  "HasVcmpxPermlaneHazard",
194  "true",
195  "TODO: describe me"
196>;
197
198def FeatureVMEMtoScalarWriteHazard : SubtargetFeature<"vmem-to-scalar-write-hazard",
199  "HasVMEMtoScalarWriteHazard",
200  "true",
201  "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution."
202>;
203
204def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard",
205  "HasSMEMtoVectorWriteHazard",
206  "true",
207  "s_load_dword followed by v_cmp page faults"
208>;
209
210def FeatureInstFwdPrefetchBug : SubtargetFeature<"inst-fwd-prefetch-bug",
211  "HasInstFwdPrefetchBug",
212  "true",
213  "S_INST_PREFETCH instruction causes shader to hang"
214>;
215
216def FeatureVcmpxExecWARHazard : SubtargetFeature<"vcmpx-exec-war-hazard",
217  "HasVcmpxExecWARHazard",
218  "true",
219  "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)"
220>;
221
222def FeatureLdsBranchVmemWARHazard : SubtargetFeature<"lds-branch-vmem-war-hazard",
223  "HasLdsBranchVmemWARHazard",
224  "true",
225  "Switching between LDS and VMEM-tex not waiting VM_VSRC=0"
226>;
227
228def FeatureNSAtoVMEMBug : SubtargetFeature<"nsa-to-vmem-bug",
229  "HasNSAtoVMEMBug",
230  "true",
231  "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero"
232>;
233
234def FeatureNSAClauseBug : SubtargetFeature<"nsa-clause-bug",
235  "HasNSAClauseBug",
236  "true",
237  "MIMG-NSA in a hard clause has unpredictable results on GFX10.1"
238>;
239
240def FeatureFlatSegmentOffsetBug : SubtargetFeature<"flat-segment-offset-bug",
241  "HasFlatSegmentOffsetBug",
242  "true",
243  "GFX10 bug where inst_offset is ignored when flat instructions access global memory"
244>;
245
246def FeatureNegativeScratchOffsetBug : SubtargetFeature<"negative-scratch-offset-bug",
247  "NegativeScratchOffsetBug",
248  "true",
249  "Negative immediate offsets in scratch instructions with an SGPR offset page fault on GFX9"
250>;
251
252def FeatureNegativeUnalignedScratchOffsetBug : SubtargetFeature<"negative-unaligned-scratch-offset-bug",
253  "NegativeUnalignedScratchOffsetBug",
254  "true",
255  "Scratch instructions with a VGPR offset and a negative immediate offset that is not a multiple of 4 read wrong memory on GFX10"
256>;
257
258def FeatureOffset3fBug : SubtargetFeature<"offset-3f-bug",
259  "HasOffset3fBug",
260  "true",
261  "Branch offset of 3f hardware bug"
262>;
263
264def FeatureImageStoreD16Bug : SubtargetFeature<"image-store-d16-bug",
265  "HasImageStoreD16Bug",
266  "true",
267  "Image Store D16 hardware bug"
268>;
269
270def FeatureImageGather4D16Bug : SubtargetFeature<"image-gather4-d16-bug",
271  "HasImageGather4D16Bug",
272  "true",
273  "Image Gather4 D16 hardware bug"
274>;
275
276class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
277  "ldsbankcount"#Value,
278  "LDSBankCount",
279  !cast<string>(Value),
280  "The number of LDS banks per compute unit."
281>;
282
283def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
284def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
285
286def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
287  "GCN3Encoding",
288  "true",
289  "Encoding format for VI"
290>;
291
292def FeatureCIInsts : SubtargetFeature<"ci-insts",
293  "CIInsts",
294  "true",
295  "Additional instructions for CI+"
296>;
297
298def FeatureGFX8Insts : SubtargetFeature<"gfx8-insts",
299  "GFX8Insts",
300  "true",
301  "Additional instructions for GFX8+"
302>;
303
304def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
305  "GFX9Insts",
306  "true",
307  "Additional instructions for GFX9+"
308>;
309
310def FeatureGFX90AInsts : SubtargetFeature<"gfx90a-insts",
311  "GFX90AInsts",
312  "true",
313  "Additional instructions for GFX90A+"
314>;
315
316def FeatureGFX940Insts : SubtargetFeature<"gfx940-insts",
317  "GFX940Insts",
318  "true",
319  "Additional instructions for GFX940+"
320>;
321
322def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts",
323  "GFX10Insts",
324  "true",
325  "Additional instructions for GFX10+"
326>;
327
328def FeatureGFX10_3Insts : SubtargetFeature<"gfx10-3-insts",
329  "GFX10_3Insts",
330  "true",
331  "Additional instructions for GFX10.3"
332>;
333
334def FeatureGFX7GFX8GFX9Insts : SubtargetFeature<"gfx7-gfx8-gfx9-insts",
335  "GFX7GFX8GFX9Insts",
336  "true",
337  "Instructions shared in GFX7, GFX8, GFX9"
338>;
339
340def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
341  "HasSMemRealTime",
342  "true",
343  "Has s_memrealtime instruction"
344>;
345
346def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
347  "HasInv2PiInlineImm",
348  "true",
349  "Has 1 / (2 * pi) as inline immediate"
350>;
351
352def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
353  "Has16BitInsts",
354  "true",
355  "Has i16/f16 instructions"
356>;
357
358def FeatureVOP3P : SubtargetFeature<"vop3p",
359  "HasVOP3PInsts",
360  "true",
361  "Has VOP3P packed instructions"
362>;
363
364def FeatureMovrel : SubtargetFeature<"movrel",
365  "HasMovrel",
366  "true",
367  "Has v_movrel*_b32 instructions"
368>;
369
370def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
371  "HasVGPRIndexMode",
372  "true",
373  "Has VGPR mode register indexing"
374>;
375
376def FeatureScalarStores : SubtargetFeature<"scalar-stores",
377  "HasScalarStores",
378  "true",
379  "Has store scalar memory instructions"
380>;
381
382def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
383  "HasScalarAtomics",
384  "true",
385  "Has atomic scalar memory instructions"
386>;
387
388def FeatureSDWA : SubtargetFeature<"sdwa",
389  "HasSDWA",
390  "true",
391  "Support SDWA (Sub-DWORD Addressing) extension"
392>;
393
394def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
395  "HasSDWAOmod",
396  "true",
397  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
398>;
399
400def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
401  "HasSDWAScalar",
402  "true",
403  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
404>;
405
406def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
407  "HasSDWASdst",
408  "true",
409  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
410>;
411
412def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
413  "HasSDWAMac",
414  "true",
415  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
416>;
417
418def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
419  "HasSDWAOutModsVOPC",
420  "true",
421  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
422>;
423
424def FeatureDPP : SubtargetFeature<"dpp",
425  "HasDPP",
426  "true",
427  "Support DPP (Data Parallel Primitives) extension"
428>;
429
430// DPP8 allows arbitrary cross-lane swizzling within groups of 8 lanes.
431def FeatureDPP8 : SubtargetFeature<"dpp8",
432  "HasDPP8",
433  "true",
434  "Support DPP8 (Data Parallel Primitives) extension"
435>;
436
437def Feature64BitDPP : SubtargetFeature<"dpp-64bit",
438  "Has64BitDPP",
439  "true",
440  "Support DPP (Data Parallel Primitives) extension"
441>;
442
443def FeaturePackedFP32Ops : SubtargetFeature<"packed-fp32-ops",
444  "HasPackedFP32Ops",
445  "true",
446  "Support packed fp32 instructions"
447>;
448
449def FeatureR128A16 : SubtargetFeature<"r128-a16",
450  "HasR128A16",
451  "true",
452  "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128"
453>;
454
455def FeatureGFX10A16 : SubtargetFeature<"a16",
456  "HasGFX10A16",
457  "true",
458  "Support gfx10-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands"
459>;
460
461def FeatureG16 : SubtargetFeature<"g16",
462  "HasG16",
463  "true",
464  "Support G16 for 16-bit gradient image operands"
465>;
466
467def FeatureNSAEncoding : SubtargetFeature<"nsa-encoding",
468  "HasNSAEncoding",
469  "true",
470  "Support NSA encoding for image instructions"
471>;
472
473def FeatureImageInsts : SubtargetFeature<"image-insts",
474  "HasImageInsts",
475  "true",
476  "Support image instructions"
477>;
478
479def FeatureExtendedImageInsts : SubtargetFeature<"extended-image-insts",
480  "HasExtendedImageInsts",
481  "true",
482  "Support mips != 0, lod != 0, gather4, and get_lod"
483>;
484
485def FeatureGFX10_AEncoding : SubtargetFeature<"gfx10_a-encoding",
486  "GFX10_AEncoding",
487  "true",
488  "Has BVH ray tracing instructions"
489>;
490
491def FeatureGFX10_BEncoding : SubtargetFeature<"gfx10_b-encoding",
492  "GFX10_BEncoding",
493  "true",
494  "Encoding format GFX10_B"
495>;
496
497def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
498  "HasIntClamp",
499  "true",
500  "Support clamp for integer destination"
501>;
502
503def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
504  "HasUnpackedD16VMem",
505  "true",
506  "Has unpacked d16 vmem instructions"
507>;
508
509def FeatureDLInsts : SubtargetFeature<"dl-insts",
510  "HasDLInsts",
511  "true",
512  "Has v_fmac_f32 and v_xnor_b32 instructions"
513>;
514
515def FeatureDot1Insts : SubtargetFeature<"dot1-insts",
516  "HasDot1Insts",
517  "true",
518  "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions"
519>;
520
521def FeatureDot2Insts : SubtargetFeature<"dot2-insts",
522  "HasDot2Insts",
523  "true",
524  "Has v_dot2_i32_i16, v_dot2_u32_u16 instructions"
525>;
526
527def FeatureDot3Insts : SubtargetFeature<"dot3-insts",
528  "HasDot3Insts",
529  "true",
530  "Has v_dot8c_i32_i4 instruction"
531>;
532
533def FeatureDot4Insts : SubtargetFeature<"dot4-insts",
534  "HasDot4Insts",
535  "true",
536  "Has v_dot2c_i32_i16 instruction"
537>;
538
539def FeatureDot5Insts : SubtargetFeature<"dot5-insts",
540  "HasDot5Insts",
541  "true",
542  "Has v_dot2c_f32_f16 instruction"
543>;
544
545def FeatureDot6Insts : SubtargetFeature<"dot6-insts",
546  "HasDot6Insts",
547  "true",
548  "Has v_dot4c_i32_i8 instruction"
549>;
550
551def FeatureDot7Insts : SubtargetFeature<"dot7-insts",
552  "HasDot7Insts",
553  "true",
554  "Has v_dot2_f32_f16, v_dot4_u32_u8, v_dot8_u32_u4 instructions"
555>;
556
557def FeatureMAIInsts : SubtargetFeature<"mai-insts",
558  "HasMAIInsts",
559  "true",
560  "Has mAI instructions"
561>;
562
563def FeaturePkFmacF16Inst : SubtargetFeature<"pk-fmac-f16-inst",
564  "HasPkFmacF16Inst",
565  "true",
566  "Has v_pk_fmac_f16 instruction"
567>;
568
569def FeatureAtomicFaddInsts : SubtargetFeature<"atomic-fadd-insts",
570  "HasAtomicFaddInsts",
571  "true",
572  "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, "
573  "global_atomic_pk_add_f16 instructions",
574  [FeatureFlatGlobalInsts]
575>;
576
577def FeatureSupportsSRAMECC : SubtargetFeature<"sramecc-support",
578  "SupportsSRAMECC",
579  "true",
580  "Hardware supports SRAMECC"
581>;
582
583def FeatureSRAMECC : SubtargetFeature<"sramecc",
584  "EnableSRAMECC",
585  "true",
586  "Enable SRAMECC"
587>;
588
589def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx",
590  "HasNoSdstCMPX",
591  "true",
592  "V_CMPX does not write VCC/SGPR in addition to EXEC"
593>;
594
595def FeatureVscnt : SubtargetFeature<"vscnt",
596  "HasVscnt",
597  "true",
598  "Has separate store vscnt counter"
599>;
600
601def FeatureGetWaveIdInst : SubtargetFeature<"get-wave-id-inst",
602  "HasGetWaveIdInst",
603  "true",
604  "Has s_get_waveid_in_workgroup instruction"
605>;
606
607def FeatureSMemTimeInst : SubtargetFeature<"s-memtime-inst",
608  "HasSMemTimeInst",
609  "true",
610  "Has s_memtime instruction"
611>;
612
613def FeatureShaderCyclesRegister : SubtargetFeature<"shader-cycles-register",
614  "HasShaderCyclesRegister",
615  "true",
616  "Has SHADER_CYCLES hardware register"
617>;
618
619def FeatureMadMacF32Insts : SubtargetFeature<"mad-mac-f32-insts",
620  "HasMadMacF32Insts",
621  "true",
622  "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions"
623>;
624
625def FeatureDsSrc2Insts : SubtargetFeature<"ds-src2-insts",
626  "HasDsSrc2Insts",
627  "true",
628  "Has ds_*_src2 instructions"
629>;
630
631def FeatureVOP3Literal : SubtargetFeature<"vop3-literal",
632  "HasVOP3Literal",
633  "true",
634  "Can use one literal in VOP3"
635>;
636
637def FeatureNoDataDepHazard : SubtargetFeature<"no-data-dep-hazard",
638  "HasNoDataDepHazard",
639  "true",
640  "Does not need SW waitstates"
641>;
642
643class SubtargetFeatureNSAMaxSize <int Value> : SubtargetFeature <
644  "nsa-max-size-"#Value,
645  "NSAMaxSize",
646  !cast<string>(Value),
647  "The maximum non-sequential address size in VGPRs."
648>;
649
650def FeatureNSAMaxSize5 : SubtargetFeatureNSAMaxSize<5>;
651def FeatureNSAMaxSize13 : SubtargetFeatureNSAMaxSize<13>;
652
653//===------------------------------------------------------------===//
654// Subtarget Features (options and debugging)
655//===------------------------------------------------------------===//
656
657class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
658  "max-private-element-size-"#size,
659  "MaxPrivateElementSize",
660  !cast<string>(size),
661  "Maximum private access size may be "#size
662>;
663
664def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
665def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
666def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
667
668def FeatureDumpCode : SubtargetFeature <"DumpCode",
669  "DumpCode",
670  "true",
671  "Dump MachineInstrs in the CodeEmitter"
672>;
673
674def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
675  "DumpCode",
676  "true",
677  "Dump MachineInstrs in the CodeEmitter"
678>;
679
680// XXX - This should probably be removed once enabled by default
681def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
682  "EnableLoadStoreOpt",
683  "true",
684  "Enable SI load/store optimizer pass"
685>;
686
687// Performance debugging feature. Allow using DS instruction immediate
688// offsets even if the base pointer can't be proven to be base. On SI,
689// base pointer values that won't give the same result as a 16-bit add
690// are not safe to fold, but this will override the conservative test
691// for the base pointer.
692def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
693  "unsafe-ds-offset-folding",
694  "EnableUnsafeDSOffsetFolding",
695  "true",
696  "Force using DS instruction immediate offsets on SI"
697>;
698
699def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
700  "EnableSIScheduler",
701  "true",
702  "Enable SI Machine Scheduler"
703>;
704
705def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
706  "EnableDS128",
707  "true",
708  "Use ds_{read|write}_b128"
709>;
710
711// Sparse texture support requires that all result registers are zeroed when
712// PRTStrictNull is set to true. This feature is turned on for all architectures
713// but is enabled as a feature in case there are situations where PRTStrictNull
714// is disabled by the driver.
715def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
716  "EnablePRTStrictNull",
717  "true",
718  "Enable zeroing of result registers for sparse texture fetches"
719>;
720
721// Unless +-flat-for-global is specified, turn on FlatForGlobal for
722// all OS-es on VI and newer hardware to avoid assertion failures due
723// to missing ADDR64 variants of MUBUF instructions.
724// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
725// instructions.
726
727def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
728  "FlatForGlobal",
729  "true",
730  "Force to generate flat instruction for global"
731>;
732
733def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
734  "auto-waitcnt-before-barrier",
735  "AutoWaitcntBeforeBarrier",
736  "true",
737  "Hardware automatically inserts waitcnt before barrier"
738>;
739
740def FeatureBackOffBarrier : SubtargetFeature <"back-off-barrier",
741  "BackOffBarrier",
742  "true",
743  "Hardware supports backing off s_barrier if an exception occurs"
744>;
745
746def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
747  "HasTrigReducedRange",
748  "true",
749  "Requires use of fract on arguments to trig instructions"
750>;
751
752// Alignment enforcement is controlled by a configuration register:
753// SH_MEM_CONFIG.alignment_mode
754def FeatureUnalignedAccessMode : SubtargetFeature<"unaligned-access-mode",
755  "UnalignedAccessMode",
756  "true",
757  "Enable unaligned global, local and region loads and stores if the hardware"
758  " supports it"
759>;
760
761def FeaturePackedTID : SubtargetFeature<"packed-tid",
762  "HasPackedTID",
763  "true",
764  "Workitem IDs are packed into v0 at kernel launch"
765>;
766
767def FeatureArchitectedFlatScratch : SubtargetFeature<"architected-flat-scratch",
768  "HasArchitectedFlatScratch",
769  "true",
770  "Flat Scratch register is a readonly SPI initialized architected register"
771>;
772
773// Dummy feature used to disable assembler instructions.
774def FeatureDisable : SubtargetFeature<"",
775  "FeatureDisable","true",
776  "Dummy feature to disable assembler instructions"
777>;
778
779class GCNSubtargetFeatureGeneration <string Value,
780                                     string FeatureName,
781                                     list<SubtargetFeature> Implies> :
782        SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
783
784def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
785    "southern-islands",
786  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
787  FeatureWavefrontSize64, FeatureSMemTimeInst, FeatureMadMacF32Insts,
788  FeatureDsSrc2Insts, FeatureLDSBankCount32, FeatureMovrel,
789  FeatureTrigReducedRange, FeatureExtendedImageInsts, FeatureImageInsts
790  ]
791>;
792
793def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
794    "sea-islands",
795  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
796  FeatureWavefrontSize64, FeatureFlatAddressSpace,
797  FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange,
798  FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
799  FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureUnalignedBufferAccess,
800  FeatureImageInsts
801  ]
802>;
803
804def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
805  "volcanic-islands",
806  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
807   FeatureWavefrontSize64, FeatureFlatAddressSpace,
808   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
809   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
810   FeatureScalarStores, FeatureInv2PiInlineImm,
811   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
812   FeatureIntClamp, FeatureTrigReducedRange, FeatureGFX8Insts,
813   FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts,
814   FeatureDsSrc2Insts, FeatureExtendedImageInsts, FeatureFastDenormalF32,
815   FeatureUnalignedBufferAccess, FeatureImageInsts
816  ]
817>;
818
819def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
820  "gfx9",
821  [FeatureFP64, FeatureLocalMemorySize65536,
822   FeatureWavefrontSize64, FeatureFlatAddressSpace,
823   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
824   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
825   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
826   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
827   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
828   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
829   FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts,
830   FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16,
831   FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureSupportsXNACK,
832   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess,
833   FeatureNegativeScratchOffsetBug
834  ]
835>;
836
837def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
838  "gfx10",
839  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
840   FeatureFlatAddressSpace,
841   FeatureCIInsts, Feature16BitInsts,
842   FeatureSMemRealTime, FeatureInv2PiInlineImm,
843   FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P,
844   FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
845   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
846   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
847   FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
848   FeatureNoSdstCMPX, FeatureVscnt,
849   FeatureVOP3Literal, FeatureDPP8, FeatureExtendedImageInsts,
850   FeatureNoDataDepHazard, FeaturePkFmacF16Inst,
851   FeatureGFX10A16, FeatureSMemTimeInst, FeatureFastDenormalF32, FeatureG16,
852   FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess, FeatureImageInsts
853  ]
854>;
855
856class FeatureSet<list<SubtargetFeature> Features_> {
857  list<SubtargetFeature> Features = Features_;
858}
859
860def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
861   FeatureFastFMAF32,
862   HalfRate64Ops,
863   FeatureLDSBankCount32]>;
864
865def FeatureISAVersion6_0_1 : FeatureSet<
866  [FeatureSouthernIslands,
867   FeatureLDSBankCount32]>;
868
869def FeatureISAVersion6_0_2 : FeatureSet<
870  [FeatureSouthernIslands,
871   FeatureLDSBankCount32]>;
872
873def FeatureISAVersion7_0_0 : FeatureSet<
874  [FeatureSeaIslands,
875   FeatureLDSBankCount32]>;
876
877def FeatureISAVersion7_0_1 : FeatureSet<
878  [FeatureSeaIslands,
879   HalfRate64Ops,
880   FeatureLDSBankCount32,
881   FeatureFastFMAF32]>;
882
883def FeatureISAVersion7_0_2 : FeatureSet<
884  [FeatureSeaIslands,
885   FeatureLDSBankCount16,
886   FeatureFastFMAF32]>;
887
888def FeatureISAVersion7_0_3 : FeatureSet<
889  [FeatureSeaIslands,
890   FeatureLDSBankCount16]>;
891
892def FeatureISAVersion7_0_4 : FeatureSet<
893  [FeatureSeaIslands,
894   FeatureLDSBankCount32]>;
895
896def FeatureISAVersion7_0_5 : FeatureSet<
897  [FeatureSeaIslands,
898   FeatureLDSBankCount16]>;
899
900def FeatureISAVersion8_0_1 : FeatureSet<
901  [FeatureVolcanicIslands,
902   FeatureFastFMAF32,
903   HalfRate64Ops,
904   FeatureLDSBankCount32,
905   FeatureSupportsXNACK,
906   FeatureUnpackedD16VMem]>;
907
908def FeatureISAVersion8_0_2 : FeatureSet<
909  [FeatureVolcanicIslands,
910   FeatureLDSBankCount32,
911   FeatureSGPRInitBug,
912   FeatureUnpackedD16VMem]>;
913
914def FeatureISAVersion8_0_3 : FeatureSet<
915  [FeatureVolcanicIslands,
916   FeatureLDSBankCount32,
917   FeatureUnpackedD16VMem]>;
918
919def FeatureISAVersion8_0_5 : FeatureSet<
920  [FeatureVolcanicIslands,
921   FeatureLDSBankCount32,
922   FeatureSGPRInitBug,
923   FeatureUnpackedD16VMem]>;
924
925def FeatureISAVersion8_1_0 : FeatureSet<
926  [FeatureVolcanicIslands,
927   FeatureLDSBankCount16,
928   FeatureSupportsXNACK,
929   FeatureImageStoreD16Bug,
930   FeatureImageGather4D16Bug]>;
931
932def FeatureISAVersion9_0_0 : FeatureSet<
933  [FeatureGFX9,
934   FeatureMadMixInsts,
935   FeatureLDSBankCount32,
936   FeatureDsSrc2Insts,
937   FeatureExtendedImageInsts,
938   FeatureImageInsts,
939   FeatureMadMacF32Insts,
940   FeatureImageGather4D16Bug]>;
941
942def FeatureISAVersion9_0_2 : FeatureSet<
943  [FeatureGFX9,
944   FeatureMadMixInsts,
945   FeatureLDSBankCount32,
946   FeatureDsSrc2Insts,
947   FeatureExtendedImageInsts,
948   FeatureImageInsts,
949   FeatureMadMacF32Insts,
950   FeatureImageGather4D16Bug]>;
951
952def FeatureISAVersion9_0_4 : FeatureSet<
953  [FeatureGFX9,
954   FeatureLDSBankCount32,
955   FeatureDsSrc2Insts,
956   FeatureExtendedImageInsts,
957   FeatureImageInsts,
958   FeatureMadMacF32Insts,
959   FeatureFmaMixInsts,
960   FeatureImageGather4D16Bug]>;
961
962def FeatureISAVersion9_0_6 : FeatureSet<
963  [FeatureGFX9,
964   HalfRate64Ops,
965   FeatureFmaMixInsts,
966   FeatureLDSBankCount32,
967   FeatureDsSrc2Insts,
968   FeatureExtendedImageInsts,
969   FeatureImageInsts,
970   FeatureMadMacF32Insts,
971   FeatureDLInsts,
972   FeatureDot1Insts,
973   FeatureDot2Insts,
974   FeatureDot7Insts,
975   FeatureSupportsSRAMECC,
976   FeatureImageGather4D16Bug]>;
977
978def FeatureISAVersion9_0_8 : FeatureSet<
979  [FeatureGFX9,
980   HalfRate64Ops,
981   FeatureFmaMixInsts,
982   FeatureLDSBankCount32,
983   FeatureDsSrc2Insts,
984   FeatureExtendedImageInsts,
985   FeatureImageInsts,
986   FeatureMadMacF32Insts,
987   FeatureDLInsts,
988   FeatureDot1Insts,
989   FeatureDot2Insts,
990   FeatureDot3Insts,
991   FeatureDot4Insts,
992   FeatureDot5Insts,
993   FeatureDot6Insts,
994   FeatureDot7Insts,
995   FeatureMAIInsts,
996   FeaturePkFmacF16Inst,
997   FeatureAtomicFaddInsts,
998   FeatureSupportsSRAMECC,
999   FeatureMFMAInlineLiteralBug,
1000   FeatureImageGather4D16Bug]>;
1001
1002def FeatureISAVersion9_0_9 : FeatureSet<
1003  [FeatureGFX9,
1004   FeatureMadMixInsts,
1005   FeatureLDSBankCount32,
1006   FeatureDsSrc2Insts,
1007   FeatureExtendedImageInsts,
1008   FeatureImageInsts,
1009   FeatureMadMacF32Insts,
1010   FeatureImageGather4D16Bug]>;
1011
1012def FeatureISAVersion9_0_A : FeatureSet<
1013  [FeatureGFX9,
1014   FeatureGFX90AInsts,
1015   FeatureFmaMixInsts,
1016   FeatureLDSBankCount32,
1017   FeatureDLInsts,
1018   FeatureDot1Insts,
1019   FeatureDot2Insts,
1020   FeatureDot3Insts,
1021   FeatureDot4Insts,
1022   FeatureDot5Insts,
1023   FeatureDot6Insts,
1024   FeatureDot7Insts,
1025   Feature64BitDPP,
1026   FeaturePackedFP32Ops,
1027   FeatureMAIInsts,
1028   FeaturePkFmacF16Inst,
1029   FeatureAtomicFaddInsts,
1030   FeatureImageInsts,
1031   FeatureMadMacF32Insts,
1032   FeatureSupportsSRAMECC,
1033   FeaturePackedTID,
1034   FullRate64Ops,
1035   FeatureBackOffBarrier]>;
1036
1037def FeatureISAVersion9_0_C : FeatureSet<
1038  [FeatureGFX9,
1039   FeatureMadMixInsts,
1040   FeatureLDSBankCount32,
1041   FeatureDsSrc2Insts,
1042   FeatureExtendedImageInsts,
1043   FeatureImageInsts,
1044   FeatureMadMacF32Insts,
1045   FeatureImageGather4D16Bug]>;
1046
1047def FeatureISAVersion9_4_0 : FeatureSet<
1048  [FeatureGFX9,
1049   FeatureGFX90AInsts,
1050   FeatureGFX940Insts,
1051   FeatureFmaMixInsts,
1052   FeatureLDSBankCount32,
1053   FeatureDLInsts,
1054   FeatureDot1Insts,
1055   FeatureDot2Insts,
1056   FeatureDot3Insts,
1057   FeatureDot4Insts,
1058   FeatureDot5Insts,
1059   FeatureDot6Insts,
1060   FeatureDot7Insts,
1061   Feature64BitDPP,
1062   FeaturePackedFP32Ops,
1063   FeatureMAIInsts,
1064   FeaturePkFmacF16Inst,
1065   FeatureAtomicFaddInsts,
1066   FeatureSupportsSRAMECC,
1067   FeaturePackedTID,
1068   FeatureArchitectedFlatScratch,
1069   FullRate64Ops,
1070   FeatureBackOffBarrier]>;
1071
1072// TODO: Organize more features into groups.
1073def FeatureGroup {
1074  // Bugs present on gfx10.1.
1075  list<SubtargetFeature> GFX10_1_Bugs = [
1076    FeatureVcmpxPermlaneHazard,
1077    FeatureVMEMtoScalarWriteHazard,
1078    FeatureSMEMtoVectorWriteHazard,
1079    FeatureInstFwdPrefetchBug,
1080    FeatureVcmpxExecWARHazard,
1081    FeatureLdsBranchVmemWARHazard,
1082    FeatureNSAtoVMEMBug,
1083    FeatureNSAClauseBug,
1084    FeatureOffset3fBug,
1085    FeatureFlatSegmentOffsetBug,
1086    FeatureNegativeUnalignedScratchOffsetBug
1087   ];
1088}
1089
1090def FeatureISAVersion10_1_0 : FeatureSet<
1091  !listconcat(FeatureGroup.GFX10_1_Bugs,
1092    [FeatureGFX10,
1093     FeatureLDSBankCount32,
1094     FeatureDLInsts,
1095     FeatureNSAEncoding,
1096     FeatureNSAMaxSize5,
1097     FeatureWavefrontSize32,
1098     FeatureScalarStores,
1099     FeatureScalarAtomics,
1100     FeatureScalarFlatScratchInsts,
1101     FeatureGetWaveIdInst,
1102     FeatureMadMacF32Insts,
1103     FeatureDsSrc2Insts,
1104     FeatureLdsMisalignedBug,
1105     FeatureSupportsXNACK,
1106     FeatureBackOffBarrier])>;
1107
1108def FeatureISAVersion10_1_1 : FeatureSet<
1109  !listconcat(FeatureGroup.GFX10_1_Bugs,
1110    [FeatureGFX10,
1111     FeatureLDSBankCount32,
1112     FeatureDLInsts,
1113     FeatureDot1Insts,
1114     FeatureDot2Insts,
1115     FeatureDot5Insts,
1116     FeatureDot6Insts,
1117     FeatureDot7Insts,
1118     FeatureNSAEncoding,
1119     FeatureNSAMaxSize5,
1120     FeatureWavefrontSize32,
1121     FeatureScalarStores,
1122     FeatureScalarAtomics,
1123     FeatureScalarFlatScratchInsts,
1124     FeatureGetWaveIdInst,
1125     FeatureMadMacF32Insts,
1126     FeatureDsSrc2Insts,
1127     FeatureLdsMisalignedBug,
1128     FeatureSupportsXNACK,
1129     FeatureBackOffBarrier])>;
1130
1131def FeatureISAVersion10_1_2 : FeatureSet<
1132  !listconcat(FeatureGroup.GFX10_1_Bugs,
1133    [FeatureGFX10,
1134     FeatureLDSBankCount32,
1135     FeatureDLInsts,
1136     FeatureDot1Insts,
1137     FeatureDot2Insts,
1138     FeatureDot5Insts,
1139     FeatureDot6Insts,
1140     FeatureDot7Insts,
1141     FeatureNSAEncoding,
1142     FeatureNSAMaxSize5,
1143     FeatureWavefrontSize32,
1144     FeatureScalarStores,
1145     FeatureScalarAtomics,
1146     FeatureScalarFlatScratchInsts,
1147     FeatureGetWaveIdInst,
1148     FeatureMadMacF32Insts,
1149     FeatureDsSrc2Insts,
1150     FeatureLdsMisalignedBug,
1151     FeatureSupportsXNACK,
1152     FeatureBackOffBarrier])>;
1153
1154def FeatureISAVersion10_1_3 : FeatureSet<
1155  !listconcat(FeatureGroup.GFX10_1_Bugs,
1156    [FeatureGFX10,
1157     FeatureGFX10_AEncoding,
1158     FeatureLDSBankCount32,
1159     FeatureDLInsts,
1160     FeatureNSAEncoding,
1161     FeatureNSAMaxSize5,
1162     FeatureWavefrontSize32,
1163     FeatureScalarStores,
1164     FeatureScalarAtomics,
1165     FeatureScalarFlatScratchInsts,
1166     FeatureGetWaveIdInst,
1167     FeatureMadMacF32Insts,
1168     FeatureDsSrc2Insts,
1169     FeatureLdsMisalignedBug,
1170     FeatureSupportsXNACK,
1171     FeatureBackOffBarrier])>;
1172
1173def FeatureISAVersion10_3_0 : FeatureSet<
1174  [FeatureGFX10,
1175   FeatureGFX10_AEncoding,
1176   FeatureGFX10_BEncoding,
1177   FeatureGFX10_3Insts,
1178   FeatureLDSBankCount32,
1179   FeatureDLInsts,
1180   FeatureDot1Insts,
1181   FeatureDot2Insts,
1182   FeatureDot5Insts,
1183   FeatureDot6Insts,
1184   FeatureDot7Insts,
1185   FeatureNSAEncoding,
1186   FeatureNSAMaxSize13,
1187   FeatureWavefrontSize32,
1188   FeatureShaderCyclesRegister,
1189   FeatureBackOffBarrier]>;
1190
1191//===----------------------------------------------------------------------===//
1192
1193def AMDGPUInstrInfo : InstrInfo {
1194  let guessInstructionProperties = 1;
1195  let noNamedPositionallyEncodedOperands = 1;
1196}
1197
1198def AMDGPUAsmParser : AsmParser {
1199  // Some of the R600 registers have the same name, so this crashes.
1200  // For example T0_XYZW and T0_XY both have the asm name T0.
1201  let ShouldEmitMatchRegisterName = 0;
1202}
1203
1204def AMDGPUAsmWriter : AsmWriter {
1205  int PassSubtarget = 1;
1206}
1207
1208def AMDGPUAsmVariants {
1209  string Default = "Default";
1210  int Default_ID = 0;
1211  string VOP3 = "VOP3";
1212  int VOP3_ID = 1;
1213  string SDWA = "SDWA";
1214  int SDWA_ID = 2;
1215  string SDWA9 = "SDWA9";
1216  int SDWA9_ID = 3;
1217  string DPP = "DPP";
1218  int DPP_ID = 4;
1219  string Disable = "Disable";
1220  int Disable_ID = 5;
1221}
1222
1223def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
1224  let Variant = AMDGPUAsmVariants.Default_ID;
1225  let Name = AMDGPUAsmVariants.Default;
1226}
1227
1228def VOP3AsmParserVariant : AsmParserVariant {
1229  let Variant = AMDGPUAsmVariants.VOP3_ID;
1230  let Name = AMDGPUAsmVariants.VOP3;
1231}
1232
1233def SDWAAsmParserVariant : AsmParserVariant {
1234  let Variant = AMDGPUAsmVariants.SDWA_ID;
1235  let Name = AMDGPUAsmVariants.SDWA;
1236}
1237
1238def SDWA9AsmParserVariant : AsmParserVariant {
1239  let Variant = AMDGPUAsmVariants.SDWA9_ID;
1240  let Name = AMDGPUAsmVariants.SDWA9;
1241}
1242
1243
1244def DPPAsmParserVariant : AsmParserVariant {
1245  let Variant = AMDGPUAsmVariants.DPP_ID;
1246  let Name = AMDGPUAsmVariants.DPP;
1247}
1248
1249def AMDGPU : Target {
1250  // Pull in Instruction Info:
1251  let InstructionSet = AMDGPUInstrInfo;
1252  let AssemblyParsers = [AMDGPUAsmParser];
1253  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
1254                                VOP3AsmParserVariant,
1255                                SDWAAsmParserVariant,
1256                                SDWA9AsmParserVariant,
1257                                DPPAsmParserVariant];
1258  let AssemblyWriters = [AMDGPUAsmWriter];
1259  let AllowRegisterRenaming = 1;
1260}
1261
1262// Dummy Instruction itineraries for pseudo instructions
1263def ALU_NULL : FuncUnit;
1264def NullALU : InstrItinClass;
1265
1266//===----------------------------------------------------------------------===//
1267// Predicate helper class
1268//===----------------------------------------------------------------------===//
1269
1270def isGFX6 :
1271  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
1272  AssemblerPredicate<(all_of FeatureSouthernIslands)>;
1273
1274def isGFX6GFX7 :
1275  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1276            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1277  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), (not FeatureGFX10Insts))>;
1278
1279def isGFX6GFX7GFX10 :
1280  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1281            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1282            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1283  AssemblerPredicate<(all_of (not FeatureGCN3Encoding))>;
1284
1285def isGFX7Only :
1286  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1287  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts, (not FeatureGFX10Insts))>;
1288
1289def isGFX7GFX10 :
1290  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1291            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1292  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts)>;
1293
1294def isGFX7GFX8GFX9 :
1295  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1296            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1297            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1298  AssemblerPredicate<(all_of FeatureGFX7GFX8GFX9Insts)>;
1299
1300def isGFX6GFX7GFX8GFX9 :
1301  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1302            "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1303            "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1304            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1305  AssemblerPredicate<(all_of (not FeatureGFX10Insts))>;
1306
1307def isGFX6GFX7GFX8GFX9NotGFX90A :
1308  Predicate<"!Subtarget->hasGFX90AInsts() &&"
1309            "(Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1310            " Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1311            " Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1312            " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1313  AssemblerPredicate<(all_of (not FeatureGFX10Insts), (not FeatureGFX90AInsts))>;
1314
1315def isGFX7Plus :
1316  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
1317  AssemblerPredicate<(all_of FeatureCIInsts)>;
1318
1319def isGFX8Plus :
1320  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1321  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1322
1323def isGFX8Only : Predicate<"Subtarget->getGeneration() =="
1324                           "AMDGPUSubtarget::VOLCANIC_ISLANDS">,
1325  AssemblerPredicate <(all_of FeatureVolcanicIslands)>;
1326
1327def isGFX9Plus :
1328  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1329  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1330
1331def isGFX9Only : Predicate <
1332  "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1333  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts)>;
1334
1335def isGCN3ExcludingGFX90A :
1336  Predicate<"Subtarget->isGCN3Encoding() && !Subtarget->hasGFX90AInsts()">,
1337  AssemblerPredicate<(all_of FeatureGCN3Encoding, (not FeatureGFX90AInsts))>;
1338
1339def isGFX90APlus :
1340  Predicate<"Subtarget->hasGFX90AInsts()">,
1341  AssemblerPredicate<(all_of FeatureGFX90AInsts)>;
1342
1343def isNotGFX90APlus :
1344  Predicate<"!Subtarget->hasGFX90AInsts()">,
1345  AssemblerPredicate<(all_of (not FeatureGFX90AInsts))>;
1346
1347def isGFX8GFX9NotGFX90A :
1348  Predicate<"!Subtarget->hasGFX90AInsts() &&"
1349            "(Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1350            " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1351  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding, (not FeatureGFX90AInsts))>;
1352
1353def isGFX90AOnly :
1354  Predicate<"Subtarget->hasGFX90AInsts() && !Subtarget->hasGFX940Insts()">,
1355  AssemblerPredicate<(all_of FeatureGFX90AInsts, (not FeatureGFX940Insts))>;
1356
1357def isGFX908orGFX90A :
1358  Predicate<"Subtarget->hasMAIInsts() && !Subtarget->hasGFX940Insts()">,
1359  AssemblerPredicate<(all_of FeatureMAIInsts, (not FeatureGFX940Insts))>;
1360
1361def isGFX940Plus :
1362  Predicate<"Subtarget->hasGFX940Insts()">,
1363  AssemblerPredicate<(all_of FeatureGFX940Insts)>;
1364
1365def isGFX8GFX9NotGFX940 :
1366  Predicate<"!Subtarget->hasGFX940Insts() &&"
1367            "(Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1368            " Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)">,
1369  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding, (not FeatureGFX940Insts))>;
1370
1371def isGFX8GFX9 :
1372  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||"
1373            "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">,
1374  AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding)>;
1375
1376def isGFX10Plus :
1377  Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
1378  AssemblerPredicate<(all_of FeatureGFX10Insts)>;
1379
1380def isGFX10Before1030 :
1381  Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX10 &&"
1382            "!Subtarget->hasGFX10_3Insts()">,
1383  AssemblerPredicate<(all_of FeatureGFX10Insts,(not FeatureGFX10_3Insts))>;
1384
1385def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
1386  AssemblerPredicate<(all_of FeatureFlatAddressSpace)>;
1387
1388def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
1389  AssemblerPredicate<(all_of FeatureFlatGlobalInsts)>;
1390def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
1391  AssemblerPredicate<(all_of FeatureFlatScratchInsts)>;
1392def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">,
1393  AssemblerPredicate<(all_of FeatureScalarFlatScratchInsts)>;
1394def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
1395  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1396
1397def HasFlatScratchSTMode : Predicate<"Subtarget->hasFlatScratchSTMode()">,
1398  AssemblerPredicate<(any_of FeatureGFX10_3Insts, FeatureGFX940Insts)>;
1399def HasFlatScratchSVSMode : Predicate<"Subtarget->hasFlatScratchSVSMode()">,
1400  AssemblerPredicate<(any_of FeatureGFX940Insts)>;
1401
1402def HasGFX10_AEncoding : Predicate<"Subtarget->hasGFX10_AEncoding()">,
1403  AssemblerPredicate<(all_of FeatureGFX10_AEncoding)>;
1404
1405def HasGFX10_BEncoding : Predicate<"Subtarget->hasGFX10_BEncoding()">,
1406  AssemblerPredicate<(all_of FeatureGFX10_BEncoding)>;
1407
1408def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
1409  AssemblerPredicate<(all_of FeatureUnpackedD16VMem)>;
1410def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
1411  AssemblerPredicate<(all_of (not FeatureUnpackedD16VMem))>;
1412
1413def D16PreservesUnusedBits :
1414  Predicate<"Subtarget->d16PreservesUnusedBits()">,
1415  AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureSRAMECC))>;
1416
1417def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
1418def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
1419
1420def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
1421  AssemblerPredicate<(all_of FeatureGFX9Insts)>;
1422
1423def HasLDSFPAtomicAdd : Predicate<"Subtarget->hasLDSFPAtomicAdd()">,
1424  AssemblerPredicate<(all_of FeatureGFX8Insts)>;
1425
1426def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
1427  AssemblerPredicate<(all_of FeatureAddNoCarryInsts)>;
1428
1429def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">;
1430
1431def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
1432  AssemblerPredicate<(all_of Feature16BitInsts)>;
1433def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
1434  AssemblerPredicate<(all_of FeatureVOP3P)>;
1435
1436def HasMinMaxDenormModes : Predicate<"Subtarget->supportsMinMaxDenormModes()">;
1437def NotHasMinMaxDenormModes : Predicate<"!Subtarget->supportsMinMaxDenormModes()">;
1438
1439def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
1440  AssemblerPredicate<(all_of FeatureSDWA, FeatureVolcanicIslands)>;
1441
1442def HasSDWA9 :
1443  Predicate<"Subtarget->hasSDWA()">,
1444  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts,FeatureSDWA)>;
1445
1446def HasSDWA10 :
1447  Predicate<"Subtarget->hasSDWA()">,
1448  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureSDWA)>;
1449
1450def HasDPP : Predicate<"Subtarget->hasDPP()">,
1451  AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureDPP)>;
1452
1453def HasDPP8 : Predicate<"Subtarget->hasDPP8()">,
1454  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP8)>;
1455
1456def Has64BitDPP : Predicate<"Subtarget->has64BitDPP()">,
1457  AssemblerPredicate<(all_of Feature64BitDPP)>;
1458
1459def HasPackedFP32Ops : Predicate<"Subtarget->hasPackedFP32Ops()">,
1460  AssemblerPredicate<(all_of FeaturePackedFP32Ops)>;
1461
1462def HasFmaakFmamkF32Insts :
1463  Predicate<"Subtarget->hasFmaakFmamkF32Insts()">,
1464  AssemblerPredicate<(any_of FeatureGFX10Insts, FeatureGFX940Insts)>;
1465
1466def HasImageInsts : Predicate<"Subtarget->hasImageInsts()">,
1467  AssemblerPredicate<(all_of FeatureImageInsts)>;
1468
1469def HasExtendedImageInsts : Predicate<"Subtarget->hasExtendedImageInsts()">,
1470  AssemblerPredicate<(all_of FeatureExtendedImageInsts)>;
1471
1472def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
1473  AssemblerPredicate<(all_of FeatureR128A16)>;
1474
1475def HasGFX10A16 : Predicate<"Subtarget->hasGFX10A16()">,
1476  AssemblerPredicate<(all_of FeatureGFX10A16)>;
1477
1478def HasG16 : Predicate<"Subtarget->hasG16()">,
1479  AssemblerPredicate<(all_of FeatureG16)>;
1480
1481def HasDPP16 : Predicate<"Subtarget->hasDPP()">,
1482  AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP)>;
1483
1484def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
1485  AssemblerPredicate<(all_of FeatureIntClamp)>;
1486
1487def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
1488  AssemblerPredicate<(all_of FeatureMadMixInsts)>;
1489
1490def HasScalarStores : Predicate<"Subtarget->hasScalarStores()">,
1491  AssemblerPredicate<(all_of FeatureScalarStores)>;
1492
1493def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
1494  AssemblerPredicate<(all_of FeatureScalarAtomics)>;
1495
1496def HasNoSdstCMPX : Predicate<"Subtarget->hasNoSdstCMPX()">,
1497  AssemblerPredicate<(all_of FeatureNoSdstCMPX)>;
1498
1499def HasSdstCMPX : Predicate<"!Subtarget->hasNoSdstCMPX()">,
1500  AssemblerPredicate<(all_of (not FeatureNoSdstCMPX))>;
1501
1502def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
1503def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
1504def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
1505                      AssemblerPredicate<(all_of FeatureVGPRIndexMode)>;
1506def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
1507                AssemblerPredicate<(all_of FeatureMovrel)>;
1508
1509def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
1510  AssemblerPredicate<(all_of FeatureFmaMixInsts)>;
1511
1512def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
1513  AssemblerPredicate<(all_of FeatureDLInsts)>;
1514
1515def HasDot1Insts : Predicate<"Subtarget->hasDot1Insts()">,
1516  AssemblerPredicate<(all_of FeatureDot1Insts)>;
1517
1518def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">,
1519  AssemblerPredicate<(all_of FeatureDot2Insts)>;
1520
1521def HasDot3Insts : Predicate<"Subtarget->hasDot3Insts()">,
1522  AssemblerPredicate<(all_of FeatureDot3Insts)>;
1523
1524def HasDot4Insts : Predicate<"Subtarget->hasDot4Insts()">,
1525  AssemblerPredicate<(all_of FeatureDot4Insts)>;
1526
1527def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">,
1528  AssemblerPredicate<(all_of FeatureDot5Insts)>;
1529
1530def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">,
1531  AssemblerPredicate<(all_of FeatureDot6Insts)>;
1532
1533def HasDot7Insts : Predicate<"Subtarget->hasDot7Insts()">,
1534  AssemblerPredicate<(all_of FeatureDot7Insts)>;
1535
1536def HasGetWaveIdInst : Predicate<"Subtarget->hasGetWaveIdInst()">,
1537  AssemblerPredicate<(all_of FeatureGetWaveIdInst)>;
1538
1539def HasMAIInsts : Predicate<"Subtarget->hasMAIInsts()">,
1540  AssemblerPredicate<(all_of FeatureMAIInsts)>;
1541
1542def HasSMemRealTime : Predicate<"Subtarget->hasSMemRealTime()">,
1543  AssemblerPredicate<(all_of FeatureSMemRealTime)>;
1544
1545def HasSMemTimeInst : Predicate<"Subtarget->hasSMemTimeInst()">,
1546  AssemblerPredicate<(all_of FeatureSMemTimeInst)>;
1547
1548def HasShaderCyclesRegister : Predicate<"Subtarget->hasShaderCyclesRegister()">,
1549  AssemblerPredicate<(all_of FeatureShaderCyclesRegister)>;
1550
1551def HasPkFmacF16Inst : Predicate<"Subtarget->hasPkFmacF16Inst()">,
1552  AssemblerPredicate<(all_of FeaturePkFmacF16Inst)>;
1553
1554def HasMadMacF32Insts : Predicate<"Subtarget->hasMadMacF32Insts()">,
1555  AssemblerPredicate<(all_of FeatureMadMacF32Insts)>;
1556
1557def HasFmaLegacy32 : Predicate<"Subtarget->hasGFX10_3Insts()">,
1558  AssemblerPredicate<(any_of FeatureGFX10_3Insts)>;
1559
1560def HasAtomicFaddInsts : Predicate<"Subtarget->hasAtomicFaddInsts()">,
1561  AssemblerPredicate<(all_of FeatureAtomicFaddInsts)>;
1562
1563def HasDsSrc2Insts : Predicate<"!Subtarget->hasDsSrc2Insts()">,
1564  AssemblerPredicate<(all_of FeatureDsSrc2Insts)>;
1565
1566def EnableLateCFGStructurize : Predicate<
1567  "EnableLateStructurizeCFG">;
1568
1569def EnableFlatScratch : Predicate<"Subtarget->enableFlatScratch()">;
1570
1571def DisableFlatScratch : Predicate<"!Subtarget->enableFlatScratch()">;
1572
1573def HasUnalignedAccessMode : Predicate<"Subtarget->hasUnalignedAccessMode()">,
1574  AssemblerPredicate<(all_of FeatureUnalignedAccessMode)>;
1575
1576// Include AMDGPU TD files
1577include "SISchedule.td"
1578include "GCNProcessors.td"
1579include "AMDGPUInstrInfo.td"
1580include "SIRegisterInfo.td"
1581include "AMDGPURegisterBanks.td"
1582include "AMDGPUInstructions.td"
1583include "SIInstrInfo.td"
1584include "AMDGPUCallingConv.td"
1585include "AMDGPUSearchableTables.td"
1586