1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===------------------------------------------------------------===//
9
10include "llvm/Target/Target.td"
11
12//===------------------------------------------------------------===//
13// Subtarget Features (device properties)
14//===------------------------------------------------------------===//
15
16def FeatureFP64 : SubtargetFeature<"fp64",
17  "FP64",
18  "true",
19  "Enable double precision operations"
20>;
21
22def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
23  "FastFMAF32",
24  "true",
25  "Assuming f32 fma is at least as fast as mul + add"
26>;
27
28def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
29  "HalfRate64Ops",
30  "true",
31  "Most fp64 instructions are half rate instead of quarter"
32>;
33
34def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
35  "R600ALUInst",
36  "false",
37  "Older version of ALU instructions encoding"
38>;
39
40def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
41  "HasVertexCache",
42  "true",
43  "Specify use of dedicated vertex cache"
44>;
45
46def FeatureCaymanISA : SubtargetFeature<"caymanISA",
47  "CaymanISA",
48  "true",
49  "Use Cayman ISA"
50>;
51
52def FeatureCFALUBug : SubtargetFeature<"cfalubug",
53  "CFALUBug",
54  "true",
55  "GPU has CF_ALU bug"
56>;
57
58def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
59  "FlatAddressSpace",
60  "true",
61  "Support flat address space"
62>;
63
64def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
65  "FlatInstOffsets",
66  "true",
67  "Flat instructions have immediate offset addressing mode"
68>;
69
70def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
71  "FlatGlobalInsts",
72  "true",
73  "Have global_* flat memory instructions"
74>;
75
76def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
77  "FlatScratchInsts",
78  "true",
79  "Have scratch_* flat memory instructions"
80>;
81
82def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
83  "AddNoCarryInsts",
84  "true",
85  "Have VALU add/sub instructions without carry out"
86>;
87
88def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
89  "UnalignedBufferAccess",
90  "true",
91  "Support unaligned global loads and stores"
92>;
93
94def FeatureTrapHandler: SubtargetFeature<"trap-handler",
95  "TrapHandler",
96  "true",
97  "Trap handler support"
98>;
99
100def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
101  "UnalignedScratchAccess",
102  "true",
103  "Support unaligned scratch loads and stores"
104>;
105
106def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
107  "HasApertureRegs",
108  "true",
109  "Has Memory Aperture Base and Size Registers"
110>;
111
112// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
113// XNACK. The current default kernel driver setting is:
114// - graphics ring: XNACK disabled
115// - compute ring: XNACK enabled
116//
117// If XNACK is enabled, the VMEM latency can be worse.
118// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
119def FeatureXNACK : SubtargetFeature<"xnack",
120  "EnableXNACK",
121  "true",
122  "Enable XNACK support"
123>;
124
125def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
126  "SGPRInitBug",
127  "true",
128  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
129>;
130
131class SubtargetFeatureFetchLimit <string Value> :
132                          SubtargetFeature <"fetch"#Value,
133  "TexVTXClauseSize",
134  Value,
135  "Limit the maximum number of fetches in a clause to "#Value
136>;
137
138def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
139def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
140
141class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
142  "wavefrontsize"#Value,
143  "WavefrontSize",
144  !cast<string>(Value),
145  "The number of threads per wavefront"
146>;
147
148def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
149def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
150def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
151
152class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
153  "ldsbankcount"#Value,
154  "LDSBankCount",
155  !cast<string>(Value),
156  "The number of LDS banks per compute unit."
157>;
158
159def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
160def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
161
162class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
163  "localmemorysize"#Value,
164  "LocalMemorySize",
165  !cast<string>(Value),
166  "The size of local memory in bytes"
167>;
168
169def FeatureGCN : SubtargetFeature<"gcn",
170  "IsGCN",
171  "true",
172  "GCN or newer GPU"
173>;
174
175def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
176  "GCN3Encoding",
177  "true",
178  "Encoding format for VI"
179>;
180
181def FeatureCIInsts : SubtargetFeature<"ci-insts",
182  "CIInsts",
183  "true",
184  "Additional instructions for CI+"
185>;
186
187def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
188  "GFX9Insts",
189  "true",
190  "Additional instructions for GFX9+"
191>;
192
193def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
194  "HasSMemRealTime",
195  "true",
196  "Has s_memrealtime instruction"
197>;
198
199def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
200  "HasInv2PiInlineImm",
201  "true",
202  "Has 1 / (2 * pi) as inline immediate"
203>;
204
205def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
206  "Has16BitInsts",
207  "true",
208  "Has i16/f16 instructions"
209>;
210
211def FeatureVOP3P : SubtargetFeature<"vop3p",
212  "HasVOP3PInsts",
213  "true",
214  "Has VOP3P packed instructions"
215>;
216
217def FeatureMovrel : SubtargetFeature<"movrel",
218  "HasMovrel",
219  "true",
220  "Has v_movrel*_b32 instructions"
221>;
222
223def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
224  "HasVGPRIndexMode",
225  "true",
226  "Has VGPR mode register indexing"
227>;
228
229def FeatureScalarStores : SubtargetFeature<"scalar-stores",
230  "HasScalarStores",
231  "true",
232  "Has store scalar memory instructions"
233>;
234
235def FeatureSDWA : SubtargetFeature<"sdwa",
236  "HasSDWA",
237  "true",
238  "Support SDWA (Sub-DWORD Addressing) extension"
239>;
240
241def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
242  "HasSDWAOmod",
243  "true",
244  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
245>;
246
247def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
248  "HasSDWAScalar",
249  "true",
250  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
251>;
252
253def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
254  "HasSDWASdst",
255  "true",
256  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
257>;
258
259def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
260  "HasSDWAMac",
261  "true",
262  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
263>;
264
265def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
266  "HasSDWAOutModsVOPC",
267  "true",
268  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
269>;
270
271def FeatureDPP : SubtargetFeature<"dpp",
272  "HasDPP",
273  "true",
274  "Support DPP (Data Parallel Primitives) extension"
275>;
276
277def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
278  "HasIntClamp",
279  "true",
280  "Support clamp for integer destination"
281>;
282
283//===------------------------------------------------------------===//
284// Subtarget Features (options and debugging)
285//===------------------------------------------------------------===//
286
287// Some instructions do not support denormals despite this flag. Using
288// fp32 denormals also causes instructions to run at the double
289// precision rate for the device.
290def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
291  "FP32Denormals",
292  "true",
293  "Enable single precision denormal handling"
294>;
295
296// Denormal handling for fp64 and fp16 is controlled by the same
297// config register when fp16 supported.
298// TODO: Do we need a separate f16 setting when not legal?
299def FeatureFP64FP16Denormals : SubtargetFeature<"fp64-fp16-denormals",
300  "FP64FP16Denormals",
301  "true",
302  "Enable double and half precision denormal handling",
303  [FeatureFP64]
304>;
305
306def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
307  "FP64FP16Denormals",
308  "true",
309  "Enable double and half precision denormal handling",
310  [FeatureFP64, FeatureFP64FP16Denormals]
311>;
312
313def FeatureFP16Denormals : SubtargetFeature<"fp16-denormals",
314  "FP64FP16Denormals",
315  "true",
316  "Enable half precision denormal handling",
317  [FeatureFP64FP16Denormals]
318>;
319
320def FeatureDX10Clamp : SubtargetFeature<"dx10-clamp",
321  "DX10Clamp",
322  "true",
323  "clamp modifier clamps NaNs to 0.0"
324>;
325
326def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
327  "FPExceptions",
328  "true",
329  "Enable floating point exceptions"
330>;
331
332class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
333  "max-private-element-size-"#size,
334  "MaxPrivateElementSize",
335  !cast<string>(size),
336  "Maximum private access size may be "#size
337>;
338
339def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
340def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
341def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
342
343def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
344  "EnableVGPRSpilling",
345  "true",
346  "Enable spilling of VGPRs to scratch memory"
347>;
348
349def FeatureDumpCode : SubtargetFeature <"DumpCode",
350  "DumpCode",
351  "true",
352  "Dump MachineInstrs in the CodeEmitter"
353>;
354
355def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
356  "DumpCode",
357  "true",
358  "Dump MachineInstrs in the CodeEmitter"
359>;
360
361def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
362  "EnablePromoteAlloca",
363  "true",
364  "Enable promote alloca pass"
365>;
366
367// XXX - This should probably be removed once enabled by default
368def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
369  "EnableLoadStoreOpt",
370  "true",
371  "Enable SI load/store optimizer pass"
372>;
373
374// Performance debugging feature. Allow using DS instruction immediate
375// offsets even if the base pointer can't be proven to be base. On SI,
376// base pointer values that won't give the same result as a 16-bit add
377// are not safe to fold, but this will override the conservative test
378// for the base pointer.
379def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
380  "unsafe-ds-offset-folding",
381  "EnableUnsafeDSOffsetFolding",
382  "true",
383  "Force using DS instruction immediate offsets on SI"
384>;
385
386def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
387  "EnableSIScheduler",
388  "true",
389  "Enable SI Machine Scheduler"
390>;
391
392// Unless +-flat-for-global is specified, turn on FlatForGlobal for
393// all OS-es on VI and newer hardware to avoid assertion failures due
394// to missing ADDR64 variants of MUBUF instructions.
395// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
396// instructions.
397
398def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
399  "FlatForGlobal",
400  "true",
401  "Force to generate flat instruction for global"
402>;
403
404def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
405  "auto-waitcnt-before-barrier",
406  "AutoWaitcntBeforeBarrier",
407  "true",
408  "Hardware automatically inserts waitcnt before barrier"
409>;
410
411// Dummy feature used to disable assembler instructions.
412def FeatureDisable : SubtargetFeature<"",
413  "FeatureDisable","true",
414  "Dummy feature to disable assembler instructions"
415>;
416
417class SubtargetFeatureGeneration <string Value,
418                                  list<SubtargetFeature> Implies> :
419        SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
420                          Value#" GPU generation", Implies>;
421
422def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
423def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
424def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
425
426def FeatureR600 : SubtargetFeatureGeneration<"R600",
427  [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]
428>;
429
430def FeatureR700 : SubtargetFeatureGeneration<"R700",
431  [FeatureFetchLimit16, FeatureLocalMemorySize0]
432>;
433
434def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
435  [FeatureFetchLimit16, FeatureLocalMemorySize32768]
436>;
437
438def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
439  [FeatureFetchLimit16, FeatureWavefrontSize64,
440   FeatureLocalMemorySize32768]
441>;
442
443def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
444  [FeatureFP64, FeatureLocalMemorySize32768,
445  FeatureWavefrontSize64, FeatureGCN,
446  FeatureLDSBankCount32, FeatureMovrel]
447>;
448
449def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
450  [FeatureFP64, FeatureLocalMemorySize65536,
451  FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
452  FeatureCIInsts, FeatureMovrel]
453>;
454
455def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
456  [FeatureFP64, FeatureLocalMemorySize65536,
457   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
458   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
459   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
460   FeatureScalarStores, FeatureInv2PiInlineImm,
461   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
462   FeatureIntClamp
463  ]
464>;
465
466def FeatureGFX9 : SubtargetFeatureGeneration<"GFX9",
467  [FeatureFP64, FeatureLocalMemorySize65536,
468   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
469   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
470   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
471   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
472   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
473   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
474   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
475   FeatureAddNoCarryInsts
476  ]
477>;
478
479class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping,
480                                  list<SubtargetFeature> Implies>
481                                 : SubtargetFeature <
482  "isaver"#Major#"."#Minor#"."#Stepping,
483  "IsaVersion",
484  "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
485  "Instruction set version number",
486  Implies
487>;
488
489def FeatureISAVersion6_0_0 : SubtargetFeatureISAVersion <6,0,0,
490  [FeatureSouthernIslands,
491   FeatureFastFMAF32,
492   HalfRate64Ops,
493   FeatureLDSBankCount32]>;
494
495def FeatureISAVersion6_0_1 : SubtargetFeatureISAVersion <6,0,1,
496  [FeatureSouthernIslands,
497   FeatureLDSBankCount32]>;
498
499def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0,
500  [FeatureSeaIslands,
501   FeatureLDSBankCount32]>;
502
503def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1,
504  [FeatureSeaIslands,
505   HalfRate64Ops,
506   FeatureLDSBankCount32,
507   FeatureFastFMAF32]>;
508
509def FeatureISAVersion7_0_2 : SubtargetFeatureISAVersion <7,0,2,
510  [FeatureSeaIslands,
511   FeatureLDSBankCount16]>;
512
513def FeatureISAVersion7_0_3 : SubtargetFeatureISAVersion <7,0,3,
514  [FeatureSeaIslands,
515   FeatureLDSBankCount16]>;
516
517def FeatureISAVersion8_0_0 : SubtargetFeatureISAVersion <8,0,0,
518  [FeatureVolcanicIslands,
519   FeatureLDSBankCount32,
520   FeatureSGPRInitBug]>;
521
522def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1,
523  [FeatureVolcanicIslands,
524   FeatureFastFMAF32,
525   HalfRate64Ops,
526   FeatureLDSBankCount32,
527   FeatureXNACK]>;
528
529def FeatureISAVersion8_0_2 : SubtargetFeatureISAVersion <8,0,2,
530  [FeatureVolcanicIslands,
531   FeatureLDSBankCount32,
532   FeatureSGPRInitBug]>;
533
534def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3,
535  [FeatureVolcanicIslands,
536   FeatureLDSBankCount32]>;
537
538def FeatureISAVersion8_0_4 : SubtargetFeatureISAVersion <8,0,4,
539  [FeatureVolcanicIslands,
540   FeatureLDSBankCount32]>;
541
542def FeatureISAVersion8_1_0 : SubtargetFeatureISAVersion <8,1,0,
543  [FeatureVolcanicIslands,
544   FeatureLDSBankCount16,
545   FeatureXNACK]>;
546
547def FeatureISAVersion9_0_0 : SubtargetFeatureISAVersion <9,0,0,
548  [FeatureGFX9,
549   FeatureLDSBankCount32]>;
550
551def FeatureISAVersion9_0_1 : SubtargetFeatureISAVersion <9,0,1,
552  [FeatureGFX9,
553   FeatureLDSBankCount32,
554   FeatureXNACK]>;
555
556def FeatureISAVersion9_0_2 : SubtargetFeatureISAVersion <9,0,2,
557  [FeatureGFX9,
558   FeatureLDSBankCount32]>;
559
560def FeatureISAVersion9_0_3 : SubtargetFeatureISAVersion <9,0,3,
561  [FeatureGFX9,
562   FeatureLDSBankCount32,
563   FeatureXNACK]>;
564
565//===----------------------------------------------------------------------===//
566// Debugger related subtarget features.
567//===----------------------------------------------------------------------===//
568
569def FeatureDebuggerInsertNops : SubtargetFeature<
570  "amdgpu-debugger-insert-nops",
571  "DebuggerInsertNops",
572  "true",
573  "Insert one nop instruction for each high level source statement"
574>;
575
576def FeatureDebuggerReserveRegs : SubtargetFeature<
577  "amdgpu-debugger-reserve-regs",
578  "DebuggerReserveRegs",
579  "true",
580  "Reserve registers for debugger usage"
581>;
582
583def FeatureDebuggerEmitPrologue : SubtargetFeature<
584  "amdgpu-debugger-emit-prologue",
585  "DebuggerEmitPrologue",
586  "true",
587  "Emit debugger prologue"
588>;
589
590//===----------------------------------------------------------------------===//
591
592def AMDGPUInstrInfo : InstrInfo {
593  let guessInstructionProperties = 1;
594  let noNamedPositionallyEncodedOperands = 1;
595}
596
597def AMDGPUAsmParser : AsmParser {
598  // Some of the R600 registers have the same name, so this crashes.
599  // For example T0_XYZW and T0_XY both have the asm name T0.
600  let ShouldEmitMatchRegisterName = 0;
601}
602
603def AMDGPUAsmWriter : AsmWriter {
604  int PassSubtarget = 1;
605}
606
607def AMDGPUAsmVariants {
608  string Default = "Default";
609  int Default_ID = 0;
610  string VOP3 = "VOP3";
611  int VOP3_ID = 1;
612  string SDWA = "SDWA";
613  int SDWA_ID = 2;
614  string SDWA9 = "SDWA9";
615  int SDWA9_ID = 3;
616  string DPP = "DPP";
617  int DPP_ID = 4;
618  string Disable = "Disable";
619  int Disable_ID = 5;
620}
621
622def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
623  let Variant = AMDGPUAsmVariants.Default_ID;
624  let Name = AMDGPUAsmVariants.Default;
625}
626
627def VOP3AsmParserVariant : AsmParserVariant {
628  let Variant = AMDGPUAsmVariants.VOP3_ID;
629  let Name = AMDGPUAsmVariants.VOP3;
630}
631
632def SDWAAsmParserVariant : AsmParserVariant {
633  let Variant = AMDGPUAsmVariants.SDWA_ID;
634  let Name = AMDGPUAsmVariants.SDWA;
635}
636
637def SDWA9AsmParserVariant : AsmParserVariant {
638  let Variant = AMDGPUAsmVariants.SDWA9_ID;
639  let Name = AMDGPUAsmVariants.SDWA9;
640}
641
642
643def DPPAsmParserVariant : AsmParserVariant {
644  let Variant = AMDGPUAsmVariants.DPP_ID;
645  let Name = AMDGPUAsmVariants.DPP;
646}
647
648def AMDGPU : Target {
649  // Pull in Instruction Info:
650  let InstructionSet = AMDGPUInstrInfo;
651  let AssemblyParsers = [AMDGPUAsmParser];
652  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
653                                VOP3AsmParserVariant,
654                                SDWAAsmParserVariant,
655                                SDWA9AsmParserVariant,
656                                DPPAsmParserVariant];
657  let AssemblyWriters = [AMDGPUAsmWriter];
658}
659
660// Dummy Instruction itineraries for pseudo instructions
661def ALU_NULL : FuncUnit;
662def NullALU : InstrItinClass;
663
664//===----------------------------------------------------------------------===//
665// Predicate helper class
666//===----------------------------------------------------------------------===//
667
668def TruePredicate : Predicate<"true">;
669
670def isSICI : Predicate<
671  "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
672  "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
673>, AssemblerPredicate<"!FeatureGCN3Encoding">;
674
675def isVI : Predicate <
676  "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
677  AssemblerPredicate<"FeatureGCN3Encoding">;
678
679def isGFX9 : Predicate <
680  "Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
681  AssemblerPredicate<"FeatureGFX9Insts">;
682
683// TODO: Either the name to be changed or we simply use IsCI!
684def isCIVI : Predicate <
685  "Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
686  AssemblerPredicate<"FeatureCIInsts">;
687
688def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
689  AssemblerPredicate<"FeatureFlatAddressSpace">;
690
691def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
692  AssemblerPredicate<"FeatureFlatGlobalInsts">;
693def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
694  AssemblerPredicate<"FeatureFlatScratchInsts">;
695def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
696  AssemblerPredicate<"FeatureGFX9Insts">;
697
698def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
699  AssemblerPredicate<"FeatureGFX9Insts">;
700
701def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarryInsts()">,
702  AssemblerPredicate<"FeatureAddNoCarryInsts">;
703
704def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarryInsts()">,
705  AssemblerPredicate<"!FeatureAddNoCarryInsts">;
706
707def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
708  AssemblerPredicate<"Feature16BitInsts">;
709def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
710  AssemblerPredicate<"FeatureVOP3P">;
711
712def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
713  AssemblerPredicate<"FeatureSDWA,FeatureVolcanicIslands">;
714
715def HasSDWA9 : Predicate<"Subtarget->hasSDWA()">,
716  AssemblerPredicate<"FeatureSDWA,FeatureGFX9">;
717
718def HasDPP : Predicate<"Subtarget->hasDPP()">,
719  AssemblerPredicate<"FeatureDPP">;
720
721def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
722  AssemblerPredicate<"FeatureIntClamp">;
723
724def HasMadMix : Predicate<"Subtarget->hasMadMixInsts()">,
725  AssemblerPredicate<"FeatureGFX9Insts">;
726
727
728// Exists to help track down where SubtargetPredicate isn't set rather
729// than letting tablegen crash with an unhelpful error.
730def InvalidPred : Predicate<"predicate not set on instruction or pattern">;
731
732class PredicateControl {
733  Predicate SubtargetPredicate = InvalidPred;
734  Predicate SIAssemblerPredicate = isSICI;
735  Predicate VIAssemblerPredicate = isVI;
736  list<Predicate> AssemblerPredicates = [];
737  Predicate AssemblerPredicate = TruePredicate;
738  list<Predicate> OtherPredicates = [];
739  list<Predicate> Predicates = !listconcat([SubtargetPredicate,
740                                            AssemblerPredicate],
741                                            AssemblerPredicates,
742                                            OtherPredicates);
743}
744
745class AMDGPUPat<dag pattern, dag result> : Pat<pattern, result>,
746  PredicateControl;
747
748
749// Include AMDGPU TD files
750include "R600Schedule.td"
751include "SISchedule.td"
752include "Processors.td"
753include "AMDGPUInstrInfo.td"
754include "AMDGPUIntrinsics.td"
755include "AMDGPURegisterInfo.td"
756include "AMDGPURegisterBanks.td"
757include "AMDGPUInstructions.td"
758include "AMDGPUCallingConv.td"
759